JPH07112939B2 - Anodic bonding method of silicon wafer and glass substrate - Google Patents
Anodic bonding method of silicon wafer and glass substrateInfo
- Publication number
- JPH07112939B2 JPH07112939B2 JP63293956A JP29395688A JPH07112939B2 JP H07112939 B2 JPH07112939 B2 JP H07112939B2 JP 63293956 A JP63293956 A JP 63293956A JP 29395688 A JP29395688 A JP 29395688A JP H07112939 B2 JPH07112939 B2 JP H07112939B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon wafer
- glass substrate
- conductor plate
- bonding method
- anodic bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Joining Of Glass To Other Materials (AREA)
- Pressure Sensors (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ この発明は、半導体デバイスの製作におけるシリコンウ
ェハとガラス基板の陽極接合法に関するものである。TECHNICAL FIELD The present invention relates to an anodic bonding method for a silicon wafer and a glass substrate in manufacturing a semiconductor device.
［従来の技術］ 第３図は、例えば特公昭53−28747号公報（D.I.ポメラ
ンツの発明）に示された接合法を示す構成断面図であ
る。図において（１）はシリコンウェハ、（２）はガラ
ス基板、（３）は陽極導体板、（４）は加熱ヒータ、
（５）は陰極導体板である。[Prior Art] FIG. 3 is a cross-sectional view showing a joining method shown in, for example, Japanese Patent Publication No. 53-28747 (invention of DI Pomeranz). In the figure, (1) is a silicon wafer, (2) is a glass substrate, (3) is an anode conductor plate, (4) is a heater,
(5) is a cathode conductor plate.
従来の半導体デバイス、例えばシリコンのピエゾ抵抗効
果を利用する半導体圧力センサー等は、その製作工程に
おいてシリコンウェハとガラス基板を接合した構造体と
して構成されるが、この構造体の接続方法として、陽極
接合法は極めて有効であることが知られている。シリコ
ンウェハ（１）とガラス基板（２）を加熱ヒータ（４）
で加熱し、シリコンウェハ側を陽極導体板（３）を通し
て陽極とし、ガラス基板側を同じく陰極導体板（５）を
通して陰極として直流電圧を印加し、接合する方法が行
われている。Conventional semiconductor devices, such as semiconductor pressure sensors that utilize the piezoresistive effect of silicon, are constructed as a structure in which a silicon wafer and a glass substrate are bonded in the manufacturing process. Legality is known to be extremely effective. Heater (4) for heating silicon wafer (1) and glass substrate (2)
Then, the silicon wafer side is used as an anode through the anode conductor plate (3), and the glass substrate side is also used as a cathode through the cathode conductor plate (5), and a DC voltage is applied to perform bonding.
［発明が解決しようとする課題］ 上記のような、従来のシリコンウェハとガラス基板の陽
極接合法においては、陰極導体板（５）をシリコンウェ
ハの中央部に設置した場合、接合の完結後、シリコン−
ガラス接合体のシリコンウェハとガラス基板界面におけ
る残留応力が第５図に示すごとく、その対向する真下で
ピークとなり、シリコンウェハ内での分布が不均一とな
ることである。このような大きな残留応力は、結合体ウ
エハのハンドリングによる破損及びダイシングによるチ
ップ分割時にしばしばクラックを発生し、歩留まり低下
の原因となるという問題点があった。[Problems to be Solved by the Invention] In the conventional anodic bonding method for a silicon wafer and a glass substrate as described above, when the cathode conductor plate (5) is installed in the central portion of the silicon wafer, after the bonding is completed, Silicon-
As shown in FIG. 5, the residual stress at the interface between the silicon wafer and the glass substrate of the glass bonded body has a peak just below the opposite surface, and the distribution in the silicon wafer becomes uneven. Such a large residual stress has a problem that breakage due to handling of the bonded body wafer and cracks often occur at the time of chip division due to dicing, which causes a decrease in yield.
この発明は、かかる問題点を解決するためになされたも
ので、シリコンウェハとガラス基板接合時に発生するシ
リコンとガラス界面の残留応力を減少し、かつ均一化し
て結合を達成することを目的とする。The present invention has been made to solve the above problems, and an object of the present invention is to reduce the residual stress at the interface between silicon and glass, which occurs at the time of bonding a silicon wafer and a glass substrate, and to make the bonding uniform to achieve bonding. .
［課題を解決するための手段］ この発明は、シリコンウェハとガラス基板の陽極接合時
における上記問題点を解決するため、ガラス基板の主面
にシリコンウェハを当接し、このガラス基板の他主面に
陰極導体板を当接し、上記シリコンウェハを陽極、上記
陰極導体板を陰極として、直流電圧を印加すると同時に
加熱し、上記シリコンウェハとガラス基板を接合する陽
極接合法において、上記ガラス基板の他主面に当接した
陰極導体板の当接位置を、シリコンウェハの外周部と対
向する位置に設けて電圧を印加し、接合を達成するよう
にしたものである。[Means for Solving the Problem] In order to solve the above-mentioned problems at the time of anodic bonding between a silicon wafer and a glass substrate, the present invention brings the silicon wafer into contact with the main surface of the glass substrate A cathode conductor plate is brought into contact with, the silicon wafer is used as an anode, the cathode conductor plate is used as a cathode, and a DC voltage is applied and simultaneously heated, and in the anodic bonding method of bonding the silicon wafer and the glass substrate to each other, The contact position of the cathode conductor plate that is in contact with the main surface is provided at a position facing the outer peripheral portion of the silicon wafer, and a voltage is applied to achieve bonding.
［作 用］ この発明における陽極接合法は、ガラス基板の他主面に
当接した陰極導体板の当接位置をシリコンウェハの外周
部と対向する位置に当接して電圧を印加し接合を達成す
ると、その実験結果からシリコンウェハとガラス基板界
面に発生する残留応力を減少させると共に、シリコンウ
ェハ面内での残留応力の分布の均一化を図ることができ
る。[Operation] In the anodic bonding method according to the present invention, the contact position of the cathode conductor plate which is in contact with the other main surface of the glass substrate is brought into contact with the position facing the outer peripheral portion of the silicon wafer to apply a voltage to achieve the bonding. Then, from the experimental results, it is possible to reduce the residual stress generated at the interface between the silicon wafer and the glass substrate and to make the distribution of the residual stress within the surface of the silicon wafer uniform.
［実施例］ 第１図はこの発明の一実施例を示す構成断面図であり、
シリコンウェハとガラス基板の陽極接合法において、加
熱ヒータ（４）上に同ヒータから電気的に絶縁された陽
極導体板（３）を設置し、その上に通常の半導体プロセ
スを経て回路を形成しているシリコンウェハ（１）、ま
たは未処理のシリコンウェハ（１）を載せ、シリコンと
熱膨張係数が近似する同サイズのホウケイ酸ガラス基板
（２）（例えばコーニング製商品名：パイレックスガラ
ス）を重ね、さらにその上に陰極導体板（５）をシリコ
ンウェハ（１）の外周部と対向する位置に設けて、接合
されるシリコンウェハ（１）及びガラス基板（２）を接
合に必要な所定の温度（例えば400〜450℃）に加熱ヒー
タ（４）で加熱し、陽極導体板（３）と陰極導体板
（５）の間に、直流電圧（例えば500〜1000V）を所定時
間（例えば10〜60分間）印加し、接合を達成して陽極導
体板（３）、及び陰極導体板（５）を取りはずし、シリ
コンウェハとガラス基板の接合を完成させる。[Embodiment] FIG. 1 is a sectional view showing the construction of an embodiment of the present invention.
In the anodic bonding method of a silicon wafer and a glass substrate, an anode conductor plate (3) electrically insulated from the heater (4) is placed on a heater (4), and a circuit is formed on it by a normal semiconductor process. A silicon wafer (1) or an untreated silicon wafer (1) on top of which a borosilicate glass substrate (2) of the same size that has a thermal expansion coefficient similar to that of silicon (for example, Corning product name: Pyrex glass) is stacked. Further, a cathode conductor plate (5) is further provided thereon at a position facing the outer peripheral portion of the silicon wafer (1), and the silicon wafer (1) and the glass substrate (2) to be bonded have a predetermined temperature necessary for bonding. (For example, 400 to 450 ° C.) is heated by a heater (4), and a direct current voltage (for example, 500 to 1000 V) is applied between the anode conductor plate (3) and the cathode conductor plate (5) for a predetermined time (for example, 10 to 60). Application) , Anode conductor plate to achieve a joint (3), and remove cathode conductor plate (5), to complete the bonding of the silicon wafer and the glass substrate.
従来のシリコンウェハとガラス基板の陽極接合法におい
ては、陰極導体板（５）をシリコンウェハの中央部に設
置しているため、接合の完結後、シリコン−ガラス接合
体のシリコンウェハとガラス基板界面における残留応力
が第５図に示すごとく、その対向する真下でピークとな
り、シリコンウェハ内での分布が不均一となっていた
が、この発明では第１図及びその平面図である第２図に
示したように、外周部に４×45mmの陰極導体板（５）を
設置した場合、シリコンウェハとガラス基板接合体のシ
リコンとガラス界面における残留応力は、その実験結果
から第４図に示すように電極直下ではピークとなるが、
そのピーク幅は、電極幅が細いため狭く、また、電極直
下より離れると急激に減少し、ウエハ面内では小さいレ
ベルで残留応力は均一となり、分布が改善され、シリコ
ンウェハ（１）とガラス基板（２）の接合完了後、陰極
導体板（５）直下以外では、均一でかつ減少して接合が
達成される。In the conventional anodic bonding method for a silicon wafer and a glass substrate, since the cathode conductor plate (5) is installed in the center of the silicon wafer, after the bonding is completed, the silicon wafer-glass substrate interface of the silicon-glass bonded body is completed. As shown in Fig. 5, the residual stress in Fig. 5 had a peak just below the opposite face, and the distribution in the silicon wafer was non-uniform. However, in the present invention, it is shown in Fig. 1 and Fig. 2 which is a plan view thereof. As shown, when the cathode conductor plate (5) of 4 × 45 mm is installed on the outer periphery, the residual stress at the silicon / glass interface of the silicon wafer / glass substrate assembly is shown in FIG. 4 from the experimental results. Although it peaks just below the electrode,
The peak width is narrow because the electrode width is narrow, and sharply decreases when it is separated from directly under the electrode, the residual stress becomes uniform at a small level within the wafer surface, the distribution is improved, and the silicon wafer (1) and the glass substrate are improved. After the completion of the bonding in (2), the bonding is achieved uniformly and reduced except under the cathode conductor plate (5).
［発明の効果］ この発明は、以上説明したように、ガラス基板の他主面
に当接した陰極導体板の当接位置を、シリコンウェハの
外周部と対向する位置に設けて接合を達成することによ
り、シリコンウェハとガラス基板接合体のシリコンとガ
ラス界面における残留応力を減少し、かつ均一化して接
合が達成できる。これは後プロセスにおける同接合体の
クラック及びデバイス特性のバラツキを防止することが
でき、また、同構造体のシリコンデバイスの歩留まりを
改善できる。[Effect of the Invention] As described above, the present invention achieves bonding by providing the contact position of the cathode conductor plate that contacts the other main surface of the glass substrate at a position facing the outer peripheral portion of the silicon wafer. As a result, the residual stress at the silicon / glass interface between the bonded body of the silicon wafer and the glass substrate can be reduced and uniformized to achieve the bonding. This makes it possible to prevent cracks in the same junction and variations in device characteristics in the subsequent process, and improve the yield of silicon devices having the same structure.
第１図はこの発明の一実施例によるシリコンウェハとガ
ラス基板の陽極接合法を説明する構成断面図、第２図は
その平面図である。第３図は従来のシリコンウェハとガ
ラス基板の陽極接合法を示す構成断面図である。 第４図はこの発明によるシリコンウェハとガラス基板接
合体のシリコンとガラス界面におけるウェハ面内の残留
応力分布図。第５図は従来法によるシリコンウェハとガ
ラス基板接合体のシリコンとガラス界面におけるウェハ
面内の残留応力分布図である。 図において（１）はシリコンウェハ、（２）はガラス基
板、（３）は陰極導体板、（４）は加熱ヒータ、（５）
は陰極導体板である。 なお、図中同一符号は同一又は相当部分を示す。FIG. 1 is a sectional view showing the construction of an anodic bonding method for a silicon wafer and a glass substrate according to an embodiment of the present invention, and FIG. 2 is a plan view thereof. FIG. 3 is a cross-sectional view of a structure showing a conventional anodic bonding method for a silicon wafer and a glass substrate. FIG. 4 is a residual stress distribution diagram in a wafer surface at a silicon / glass interface of a bonded body of a silicon wafer and a glass substrate according to the present invention. FIG. 5 is a residual stress distribution diagram in a wafer surface at a silicon / glass interface of a silicon wafer / glass substrate bonded body according to a conventional method. In the figure, (1) is a silicon wafer, (2) is a glass substrate, (3) is a cathode conductor plate, (4) is a heater, and (5) is.
Is a cathode conductor plate. The same reference numerals in the drawings indicate the same or corresponding parts.
Claims (1)
し、このガラス基板の他主面に陰極導体板を当接し、上
記シリコンウェハを陽極、上記陰極導体板を陰極とし
て、直流電圧を印加すると同時に加熱し、上記シリコン
ウェハとガラス基板を接合する陽極接合法において、上
記ガラス基板の他主面に当接した陰極導体板の当接位置
を、シリコンウェハの外周部の一部のみと対向する位置
に設けて電圧を印加し、接合を達成することを特徴とす
るシリコンウェハとガラス基板の陽極接合法。1. A silicon wafer is brought into contact with the main surface of a glass substrate, a cathode conductor plate is brought into contact with the other main surface of the glass substrate, and a DC voltage is applied with the silicon wafer as an anode and the cathode conductor plate as a cathode. In the anodic bonding method in which the silicon wafer and the glass substrate are heated at the same time, the contact position of the cathode conductor plate contacting the other main surface of the glass substrate is opposed to only a part of the outer peripheral portion of the silicon wafer. An anodic bonding method for a silicon wafer and a glass substrate, which is provided at a position where a voltage is applied to achieve bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63293956A JPH07112939B2 (en) | 1988-11-21 | 1988-11-21 | Anodic bonding method of silicon wafer and glass substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63293956A JPH07112939B2 (en) | 1988-11-21 | 1988-11-21 | Anodic bonding method of silicon wafer and glass substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02141442A JPH02141442A (en) | 1990-05-30 |
| JPH07112939B2 true JPH07112939B2 (en) | 1995-12-06 |
Family
ID=17801360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63293956A Expired - Fee Related JPH07112939B2 (en) | 1988-11-21 | 1988-11-21 | Anodic bonding method of silicon wafer and glass substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07112939B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2812405B2 (en) * | 1991-03-15 | 1998-10-22 | 信越半導体株式会社 | Semiconductor substrate manufacturing method |
| JP3383081B2 (en) * | 1994-07-12 | 2003-03-04 | 三菱電機株式会社 | Electronic component manufactured using anodic bonding and method of manufacturing electronic component |
| DE19741924C2 (en) * | 1997-09-23 | 2000-03-02 | Siemens Ag | Process for electrochemical connection and composite part |
| IT1320381B1 (en) * | 2000-05-29 | 2003-11-26 | Olivetti Lexikon Spa | METHOD FOR THE MANUFACTURE OF AN EJECTION HEAD OF DILQUID DROPS, PARTICULARLY SUITABLE FOR OPERATING WITH CHEMICALLY LIQUIDS |
| US6475326B2 (en) | 2000-12-13 | 2002-11-05 | Applied Materials, Inc. | Anodic bonding of a stack of conductive and glass layers |
| JP4871602B2 (en) * | 2005-01-25 | 2012-02-08 | 有限会社 テクノスキャン | Cane |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63229864A (en) * | 1987-03-19 | 1988-09-26 | Ishizuka Glass Ltd | Method of joining anode |
| JPS63229863A (en) * | 1987-03-19 | 1988-09-26 | Ishizuka Glass Ltd | Method of joining anode |
-
1988
- 1988-11-21 JP JP63293956A patent/JPH07112939B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02141442A (en) | 1990-05-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |