JPH02119233A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH02119233A
JPH02119233A JP63273610A JP27361088A JPH02119233A JP H02119233 A JPH02119233 A JP H02119233A JP 63273610 A JP63273610 A JP 63273610A JP 27361088 A JP27361088 A JP 27361088A JP H02119233 A JPH02119233 A JP H02119233A
Authority
JP
Japan
Prior art keywords
row
bonding pads
bonding
parallel
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63273610A
Other languages
English (en)
Inventor
Takumi Matsukura
松倉　巧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63273610A priority Critical patent/JPH02119233A/ja
Publication of JPH02119233A publication Critical patent/JPH02119233A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特にその外部端子の取り出
しを高密度に行う技術に関するものである。
〔従来の技術〕
従来この種の半導体装置は第３図に示すように、四角形
状のボンディングパッド２を半導体ベレット１の周辺に
一列に配置し、このボンディングパッド２とこれに対応
するボンディングリード３をボンディングワイヤ４で接
続した構造となっていた。
〔発明が解決しようとする課題〕
しかしながら上述した従来の半導体装置では、半導体ペ
レット内の回路素子の高密度化に伴いボンディングパッ
ド数も増加した場合、単にボンディングパッドを半導体
ベレットに一列に配置するのではボンディングパッド間
隔が狭くなって歩留が低下するか若しくはペレットサイ
ズの増大につながる。
またこのような四角形状のボンディングパッドについて
第１列、第２例というように２列に配置することも考え
られるが、この場合は第４図に示すようにボンディング
パッド２にボンディングする際に先にボンディングした
ワイヤ４とキャピラリー５が接触し、変形を生じる。あ
るいは、ワイヤとワイヤが接近してしまう為に、モール
ド封入時に圧入される樹脂によって変形を生じ隣接ワイ
ヤとの接触事故を生じる等の問題がある。この問題はペ
レットコーナ一部のペレット端に対する角度θが小さい
ワイヤはど顕著となる。
本発明の目的は多数のボンディングパッドを高密度に配
設することが可能な半導体装置を提供することにある。
〔課題を解決するための手段〕
本発明の半導体装置は、複数のボンディングパッドを所
定間隔で配置した互いに平行な第１の列及び第２の列を
有し、前記第１の列のボンディングパッドの間に対応す
る位置に前記第２の列のボンディングパッドを配置して
なり、前記ボンディングパッドの少なくとも一つは、半
導体ペレットの縁に平行な長辺を有する長方形であると
いうものである。
〔実施例〕
次に本発明について図面を参照して説明する。
第１図（ａ）は本発明の一実施例の平面図、第１図（ｂ
）は第１図（ａ）の部分拡大平面図である。
図に示す如く、ボンディングパッドを半導体ベレット１
の周辺に所定間隔を置いて列状に配置し、このようにし
て配列した第１の列のボンディングパッド２Ａ群に並行
に、半導体ベレット１の縁に並行な辺を長辺とする長方
形のボンディングパッド２Ｂを第１の列の各ボンディン
グパッド間に所定間隔を置いて複数個列状に配列して成
る。
この際の短辺と長辺の比はワイヤの角度にもよるが１：
２〜１：２．５程度あれば十分である。
このような構造において、ボンディングパッド２Ａ、２
Ｂとボンディングリード３の間をボンディングワイヤ４
で接続するのであるが、ペレットの中央部では、ボンデ
ィングパッドの中心に、ペレットコーナ一部では、第１
図（ｂ）に示すように、長方形のパッド（２Ｂ）のペレ
ット中心よりにボンディングすることにより、キャピラ
リー５のペレット面から一定の高さ（βで示す）におけ
る外径りの領域は隣接するワイヤと接触せず隣接するワ
イヤ間の距離も適正となる為にモールド封入時に圧入さ
れる樹脂による変形があっても、接触事故を防止できる
。
第２図は本発明の第２の実施例を示す平面図である。
この実施例は、第１の列のボンディングパッド２Ａ群、
第２列のボンディングパッド２Ｂ群とも形状を、半導体
ペレットの縁に平行な辺を長辺とする長方形となってい
る。この実施例では前述の第２の列のみに長方形パッド
を配置した第１の実施例と同様な利点を有することはも
ちろん、第１の列も長方形となっている為、ボンディン
グリードの位置によってパッド側のボンディング位置を
選択でき、同一種類の半導体ペレットを必要に応じて種
々のパッケージに搭載することも容易にすることができ
る利点がある。
〔発明の効果〕
以上説明したように本発明は、半導体ペレット上のボン
ディングパッドを第１の列と第２の列に分けて平行に配
置し、かつそれぞれの列のボンディングパッドの間に対
応する位置に他の列のボンディングパッドがくるように
配設することにより、パッドの高密度化を達成すると共
に、ボンディングパッド形状をペレットの縁に平行な辺
を長辺とする長方形とすることによってワイヤとキャピ
ラリーの接触を防止することができ、工程歩留を向上で
きるばかりでなく、信頼性も向上させることができる。
さらに、ボンディングパッドが長方形となっている為に
、ボンディング可能な範囲を選択できボンディングを容
易にできるばかりでなく、同一種類の半導体ペレットを
複数のパッケージに搭載することも容易になるという管
理上の効果もある。
【図面の簡単な説明】
第１図（ａ）、（ｂ）は本発明の第１の実施例を示すも
ので、第１図（ａ）は平面図、第１図（ｂ）はその部分
拡大図、第２図は第２の実施例を示す平面図である。第
３図、第４図は従来の半導体装置を示す平面図で第３図
は通常のパッド配置のもの、第４図は千鳥状のパッド配
置のものをそれぞれ示し、第５図はボンディング蒔のパ
ッドにワイヤを圧着する時のキャピラリーの位置、大き
さを説明するための断明図である。 １・・・半導体ペレット、２・・・ボンディングパッド
、２Ａ・・・第１の列のボンディングパッド、２Ｂ・・
・第２の列のボンディングパッド（長方形）、３・・・
ボンディングリード、４・・・ボンディングワイヤ、５
・・・キャピラリー　Ｄ・・・一定の高さｌにおけるキ
ャピラリーの外径。 鼻ど因 鼻３区 （Ｑ） （ｂ）

Claims (1)

    【特許請求の範囲】
  1. 複数のボンディングパッドを所定間隔で配置した互いに
    平行な第１の列及び第２の列を有し、前記第１の列のボ
    ンディングパッドの間に対応する位置に前記第２の列の
    ボンディングパッドを配置してなり、前記ボンィングパ
    ッドの少なくとも一つは、半導体ペレットの縁に平行な
    長辺を有する長方形であることを特徴とする半導体装置
    。
JP63273610A 1988-10-28 1988-10-28 半導体装置 Pending JPH02119233A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63273610A JPH02119233A (ja) 1988-10-28 1988-10-28 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63273610A JPH02119233A (ja) 1988-10-28 1988-10-28 半導体装置

Publications (1)

Publication Number Publication Date
JPH02119233A true JPH02119233A (ja) 1990-05-07

Family

ID=17530148

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63273610A Pending JPH02119233A (ja) 1988-10-28 1988-10-28 半導体装置

Country Status (1)

Country Link
JP (1) JPH02119233A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6307271B1 (en) 1999-04-27 2001-10-23 Oki Electric Industry Co., Ltd. Semiconductor device having pads, the intervals of which are adjusted and arranged in semiconductor chip corners
JP2010118428A (ja) * 2008-11-12 2010-05-27 Renesas Technology Corp 表示装置駆動用半導体集積回路装置および表示装置駆動用半導体集積回路装置の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6307271B1 (en) 1999-04-27 2001-10-23 Oki Electric Industry Co., Ltd. Semiconductor device having pads, the intervals of which are adjusted and arranged in semiconductor chip corners
US6476505B2 (en) 1999-04-27 2002-11-05 Oki Electric Industry Co, Ltd. Semiconductor device having pads, the intervals of which are adjusted and arranged in semiconductor chip corners
JP2010118428A (ja) * 2008-11-12 2010-05-27 Renesas Technology Corp 表示装置駆動用半導体集積回路装置および表示装置駆動用半導体集積回路装置の製造方法

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