JP7487213B2 - プロセッサおよびダイナミック・ランダムアクセス・メモリを有する接合半導体デバイスおよびそれを形成する方法 - Google Patents
プロセッサおよびダイナミック・ランダムアクセス・メモリを有する接合半導体デバイスおよびそれを形成する方法 Download PDFInfo
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- JP7487213B2 JP7487213B2 JP2021545730A JP2021545730A JP7487213B2 JP 7487213 B2 JP7487213 B2 JP 7487213B2 JP 2021545730 A JP2021545730 A JP 2021545730A JP 2021545730 A JP2021545730 A JP 2021545730A JP 7487213 B2 JP7487213 B2 JP 7487213B2
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- 239000004065 semiconductor Substances 0.000 title claims description 567
- 238000000034 method Methods 0.000 title claims description 85
- 235000012431 wafers Nutrition 0.000 claims description 132
- 230000002093 peripheral effect Effects 0.000 claims description 90
- 239000000758 substrate Substances 0.000 claims description 81
- 230000003068 static effect Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 411
- 239000003990 capacitor Substances 0.000 description 40
- 230000008569 process Effects 0.000 description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 32
- 229910052710 silicon Inorganic materials 0.000 description 32
- 239000010703 silicon Substances 0.000 description 32
- 238000004519 manufacturing process Methods 0.000 description 28
- 239000004020 conductor Substances 0.000 description 15
- 239000000463 material Substances 0.000 description 14
- 238000001312 dry etching Methods 0.000 description 13
- 230000015654 memory Effects 0.000 description 13
- 238000012546 transfer Methods 0.000 description 13
- 238000001039 wet etching Methods 0.000 description 13
- 239000003989 dielectric material Substances 0.000 description 12
- 238000002955 isolation Methods 0.000 description 12
- 230000006870 function Effects 0.000 description 11
- 238000000427 thin-film deposition Methods 0.000 description 11
- 239000010949 copper Substances 0.000 description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 239000000872 buffer Substances 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 230000010267 cellular communication Effects 0.000 description 3
- 230000001934 delay Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003190 augmentative effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001537 neural effect Effects 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
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-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
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- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/03452—Chemical vapour deposition [CVD], e.g. laser CVD
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
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- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
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- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1437—Static random-access memory [SRAM]
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Description
本願は、2019年4月15日に出願された「INTEGRATION OF THREE-DIMENSIONAL NAND MEMORY DEVICES WITH MULTIPLE FUNCTIONAL CHIPS」と題する国際出願第PCT/CN2019/082607号に対する優先権の利益を主張するものであり、その全体は参照により本明細書に組み込まれる。
Claims (19)
- 半導体デバイスであって、
トランジスタを含むプロセッサと、スタティック・ランダムアクセス・メモリ(SRAM)セルのアレイと、複数の第1の接合接点を含む第1の接合層とを有する第1の半導体構造と、
ダイナミック・ランダムアクセス・メモリ(DRAM)セルのアレイと、複数の第2の接合接点を含む第2の接合層とを有する第2の半導体構造と、
前記第1の接合層と前記第2の接合層との間の接合界面であって、前記第1の接合接点が前記接合界面で前記第2の接合接点と接触している接合界面と、を備え、
前記第1の半導体構造及び前記第2の半導体構造の少なくとも一方は、さらに、前記DRAMセルのアレイの周辺回路であって、前記プロセッサに含まれるトランジスタとは異なるトランジスタを含む周辺回路を含む、
半導体デバイス。 - 前記第1の半導体構造は、
基板と、
前記基板上の前記プロセッサと、
前記基板上かつ前記プロセッサの外側の前記SRAMセルのアレイと、
前記プロセッサおよび前記SRAMセルのアレイの上方の前記第1の接合層と、を有する、
請求項1に記載の半導体デバイス。 - 前記第2の半導体構造は、
前記第1の接合層の上方の前記第2の接合層と、
前記第2の接合層の上方の前記DRAMセルのアレイと、
前記DRAMセルのアレイの上方にあり、前記DRAMセルのアレイと接触している半導体層と、を有する、
請求項2に記載の半導体デバイス。 - 前記半導体層の上方にパッドアウト相互接続層をさらに備える、
請求項3に記載の半導体デバイス。 - 前記第2の半導体構造は、
基板と、
前記基板上の前記DRAMセルのアレイと、
前記DRAMセルのアレイの上方の前記第2の接合層と、を有する、
請求項1に記載の半導体デバイス。 - 前記第1の半導体構造は、
前記第2の接合層の上方の前記第1の接合層と、
前記第1の接合層の上方の前記プロセッサと、
前記第1の接合層の上方かつ前記プロセッサの外側にある前記SRAMセルのアレイと、
前記プロセッサおよび前記SRAMセルのアレイの上方にあり、前記プロセッサおよび前記SRAMセルのアレイと接触する半導体層と、を有する、
請求項5に記載の半導体デバイス。 - 前記半導体層の上方にパッドアウト相互接続層をさらに備える、
請求項6に記載の半導体デバイス。 - 前記第1の半導体構造は、垂直方向における前記第1の接合層と前記プロセッサとの間に第1の相互接続層を有し、
前記第2の半導体構造は、垂直方向における前記第2の接合層と前記DRAMセルのアレイとの間に第2の相互接続層を有し、
前記プロセッサおよび前記SRAMセルのアレイは、前記第1および第2の相互接続層ならびに前記第1および第2の接合接点を介して前記DRAMセルのアレイに電気的に接続される、
請求項1に記載の半導体デバイス。 - 前記SRAMセルのアレイは、前記第1の半導体構造内の複数の別個の領域に分散される、
請求項1に記載の半導体デバイス。 - 半導体デバイスを形成するための方法であって、
第1のウェハ上に複数の第1の半導体構造を形成することであって、前記第1の半導体構造の少なくとも1つは、トランジスタを含むプロセッサと、スタティック・ランダムアクセス・メモリ(SRAM)セルのアレイと、複数の第1の接合接点を含む第1の接合層とを有する、複数の第1の半導体構造を形成することと、
第2のウェハ上に複数の第2の半導体構造を形成することであって、前記第2の半導体構造の少なくとも1つは、ダイナミック・ランダムアクセス・メモリ(DRAM)セルのアレイと、複数の第2の接合接点を含む第2の接合層とを有する、複数の第2の半導体構造を形成することと、
前記第1の半導体構造の前記少なくとも1つが前記第2の半導体構造の前記少なくとも1つに接合されるように、face-to-face方式で前記第1のウェハと前記第2のウェハとを接合することであって、前記第1の半導体構造の前記第1の接合接点が前記第2の半導体構造の前記第2の接合接点に接合界面で接触するように、前記第1のウェハと前記第2のウェハとを接合することと、
複数のダイに前記接合された第1および第2のウェハをダイシングすることであって、前記ダイの少なくとも1つが、前記接合された第1および第2の半導体構造を含むように、前記接合された第1および第2のウェハをダイシングすることと、を含み、
前記第1の半導体構造及び前記第2の半導体構造の少なくとも一方は、さらに、前記DRAMセルのアレイの周辺回路であって、前記プロセッサに含まれるトランジスタとは異なるトランジスタを含む周辺回路を含む、
方法。 - 前記複数の第1の半導体構造を形成することは、
前記プロセッサおよび前記SRAMセルのアレイを前記第1のウェハ上に形成することと、
前記プロセッサおよび前記SRAMセルのアレイの上方に第1の相互接続層を形成することと、
前記第1の相互接続層の上方に前記第1の接合層を形成することと、を含む、
請求項10に記載の方法。 - 前記複数の第2の半導体構造を形成することは、
前記第2のウェハ上に前記DRAMセルのアレイを形成することと、
前記DRAMセルのアレイの上方に第2の相互接続層を形成することと、
前記第2の相互接続層の上方に前記第2の接合層を形成することと、を含む、
請求項10に記載の方法。 - 前記第1のウェハと前記第2のウェハとを接合することの後に、前記第2の半導体構造は、前記第1の半導体構造の上方にあり、
前記方法は、前記第1のウェハと前記第2のウェハとを接合することの後、かつ、前記接合された第1および第2のウェハをダイシングすることの前に、
半導体層を形成するために前記第2のウェハを薄くすることと、
前記半導体層の上方にパッドアウト相互接続層を形成することと、をさらに含む、
請求項10に記載の方法。 - 前記第1のウェハと前記第2のウェハとを接合することの後に、前記第1の半導体構造は、前記第2の半導体構造の上方にあり、
前記方法は、前記接合することの後に、前記第1のウェハと前記第2のウェハとを接合することの後、かつ、前記接合された第1および第2のウェハをダイシングすることの前に、
半導体層を形成するために前記第1のウェハを薄くすることと、
前記半導体層の上方にパッドアウト相互接続層を形成することと、をさらに含む、
請求項10に記載の方法。 - 半導体デバイスを形成するための方法であって、
第1のウェハ上に複数の第1の半導体構造を形成することであって、前記第1の半導体構造の少なくとも1つは、トランジスタを含むプロセッサと、スタティック・ランダムアクセス・メモリ(SRAM)セルのアレイと、複数の第1の接合接点を含む第1の接合層とを有する、複数の第1の半導体構造を形成することと、
複数の第1のダイに前記第1のウェハをダイシングすることであって、前記第1のダイの少なくとも1つが前記第1の半導体構造の前記少なくとも1つを含むように、前記第1のウェハをダイシングすることと、
第2のウェハ上に複数の第2の半導体構造を形成することであって、前記第2の半導体構造の少なくとも1つは、ダイナミック・ランダムアクセス・メモリ(DRAM)セルのアレイと、複数の第2の接合接点を含む第2の接合層とを有する、複数の第2の半導体構造を形成することと、
複数の第2のダイに前記第2のウェハをダイシングすることであって、前記第2のダイの少なくとも1つが前記第2の半導体構造の前記少なくとも1つを含むように、前記第2のウェハをダイシングすることと、
前記第1の半導体構造が前記第2の半導体構造に接合されるように、face-to-face方式で前記第1のダイと前記第2のダイとを接合することであって、前記第1の半導体構造の前記第1の接合接点が前記第2の半導体構造の前記第2の接合接点に接合界面で接触するように、前記第1のダイと前記第2のダイとを接合することと、を含み、
前記第1の半導体構造及び前記第2の半導体構造の少なくとも一方は、さらに、前記DRAMセルのアレイの周辺回路であって、前記プロセッサに含まれるトランジスタとは異なるトランジスタを含む周辺回路を含む、
方法。 - 前記複数の第1の半導体構造を形成することは、
前記第1のウェハ上に前記プロセッサおよび前記SRAMセルのアレイを形成することと、
前記プロセッサおよび前記SRAMセルのアレイの上方に第1の相互接続層を形成することと、
前記第1の相互接続層の上方に前記第1の接合層を形成することと、を含む、
請求項15に記載の方法。 - 前記複数の第2の半導体構造を形成することは、
前記第2のウェハ上に前記DRAMセルのアレイを形成することと、
前記DRAMセルのアレイの上方に第2の相互接続層を形成することと、
前記第2の相互接続層の上方に前記第2の接合層を形成することと、を含む、
請求項15に記載の方法。 - 前記第1のダイと前記第2のダイとを接合することの後に、前記第2の半導体構造は、前記第1の半導体構造の上方にあり、
前記方法は、
前記第1のダイと前記第2のダイとを接合することの後に、半導体層を形成するために前記第2のウェハを薄くすることと、
前記半導体層の上方にパッドアウト相互接続層を形成することと、をさらに含む、
請求項15に記載の方法。 - 前記第1のダイと前記第2のダイとを接合することの後に、前記第1の半導体構造は、前記第2の半導体構造の上方にあり、
前記方法は、
前記第1のダイと前記第2のダイとを接合することの後に、半導体層を形成するために前記第1のウェハを薄くすることと、
前記半導体層の上方にパッドアウト相互接続層を形成することと、をさらに含む、
請求項15に記載の方法。
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