JP7331119B2 - 複数の機能性チップを伴う三次元nandメモリデバイスの集積 - Google Patents
複数の機能性チップを伴う三次元nandメモリデバイスの集積 Download PDFInfo
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- JP7331119B2 JP7331119B2 JP2021549842A JP2021549842A JP7331119B2 JP 7331119 B2 JP7331119 B2 JP 7331119B2 JP 2021549842 A JP2021549842 A JP 2021549842A JP 2021549842 A JP2021549842 A JP 2021549842A JP 7331119 B2 JP7331119 B2 JP 7331119B2
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Description
一部の実施形態では、三次元半導体デバイスを形成するための方法は、第1のメモリチップの第1の相互接続層を第2のメモリチップの第2の相互接続層と接合するステップの後に第1の基板または第2の基板を薄化するステップであって、薄化は、研削、湿式エッチング、乾式エッチング、または化学機械研磨を含む、ステップをさらに含む。
101 マイクロプロセッサチップ、CPUチップ
103 メモリチップ、DRAMチップ
105 CPU相互接続VIA
107、107b、107f DRAM相互接続VIA
202 CPU基板
204 CPUデバイス
206 ウェル
208 ゲートスタック
210 ゲートスペーサ
212 ソース/ドレイン
214 CPU相互接続層
216 垂直接触構造
218 導電線
220 絶縁層
222 導電レベル、金属レベル
222-1 底金属レベル
222-2 上方金属レベル
223 上面
300 CPUチップ
324 CPU接合層
400 DRAMチップ
402 DRAM基板
402b 底面
404 DRAMデバイス
408 ゲートスタック
410 ゲートスペーサ
412 ソース/ドレイン
414 DRAM相互接続層
416 接触構造
418 導電線
420 絶縁層
420b 底面
423 上面
424 DRAM接合層
430 DRAMコンデンサ
432 コンデンサ誘電層
434 コンデンサ電極
500 3DのICデバイス
526 接合境界面
536 接合境界面
600 製作プロセス
700 3DのICデバイス
740 NANDチップ
742 NAND相互接続VIA
800 DRAMチップ
844 DRAM基板接触部
900 NANDチップ
900t 上面
902 NAND基板
914 NAND相互接続層
916 接触構造
918 導電線
920 絶縁層
924 接合層
944 NAND基板接触部
946 NANDメモリストリング
948 導体層
950 誘電層
952 交互の導体/誘電体の積み重ね
954 半導体チャネル
956 メモリ膜
958 下方選択ゲート、ソース選択ゲート
960 上選択ゲート、ドレイン選択ゲート
962 エピタキシャル層、エピタキシャルプラグ
964 半導体層
966 ワード線接触部
968 ビット線接触部
1000 3DのICデバイス
1070 第1の接合境界面
1100 3DのICデバイス
1100t 表面
1172 垂直相互接続構造、Si貫通電極(TSV)
1200 3DのICデバイス
1224 接合層
1300 3DのICデバイス
1376 第2の接合境界面
1400 3DのICデバイス
1478 絶縁膜
1480 入力/出力(I/O)パッド
1482 TSV
1500 製作プロセス
L ゲート長さ
Claims (13)
- 三次元半導体デバイスを形成するための方法であって、
第1のメモリチップを形成するステップであって、
少なくとも1つの第1のメモリセルを第1の基板の上に形成すること、および、
少なくとも1つの第1の相互接続構造を備える第1の相互接続層を前記少なくとも1つの第1のメモリセルの上に形成すること
を含むステップと、
第2のメモリチップを形成するステップであって、
少なくとも1つの第2のメモリセルを第2の基板の上に形成すること、および、
少なくとも1つの第2の相互接続構造を備える第2の相互接続層を前記少なくとも1つの第2のメモリセルの上に形成すること
を含むステップと、
前記第1のメモリチップの前記少なくとも1つの第1のメモリセルが、前記少なくとも1つの第1の相互接続構造または前記少なくとも1つの第2の相互接続構造を通じて前記第2のメモリチップの前記少なくとも1つの第2のメモリセルと電気的に接続されるように、前記第1のメモリチップの前記第1の相互接続層を前記第2のメモリチップの前記第2の相互接続層と接合するステップであって、前記第1のメモリチップの前記第1の相互接続層を前記第2のメモリチップの前記第2の相互接続層と接合する前記ステップは、接合境界面において、誘電体から誘電体への接合と、金属から金属への接合とを含む、ステップと、
マイクロプロセッサチップを形成するステップであって、
少なくとも1つのマイクロプロセッサデバイスを第3の基板の上に形成すること、および、
第3の相互接続層を前記少なくとも1つのマイクロプロセッサデバイスの上に形成すること
を含むステップと、
前記マイクロプロセッサチップの前記少なくとも1つのマイクロプロセッサデバイスが、前記第1のメモリチップの前記少なくとも1つの第1のメモリセルと電気的に接続されるように、前記マイクロプロセッサチップの前記第3の相互接続層を前記第1のメモリチップの前記第1の基板と接合するステップと
を含む方法。 - 前記マイクロプロセッサチップの前記第3の相互接続層を前記第1のメモリチップの前記第1の基板と接合する前記ステップは、接合境界面において、誘電体から誘電体への接合と、金属から金属への接合とを含む、請求項1に記載の方法。
- 前記第1のメモリチップの前記第1の基板を通じて延びる少なくとも1つの垂直相互接続構造を形成するステップであって、前記少なくとも1つの垂直相互接続構造は前記第1の相互接続層の少なくとも1つの第1の相互接続構造に電気的接続を提供する、ステップをさらに含む、請求項1に記載の方法。
- 前記第2のメモリチップの前記第2の基板を通じて延びる少なくとも1つの垂直相互接続構造を形成するステップであって、前記少なくとも1つの垂直相互接続構造は前記第2の相互接続層の少なくとも1つの第2の相互接続構造に電気的接続を提供する、ステップをさらに含む、請求項1に記載の方法。
- 前記マイクロプロセッサチップの前記第3の基板を通じて延びる少なくとも1つの垂直相互接続構造を形成するステップであって、前記少なくとも1つの垂直相互接続構造は前記第3の相互接続層の少なくとも1つの第3の相互接続構造に電気的接続を提供する、ステップをさらに含む、請求項1に記載の方法。
- 前記マイクロプロセッサチップを形成する前記ステップは、コンピュータまたは携帯機器のためのデジタル信号処理装置、マイクロコントローラ、または中央演算機を形成することを含む、請求項1に記載の方法。
- 前記第1のメモリチップを形成する前記ステップはスタティックランダムアクセスメモリまたはダイナミックランダムアクセスメモリを形成することを含む、請求項1に記載の方法。
- 前記第2のメモリチップを形成する前記ステップはフラッシュメモリを形成することを含む、請求項1に記載の方法。
- 少なくとも1つのマイクロプロセッサデバイス、および、
前記少なくとも1つのマイクロプロセッサデバイスに配置される、少なくとも1つの第1の相互接続構造を備える第1の相互接続層
を備えるマイクロプロセッサチップと、
少なくとも1つの第1のメモリセル、および、
前記少なくとも1つの第1のメモリセルに配置される、少なくとも1つの第2の相互接続構造を備える第2の相互接続層
を備える第1のメモリチップと、
少なくとも1つの第2のメモリセル、および、
前記少なくとも1つの第2のメモリセルに配置される、少なくとも1つの第3の相互接続構造を備える第3の相互接続層
を備える第2のメモリチップと、
前記第2のメモリチップの前記第3の相互接続層と前記第1のメモリチップの前記第2の相互接続層との間の接合境界面であって、誘電体から誘電体への接合と、金属から金属への接合とを含む接合境界面と
を備え、
前記マイクロプロセッサチップの前記第1の相互接続層は前記第1のメモリチップと接合され、前記マイクロプロセッサチップの前記少なくとも1つのマイクロプロセッサデバイスは、前記少なくとも1つの第1の相互接続構造または前記少なくとも1つの第2の相互接続構造を通じて前記第1のメモリチップの前記少なくとも1つの第1のメモリセルと電気的に接続され、
前記第2のメモリチップの前記第3の相互接続層は前記第1のメモリチップの前記第2の相互接続層と接合され、前記マイクロプロセッサチップの前記少なくとも1つのマイクロプロセッサデバイスは、前記少なくとも1つの第1の相互接続構造、前記少なくとも1つの第2の相互接続構造、または、前記少なくとも1つの第3の相互接続構造を通じて前記第2のメモリチップの前記少なくとも1つの第2のメモリセルと電気的に接続され、
前記第1のメモリチップの前記少なくとも1つの第1のメモリセルは、前記少なくとも1つの第3の相互接続構造または前記少なくとも1つの第2の相互接続構造を通じて前記第2のメモリチップの前記少なくとも1つの第2のメモリセルと電気的に接続される、三次元半導体デバイス。 - 前記マイクロプロセッサチップの前記第1の相互接続層と前記第1のメモリチップとの間の接合境界面であって、誘電体から誘電体への接合と、金属から金属への接合とを含む接合境界面をさらに備える、請求項9に記載の三次元半導体デバイス。
- 前記マイクロプロセッサチップは、コンピュータまたは携帯機器のためのデジタル信号処理装置、マイクロコントローラ、または中央演算機を備える、請求項9に記載の三次元半導体デバイス。
- 前記第1のメモリチップはスタティックランダムアクセスメモリまたはダイナミックランダムアクセスメモリを備える、請求項9に記載の三次元半導体デバイス。
- 前記第2のメモリチップはフラッシュメモリを備える、請求項9に記載の三次元半導体デバイス。
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