JP7326192B2 - 配線基板及び半導体装置 - Google Patents
配線基板及び半導体装置 Download PDFInfo
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Description
高速配線20は、例えばPCIe(Peripheral Component Interconnect Express)などの高速配線であり、周波数が例えば1GHz以上の信号を流す配線であって、インピーダンスコントロールが必要とされる。信号配線では高速配線よりも遅い周波数の信号が流れる。高速配線ランド20aは、第1層高速配線20の線幅に比べて大きな径を有し、大きな面積を占める導体部となっている。また第1層高速配線20及び第2層高速配線20cは2本で一組のペア配線であり、その配線パターンは互いに似通っている。高速配線はペアで使用することが好ましい。例えば高速配線20は信号を高速でやりとりする必要がある第1の半導体チップ3にのみ接続される。例えば信号配線20は信号配線ランド22aから出て第1の半導体チップ3に接続されるものと、信号配線ランド22aから出て第3の半導体チップ6に接続されるものと、第1の半導体チップ3と第3の半導体チップ6とを接続するものとがある。
(a)上記実施形態ではグランド配線26をシールドとして利用したが、電源配線25をシールドとして用いてもよい。または、電源配線25とグランド配線26との両方をシールドに用いても良い。
(b)上記実施形態では電源配線25の上にグランド配線26があるが、電源配線25が上側にあり、グランド配線26が下側にあってもよい。
(c)上記実施形態ではグランド配線26または電源配線25がシールドするのは高速配線ランド20aであるが、信号配線ランド22aをシールドしてもよい。
(d)上記実施形態では図2、図3に示すように電源配線25の上にグランド配線26があり、疑似的に二層になっているが、電源配線25とグランド配線26とが同一層に設けられていてもよい。
Claims (7)
- 高速配線が配置された第1配線層と、
前記高速配線よりも遅い信号を伝送する信号配線が配置された第2配線層と、
前記第1配線層と前記第2配線層との間に配置され、電源配線又は/及びグランド配線を含む第3配線層と、を有する配線基板であって、
前記第1配線層のランドと前記信号配線が重ならない部分の前記電源配線又は/及びグランド配線を除去し、
前記第1配線層のランドと前記信号配線が重なる部分の前記電源配線又は/及びグランド配線を、前記信号配線と重なるように配置した、配線基板。 - 前記高速配線が、1GHz以上の周波数の信号を流す配線である
請求項1記載の配線基板。 - 前記第1配線層のランドと前記信号配線が重なる部分の前記電源配線又は/及びグランド配線の線幅は、前記信号配線の線幅を10とした場合、5から15の幅である
請求項1又は2記載の配線基板。 - 前記第1配線層と前記第2配線層との間のノイズシールドのために設けられた前記第3配線層の配線は、グランド配線である
請求項1乃至3の何れか1項記載の配線基板。 - 絶縁層が、樹脂、セラミックス、ガラス、ポリイミド、シリコン酸化物、シリコン窒化物の何れか一つを少なくとも含む絶縁材料で形成され、
導体層が、銅、アルミニウム、タングステン、金、銀の何れか一つを少なくとも含む合金で形成された
請求項1乃至4の何れか1項記載の配線基板。 - 請求項1乃至5の何れか1項記載の配線基板に設けられた第1半導体チップと、
前記第1半導体チップの上に設けられた第1樹脂層と、
前記第1樹脂層の上に設けられた第2半導体チップと、をさらに備え、
前記高速配線は前記第1半導体チップと接続する半導体装置。 - 前記第1半導体チップはコントローラチップであり、
前記第2半導体チップは半導体メモリチップである、
請求項6記載の半導体装置。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000156549A (ja) | 1998-11-20 | 2000-06-06 | Sega Enterp Ltd | プリント配線基板及びそれを搭載したゲーム装置 |
JP2000311964A (ja) | 1999-04-27 | 2000-11-07 | Nec Corp | 半導体装置 |
JP2014022652A (ja) | 2012-07-20 | 2014-02-03 | Elpida Memory Inc | 半導体装置及びそのテスト装置、並びに、半導体装置のテスト方法 |
JP2019129181A (ja) | 2018-01-22 | 2019-08-01 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6510545B1 (en) * | 2000-01-19 | 2003-01-21 | Sun Microsystems, Inc. | Automated shielding algorithm for dynamic circuits |
JP2001203470A (ja) * | 2000-01-21 | 2001-07-27 | Toshiba Corp | 配線基板、半導体パッケージ、および半導体装置 |
JP2001250825A (ja) | 2000-03-06 | 2001-09-14 | Nec Microsystems Ltd | 多層配線構造 |
US7002253B2 (en) | 2003-04-30 | 2006-02-21 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and design method thereof |
US7227247B2 (en) * | 2005-02-16 | 2007-06-05 | Intel Corporation | IC package with signal land pads |
JP4919475B2 (ja) | 2006-07-13 | 2012-04-18 | ルネサスエレクトロニクス株式会社 | 半導体集積回路の製造方法 |
US7894199B1 (en) * | 2008-02-20 | 2011-02-22 | Altera Corporation | Hybrid package |
KR101817156B1 (ko) * | 2010-12-28 | 2018-01-10 | 삼성전자 주식회사 | 관통 전극을 갖는 적층 구조의 반도체 장치, 반도체 메모리 장치, 반도체 메모리 시스템 및 그 동작방법 |
US20140209367A1 (en) * | 2011-09-09 | 2014-07-31 | Nec Corporation | Wiring board |
JP6122606B2 (ja) * | 2012-10-16 | 2017-04-26 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20140252632A1 (en) * | 2013-03-06 | 2014-09-11 | Hans-Joachim Barth | Semiconductor devices |
US9099533B2 (en) * | 2013-07-02 | 2015-08-04 | International Business Machines Corporation | Semiconductor device with distinct multiple-patterned conductive tracks on a same level |
WO2015162768A1 (ja) * | 2014-04-24 | 2015-10-29 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US10276519B2 (en) * | 2015-06-02 | 2019-04-30 | Sarcina Technology LLC | Package substrate differential impedance optimization for 25 to 60 Gbps and beyond |
JP6819599B2 (ja) * | 2015-09-25 | 2021-01-27 | 大日本印刷株式会社 | 実装部品、配線基板、電子装置、およびその製造方法 |
JP2017146767A (ja) * | 2016-02-17 | 2017-08-24 | 株式会社ジャパンディスプレイ | 表示装置 |
US9985007B2 (en) * | 2016-07-22 | 2018-05-29 | Invensas Corporation | Package on-package devices with multiple levels and methods therefor |
JP7001530B2 (ja) * | 2018-04-16 | 2022-01-19 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6535788B2 (ja) * | 2018-06-06 | 2019-06-26 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2020
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- 2020-08-03 CN CN202010768154.0A patent/CN113410204B/zh active Active
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000156549A (ja) | 1998-11-20 | 2000-06-06 | Sega Enterp Ltd | プリント配線基板及びそれを搭載したゲーム装置 |
JP2000311964A (ja) | 1999-04-27 | 2000-11-07 | Nec Corp | 半導体装置 |
JP2014022652A (ja) | 2012-07-20 | 2014-02-03 | Elpida Memory Inc | 半導体装置及びそのテスト装置、並びに、半導体装置のテスト方法 |
JP2019129181A (ja) | 2018-01-22 | 2019-08-01 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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