JP7071311B2 - 酸化物トランジスタ閾値電圧に対して感度が低減された低リフレッシュレート表示画素を有する電子デバイス - Google Patents
酸化物トランジスタ閾値電圧に対して感度が低減された低リフレッシュレート表示画素を有する電子デバイス Download PDFInfo
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Description
本出願は、一般的には、電子デバイスに関し、より具体的には、ディスプレイを有する電子デバイスに関する。
Claims (13)
- 表示画素であって、
発光ダイオードと、
前記発光ダイオードと直列に結合されている駆動トランジスタであって、ドレイン端子とゲート端子とソース端子とを含む、駆動トランジスタと、
前記駆動トランジスタの前記ドレイン端子と前記ゲート端子との間に結合されている半導体酸化物トランジスタであって、前記駆動トランジスタの前記ゲート端子におけるリークを低減するように構成されており、かつ、閾値電圧を有する、半導体酸化物トランジスタと、
前記半導体酸化物トランジスタと前記駆動トランジスタの前記ゲート端子との間に介在しているシリコントランジスタであって、前記半導体酸化物トランジスタの前記閾値電圧の変化に対して、前記発光ダイオードを通じて流れる発光電流の感度を低減するように構成されている、シリコントランジスタと、を備える、表示画素。 - 前記半導体酸化物トランジスタ及び前記シリコントランジスタは、両方ともnチャネル薄膜トランジスタである、請求項1に記載の表示画素。
- 前記半導体酸化物トランジスタはnチャネル薄膜トランジスタであり、前記シリコントランジスタはpチャネル薄膜トランジスタである、請求項1に記載の表示画素。
- 前記駆動トランジスタの前記ゲート端子に結合されている蓄積コンデンサであって、前記表示画素に対するデータ信号を記憶するように構成されている、蓄積コンデンサと、
前記半導体酸化物トランジスタと前記シリコントランジスタとの間の中間ノードに結合されている整合コンデンサであって、前記半導体酸化物トランジスタがオフにされるときに、前記半導体酸化物トランジスタを通じて流れる再バランス電流を低減するように構成されている、整合コンデンサと、を更に備える、請求項1に記載の表示画素。 - 前記整合コンデンサの容量値は前記蓄積コンデンサの容量値よりも小さい、請求項4に記載の表示画素。
- 前記駆動トランジスタの前記ゲート端子に結合されている蓄積コンデンサであって、前記表示画素に対するデータ信号を記憶するように構成されている、蓄積コンデンサと、
前記駆動トランジスタの前記ドレイン端子に結合されている容量バランスコンデンサであって、前記半導体酸化物トランジスタがオフにされるときに、前記半導体酸化物トランジスタを通じて流れる再バランス電流を低減するように構成されている、容量バランスコンデンサと、を更に備える、請求項1に記載の表示画素。 - 前記半導体酸化物トランジスタは、走査制御信号を受信するように構成されているゲート端子を有し、前記シリコントランジスタは、前記走査制御信号とは異なる発光制御信号を受信するように構成されているゲート端子を有する、請求項1に記載の表示画素。
- 前記半導体酸化物トランジスタ及び前記シリコントランジスタは、同じ走査制御信号を受信するように構成されているゲート端子を有する、請求項1に記載の表示画素。
- 前記半導体酸化物トランジスタは第1の閾値電圧を有し、前記シリコントランジスタは、前記第1の閾値電圧よりも大きい第2の閾値電圧を有する、請求項8に記載の表示画素。
- 前記駆動トランジスタ及び前記発光ダイオードと直列に結合されている第1の発光トランジスタと、
前記駆動トランジスタ及び前記発光ダイオードと直列に結合されている第2の発光トランジスタと、
前記発光ダイオードに直接結合されている初期化トランジスタと、
前記駆動トランジスタの前記ソース端子に直接結合されているデータローディングトランジスタと、を更に備える、請求項1に記載の表示画素。 - 表示画素を動作させる方法であって、
発光フェーズ中に、前記表示画素内の駆動トランジスタを使用して、前記表示画素内の発光ダイオードに発光電流を伝達することであって、前記駆動トランジスタがドレイン端子とゲート端子とを含む、ことと、
前記発光フェーズ中に、前記駆動トランジスタの前記ドレイン端子と前記ゲート端子との間に結合されている半導体酸化物トランジスタを使用して、前記駆動トランジスタの前記ゲート端子におけるリークを低減することであって、前記半導体酸化物トランジスタが閾値電圧を有する、ことと、
前記半導体酸化物トランジスタと前記駆動トランジスタの前記ゲート端子との間に介在するシリコントランジスタを使用して、前記半導体酸化物トランジスタの前記閾値電圧の変化に対して前記発光電流の感度を低減することと、を含む、方法。 - 前記半導体酸化物トランジスタのゲート端子に走査制御信号を提供することと、
前記シリコントランジスタのゲート端子に、前記走査制御信号とは異なる発光制御信号を提供することと、
前記走査制御信号の立ち下がりエッジ前に前記発光制御信号を無効にし、前記走査制御信号の前記立ち下がりエッジ後に前記発光制御信号を有効にすることと、を更に含む、請求項11に記載の方法。 - 前記半導体酸化物トランジスタのゲート端子に走査制御信号を提供することと、
前記シリコントランジスタのゲート端子に前記走査制御信号を提供することと、
前記走査制御信号の立ち下がりエッジにおいて、前記半導体酸化物トランジスタをオフにする前に、前記シリコントランジスタをオフにすることと、を更に含む、請求項11に記載の方法。
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