JP6920189B2 - 配線基板 - Google Patents
配線基板 Download PDFInfo
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- JP6920189B2 JP6920189B2 JP2017250751A JP2017250751A JP6920189B2 JP 6920189 B2 JP6920189 B2 JP 6920189B2 JP 2017250751 A JP2017250751 A JP 2017250751A JP 2017250751 A JP2017250751 A JP 2017250751A JP 6920189 B2 JP6920189 B2 JP 6920189B2
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- Prior art keywords
- wiring
- pattern
- insulating layer
- dummy pattern
- layer
- Prior art date
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- 229920005989 resin Polymers 0.000 claims description 68
- 239000011347 resin Substances 0.000 claims description 68
- 230000004048 modification Effects 0.000 description 21
- 238000012986 modification Methods 0.000 description 21
- 238000009713 electroplating Methods 0.000 description 16
- 230000000694 effects Effects 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 11
- 239000010949 copper Substances 0.000 description 9
- 230000000052 comparative effect Effects 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000010030 laminating Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 239000011800 void material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910001431 copper ion Inorganic materials 0.000 description 2
- 230000006837 decompression Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 229920006231 aramid fiber Polymers 0.000 description 1
- XLJMAIOERFSOGZ-UHFFFAOYSA-M cyanate Chemical compound [O-]C#N XLJMAIOERFSOGZ-UHFFFAOYSA-M 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000002759 woven fabric Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/066—Transfer laminating of insulating material, e.g. resist as a whole layer, not as a pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1178—Means for venting or for letting gases escape
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Structure Of Printed Boards (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
[第1の実施の形態に係る配線基板の構造]
まず、第1の実施の形態に係る配線基板の構造について説明する。図1は、第1の実施の形態に係る配線基板を例示する図であり、図1(a)は部分平面図、図1(b)は図1(a)のA−A線に沿う断面図である。なお、図1(a)では、便宜上、配線パターン21及び22並びにダミーパターン23を梨地模様で示している。又、図1(a)では、図1(b)に示す絶縁層30の図示を省略している。
次に、第1の実施の形態に係る配線基板の製造方法について説明する。図2は、第1の実施の形態に係る配線基板の製造工程を例示する図である。なお、本実施の形態では、単品の配線基板を作製する工程の例を示すが、配線基板となる複数の部分を作製後、各部分を個片化して複数の配線基板とする工程としてもよい。
第1の実施の形態の変形例1では、第1の実施の形態とは異なるダミーパターンを有する配線基板の例を示す。なお、第1の実施の形態の変形例1において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第1の実施の形態の変形例2では、第1の実施の形態とは異なるダミーパターンを有する配線基板の他の例を示す。なお、第1の実施の形態の変形例2において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第1の実施の形態の変形例3では、第1の実施の形態とは異なるダミーパターンを有する配線基板の更に他の例を示す。なお、第1の実施の形態の変形例3において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第1の実施の形態の変形例4では、第1の実施の形態とは異なるダミーパターンを有する配線基板の更に他の例を示す。なお、第1の実施の形態の変形例4において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
10、30 絶縁層
10a 一方の面
20、20A、20B、20C、20D 配線層
21 配線パターン
22 配線パターン
23、23A、23B、23C、23D ダミーパターン
201 シード層
202 電解めっき層
300 樹脂フィルム
900 加圧熱プレート
Claims (4)
- 第1絶縁層と、
前記第1絶縁層の一方の面に形成された複数の配線パターンと、
前記第1絶縁層の一方の面において、隣接する前記配線パターン間に形成されたダミーパターンと、
前記第1絶縁層の一方の面に、隣接する前記配線パターン及び前記ダミーパターンを被覆するように形成された、樹脂製の第2絶縁層と、を有し、
前記ダミーパターンは、隣接する前記配線パターンの中央部に配置されたドットパターンであり、
前記ダミーパターンを構成する各々のドットの高さが、隣接する前記配線パターンの高さよりも低く、
前記ドットは、前記第1絶縁層の一方の面に向けて拡幅する傾斜側面を有している配線基板。 - 前記ドットは、複数配置されており、千鳥状に配置されている請求項1に記載の配線基板。
- 前記ドットは、複数配置されており、複数列に配置されている請求項1に記載の配線基板。
- 前記ドットは、平面視楕円形状からなり、その長辺が配線パターンの形成方向に沿って配置されている請求項1に記載の配線基板。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017250751A JP6920189B2 (ja) | 2017-12-27 | 2017-12-27 | 配線基板 |
US16/211,716 US10854475B2 (en) | 2017-12-27 | 2018-12-06 | Wiring substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017250751A JP6920189B2 (ja) | 2017-12-27 | 2017-12-27 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2019117854A JP2019117854A (ja) | 2019-07-18 |
JP6920189B2 true JP6920189B2 (ja) | 2021-08-18 |
Family
ID=66951424
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017250751A Active JP6920189B2 (ja) | 2017-12-27 | 2017-12-27 | 配線基板 |
Country Status (2)
Country | Link |
---|---|
US (1) | US10854475B2 (ja) |
JP (1) | JP6920189B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI701979B (zh) * | 2019-05-17 | 2020-08-11 | 欣興電子股份有限公司 | 線路板及其製作方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3640097B2 (ja) * | 1994-12-14 | 2005-04-20 | セイコーエプソン株式会社 | 光センシング装置 |
JP4541260B2 (ja) | 2005-08-31 | 2010-09-08 | 東京特種紙業株式会社 | 回路板の製造方法 |
JP5259211B2 (ja) * | 2008-02-14 | 2013-08-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2017
- 2017-12-27 JP JP2017250751A patent/JP6920189B2/ja active Active
-
2018
- 2018-12-06 US US16/211,716 patent/US10854475B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20190198433A1 (en) | 2019-06-27 |
US10854475B2 (en) | 2020-12-01 |
JP2019117854A (ja) | 2019-07-18 |
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