JP6766758B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP6766758B2 JP6766758B2 JP2017117856A JP2017117856A JP6766758B2 JP 6766758 B2 JP6766758 B2 JP 6766758B2 JP 2017117856 A JP2017117856 A JP 2017117856A JP 2017117856 A JP2017117856 A JP 2017117856A JP 6766758 B2 JP6766758 B2 JP 6766758B2
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- groove portion
- substrate
- back surface
- surface side
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims description 43
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000000758 substrate Substances 0.000 claims description 111
- 230000002093 peripheral effect Effects 0.000 claims description 25
- 230000001681 protective effect Effects 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 20
- 238000005452 bending Methods 0.000 claims description 15
- 239000010410 layer Substances 0.000 description 18
- 238000005520 cutting process Methods 0.000 description 13
- 239000002390 adhesive tape Substances 0.000 description 8
- 239000012790 adhesive layer Substances 0.000 description 6
- 230000007423 decrease Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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Description
第1実施形態について説明する。図1に示すように、本実施形態の半導体装置は、半導体チップ10と、半導体チップ10が備える基板20に貼り付けられたDAF30と、実装基板40と、ボンディングワイヤ50とを備えている。
第2実施形態について説明する。本実施形態は、第1実施形態に対して基板20の形状を変更したものであり、その他については第1実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
第3実施形態について説明する。本実施形態は、第2実施形態に対して基板20の構成を変更したものであり、その他については第2実施形態と同様であるため、第2実施形態と異なる部分についてのみ説明する。
なお、本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
30 DAF
80 溝部
90 保護部材
110 溝部
Claims (12)
- 表面(20a)および裏面(20b)を有する基板(20)と、前記裏面に貼り付けられたフィルム(30)と、を備える半導体装置の製造方法であって、
前記裏面に前記フィルムを貼り付けることと、
前記フィルムと共に前記基板を前記裏面からハーフカットし、裏面側溝部(80)を形成することと、
前記裏面側溝部を形成することの後に、前記フィルムに保護部材(90)を貼り付けることと、
前記保護部材を貼り付けることの後に、前記表面から前記基板のダイシングカットを行い、前記裏面側溝部と連結された表面側溝部(110)を形成することと、
前記表面にボンディングワイヤ(50)を接続することと、を備え、
前記表面側溝部を形成することでは、前記表面側溝部が前記裏面に向かうにつれて幅が狭くなる段付き形状となるように、1つの溝部の底部に該溝部よりも開口幅が小さい別の溝部を形成することを少なくとも1回行い、
前記ボンディングワイヤを接続することでは、前記表面側溝部を前記段付き形状とすることによって前記基板の前記表面と側面(20c)との間の角部に形成された凹部(20e)を前記ボンディングワイヤが通るようにする半導体装置の製造方法。 - 前記裏面側溝部を形成することでは、前記基板のうち前記裏面側溝部と前記表面とで挟まれた部分の抗折強度が、前記表面側溝部を形成することにおいて前記基板の割れが生じる抗折強度よりも高くなるように、前記基板をハーフカットする請求項1に記載の半導体装置の製造方法。
- 前記表面側溝部を形成することでは、前記表面に第1表面側溝部(111)を形成した後、前記第1表面側溝部の底部に前記第1表面側溝部よりも開口幅が小さい第2表面側溝部(112)を形成し、前記第2表面側溝部を前記裏面側溝部と連結させる請求項1または2に記載の半導体装置の製造方法。
- 前記表面側溝部を形成することでは、前記裏面側溝部の幅より、前記表面側の前記別の溝部の幅を狭くする請求項1ないし3のいずれか1つに記載の半導体装置の製造方法。
- 前記表面側溝部を形成することでは、前記1つの溝部の底部に前記別の溝部を形成することを複数回行い、前記裏面側溝部の幅より、前記別の溝部のうち前記裏面側溝部に連結される溝部の幅を狭くする請求項1ないし3のいずれか1つに記載の半導体装置の製造方法。
- 前記表面側溝部を形成することでは、前記1つの溝部の幅を前記裏面側溝部の幅より狭くする請求項1ないし5のいずれか1つに記載の半導体装置の製造方法。
- 前記表面側溝部を形成することでは、前記基板のうち前記裏面側溝部と前記表面に形成された1つの溝部とで挟まれた部分の抗折強度が、該1つの溝部の底部に別の溝部を形成するときに前記基板の割れが生じる抗折強度よりも高くなるように、該1つの溝部を形成する請求項1ないし6のいずれか1つに記載の半導体装置の製造方法。
- 前記表面側溝部を形成することでは、ダイシングブレード(100、130)と前記保護部材とが離された状態でダイシングを行う請求項1ないし7のいずれか1つに記載の半導体装置の製造方法。
- 前記表面側溝部を形成することでは、ダイシングブレード(100、130)にて前記ダイシングカットを行い、
前記裏面側溝部を形成することでは、前記ダイシングブレードの丸くなった先端部の長さ(H31)よりも、前記裏面側溝部の深さ(H2)を大きくする請求項1ないし5のいずれか1つに記載の半導体装置の製造方法。 - 表面(20a)および裏面(20b)を有する基板(20)と、前記裏面に貼り付けられたフィルム(30)と、を備える半導体装置であって、
前記表面および前記裏面の外周部が内周部よりも凹むことにより、前記表面の内周部から前記表面の外周部、前記基板の側面(20c)、前記裏面の外周部を経て前記裏面の内周部に至る部分が段付き形状とされており、
前記フィルムは、前記裏面の内周部に貼り付けられており、
前記基板の前記表面と前記側面との間の角部に凹部(20e)が形成され、
前記表面に接続されたボンディングワイヤ(50)が該凹部を通るように配置されている半導体装置。 - 前記表面の外周端部が内周部よりも凹んだ形状とされ、該凹部が複数段の段付き形状とされている請求項10に記載の半導体装置。
- 前記基板の前記裏面と前記側面との間の角部に凹部(20d)が形成され、
前記基板の前記表面と前記側面との間の角部に形成された前記凹部の幅が、前記裏面と前記側面との間の角部に形成された前記凹部の幅よりも狭い請求項10に記載の半導体装置。
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