JP6650723B2 - リードフレーム及びその製造方法、半導体装置 - Google Patents
リードフレーム及びその製造方法、半導体装置 Download PDFInfo
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- JP6650723B2 JP6650723B2 JP2015205027A JP2015205027A JP6650723B2 JP 6650723 B2 JP6650723 B2 JP 6650723B2 JP 2015205027 A JP2015205027 A JP 2015205027A JP 2015205027 A JP2015205027 A JP 2015205027A JP 6650723 B2 JP6650723 B2 JP 6650723B2
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Description
[第1の実施の形態に係る半導体装置の構造]
まず、第1の実施の形態に係る半導体装置の構造について説明する。図1は、第1の実施の形態に係る半導体装置を例示する図であり、図1(a)は平面図、図1(b)は図1(a)のA−A線に沿う断面図、図1(c)は図1(b)のBの部分拡大断面図、図1(d)は図1(b)のBの部分拡大平面図である。但し、図1(a)では、便宜上、金属線30及び樹脂部40の図示は省略されている。又、図1(d)では、便宜上、半導体チップ20及び樹脂部40の図示は省略されている。
次に、第1の実施の形態に係る半導体装置の製造方法について説明する。図3〜図8は、第1の実施の形態に係る半導体装置の製造工程を例示する図である。
第2の実施の形態では、QFP(Quad Flat Package)の例を示す。なお、第2の実施の形態において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
まず、図11に示す試験用サンプルを作製した。具体的には、銅からなる平坦な金属板であるリードフレーム材100の上面に、凹部の平面形状が直径0.02mm以上0.060mm以下の円である凹凸部を形成した。そして、凹凸部の表面にめっきを施さないで、凹凸部上に表1に示す作製条件で樹脂カップ140を形成した。なお、6種類のSレシオにおいて、各々6個の試験用サンプルを作製し、6回測定を行った。但し、Sレシオ=1は、凹凸部を形成しない試験用サンプル(比較例:従来品)である。又、Sレシオを求める際の表面積の測定は、3次元測定レーザ顕微鏡(オリンパス社製 LEXT OLS4100)を用いて行った。
銅からなるリードフレーム材100の上面に実施例1と同様の凹凸部を形成し、凹凸部の表面に銀めっきを施し、銀めっきを施した凹凸部上に樹脂カップ140を形成した以外は実施例1と同様にしてカップシェア試験を実施した。なお、銀めっき膜の厚さは約6μmとした。
銅からなるリードフレーム材100の上面に実施例1と同様の凹凸部を形成し、凹凸部の表面にNi/Pd/Auめっきを施し、Ni/Pd/Auめっきを施した凹凸部上に樹脂カップ140を形成した以外は実施例1と同様にしてカップシェア試験を実施した。
銅からなるリードフレームの上面に、凹部の平面形状が直径0.02mm以上0.060mm以下の円であって、Sレシオが1.7以上の凹凸部、すなわち高密度凹凸部を形成することにより、樹脂部と接する部分の表面積が増加する。そのため、アンカー効果が生じ、リードフレームと樹脂部との密着性を向上することができる。
10、10S、50S リードフレーム
13 高密度凹凸部
11、51 ダイパッド
11x、12x 段差部
12、52 リード
15 連結部
20 半導体チップ
30 金属線
40 樹脂部
52i インナーリード
52o アウターリード
151 外枠部
152、552 ダムバー
153、553 サポートバー
Claims (7)
- リードフレームと、
前記リードフレームに搭載された半導体チップと、
前記リードフレーム及び前記半導体チップを被覆する封止樹脂と、を有し、
前記リードフレームの前記封止樹脂による被覆領域には凹凸部が形成され、
前記被覆領域は、前記半導体チップが搭載されるチップ搭載部の上面と、前記チップ搭載部の下面の外周に設けられた段差部の下面と、前記段差部から延在する前記段差部と同一厚さのサポートバーの上面及び下面と、を含み、
前記凹凸部における凹部の平面形状は直径0.02mm以上0.060mm以下の円、又は、直径0.02mm以上0.060mm以下の外接円に接する多角形であり、
表面積がS0の平坦面に凹凸部を形成し、凹凸部の表面積がSであった場合のS0とSとの比率S/S0が1.7以上であり、
前記リードフレームと前記半導体チップとは金属線を介して接続され、
前記リードフレームの前記金属線との接続領域に、前記凹凸部が形成されている半導体装置。 - 前記リードフレームの前記封止樹脂からの露出部分は、平坦面である請求項1に記載の半導体装置。
- 前記凹凸部上にめっき膜が形成され、
前記めっき膜が形成された前記凹凸部の前記比率S/S0が1.7以上である請求項1又は2に記載の半導体装置。 - 封止樹脂による被覆領域を有するリードフレームであって、
前記被覆領域は、半導体チップが搭載されるチップ搭載部の上面と、前記チップ搭載部の下面の外周に設けられた段差部の下面と、前記段差部から延在する前記段差部と同一厚さのサポートバーの上面及び下面と、を含み、
前記被覆領域には凹凸部が形成され、
前記凹凸部における凹部の平面形状は直径0.02mm以上0.060mm以下の円、又は、直径0.02mm以上0.060mm以下の外接円に接する多角形であり、
表面積がS0の平坦面に凹凸部を形成し、凹凸部の表面積がSであった場合のS0とSとの比率S/S0が1.7以上であり、
前記リードフレームは、金属線の接続領域を備え、
前記接続領域に、前記凹凸部が形成されているリードフレーム。 - 前記凹凸部上にめっき膜が形成され、
前記めっき膜が形成された前記凹凸部の前記比率S/S0が1.7以上である請求項4に記載のリードフレーム。 - 金属製の板材をエッチングして、リードフレームを形成する工程と、
前記リードフレームの封止樹脂による被覆領域に、凹凸部を形成する工程と、を有し、
前記凹凸部における凹部の平面形状は直径0.02mm以上0.060mm以下の円、又は、直径0.02mm以上0.060mm以下の外接円に接する多角形であり、
表面積がS0の平坦面に凹凸部を形成し、凹凸部の表面積がSであった場合のS0とSとの比率S/S0が1.7以上であり、
前記被覆領域は、半導体チップが搭載されるチップ搭載部の上面と、前記チップ搭載部の下面の外周に設けられた段差部の下面と、前記段差部から延在する前記段差部と同一厚さのサポートバーの上面及び下面と、を含み、
前記リードフレームは、金属線の接続領域を備え、
前記凹凸部を形成する工程では、前記接続領域に前記凹凸部が形成されるリードフレームの製造方法。 - 前記リードフレームを形成する工程と、前記凹凸部を形成する工程と、は同一工程であり、
前記リードフレーム、及び前記凹凸部は、同一のエッチングマスクを用いてエッチングにより形成される請求項6に記載のリードフレームの製造方法。
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