JP6620889B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6620889B2 JP6620889B2 JP2018533350A JP2018533350A JP6620889B2 JP 6620889 B2 JP6620889 B2 JP 6620889B2 JP 2018533350 A JP2018533350 A JP 2018533350A JP 2018533350 A JP2018533350 A JP 2018533350A JP 6620889 B2 JP6620889 B2 JP 6620889B2
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- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
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Description
図1は、本発明の第1実施形態に係る半導体装置の構成を模式的に示す斜視図である。第1実施形態では、複数の半導体素子として金属酸化膜半導体電界効果トランジスタ(MOSFET)を有する半導体装置を例示的に説明する。半導体素子は、平面における2軸方向(X軸方向及びZ軸方向)それぞれに更に多数配列され得る。なお、図1では分かり易くするため、電極の一部及び配線は図示を省略している。
図17は、本発明の第2実施形態に係る半導体装置を説明する断面図である。なお、図17は、第2実施形態に係る半導体装置を、ゲート電極9を通るx−y平面で切断した断面図である。第2実施形態に係る半導体装置は、ソース電極溝4がゲート電極溝7よりも深く形成される点等で上述の第1実施形態と異なる。第2実施形態において説明しない構成、作用及び効果は、第1実施形態と実質的に同様であり重複するため省略する。
図18は、本発明の第2実施形態の変形例に係る半導体装置を説明する断面図である。第2実施形態の変形例に係る半導体装置は、ソース電極溝4の底部が基板1内に位置する点で上述の第2実施形態と異なる。第2実施形態の変形例において説明しない構成、作用及び効果は、上述の第2実施形態と実質的に同様であり重複するため省略する。
図19は、本発明の第3実施形態に係る半導体装置を説明する断面図である。第3実施形態に係る半導体装置は、ゲート電極溝7の底部が基板1に接する点で第2実施形態と異なる。第3実施形態において説明しない構成、作用及び効果は、第1及び第2実施形態と実質的に同様であり重複するため省略する。
図20は、本発明の第4実施形態に係る半導体装置を説明する断面図である。第4実施形態に係る半導体装置は、ドレイン電極13が形成されるドレイン電極溝25を備える点等で第1乃至第3実施形態と異なる。第4実施形態において説明しない構成、作用及び効果は、第1乃至第3実施形態と実質的に同様であり重複するため省略する。
上記のように、本発明を上記の実施形態によって記載したが、この開示の一部をなす論述及び図面は本発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施形態、実施例及び運用技術が明らかとなろう。
2 ドリフト領域
3 ウェル領域
4 ソース電極溝
5 ソース領域
6 ソース電極
7 ゲート電極溝
8 ゲート絶縁膜
9 ゲート電極
10 ゲート配線
11 シリコン酸化膜
12 ドレイン領域
13 ドレイン電極
14 層間絶縁膜
15 ソース配線
16 ドレイン配線
Claims (8)
- 基板と、
前記基板の第1主面に設けられ、前記基板よりも高不純物濃度の第1導電型のドリフト領域と、
前記ドリフト領域の前記第1主面と反対側の第2主面から、前記第2主面の垂直方向に形成されたソース電極溝と、
前記ソース電極溝の側面に接して、少なくとも一部が前記ドリフト領域内に形成された第2導電型のウェル領域と、
前記ソース電極溝の側面に接して、前記ウェル領域内に形成された第1導電型のソース領域と、
前記ソース領域と電気的に接続されたソース電極と、
前記ドリフト領域、前記ウェル領域及び前記ソース領域と接するように、前記第2主面から前記垂直方向に形成されたゲート電極溝と、
前記ゲート電極溝の表面に形成されたゲート絶縁膜と、
前記ゲート絶縁膜の表面に形成されたゲート電極と、
前記ドリフト領域内に、前記ウェル領域から離れて形成された第1導電型のドレイン領域と、
前記ドレイン領域と電気的に接続されたドレイン電極とを備える半導体装置において、
前記ゲート電極溝は、前記ソース電極溝に接するように形成され、
前記ソース電極と電気的に絶縁され、前記ソース電極溝内に前記ゲート電極に接して形成されたゲート配線を有することを特徴とする半導体装置。 - 前記ソース電極溝は、前記ゲート電極溝よりも深く形成されることを特徴とする請求項1に記載の半導体装置。
- 前記ゲート配線は、絶縁膜を介して前記基板に接するように形成されることを特徴とする請求項1又は2に記載の半導体装置。
- 前記第2主面に形成された層間絶縁膜と、
前記ソース電極と電気的に接続されるソース配線と、
前記ドレイン電極と電気的に接続されるドレイン配線と、を更に備え、
前記ソース配線及び前記ドレイン配線は、前記層間絶縁膜の前記第2主面と反対側かつ平行な主面に形成されることを特徴とする請求項1乃至3の何れか1項に記載の半導体装置。 - 前記基板は、絶縁体又は半絶縁体からなることを特徴とする請求項1乃至4の何れか1項に記載の半導体装置。
- 前記ゲート電極及び前記ゲート配線は、互いに同じ材料で形成されることを特徴とする請求項1乃至5の何れか1項に記載の半導体装置。
- 前記ゲート配線は、シリコンから形成され、表面に形成されたシリコン酸化膜により前記ソース電極と電気的に絶縁されることを特徴とする請求項1乃至6の何れか1項に記載の半導体装置。
- 前記ドリフト領域は、ワイドバンドギャップ半導体からなることを特徴とする請求項1乃至7の何れか1項に記載の半導体装置。
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