JP6460074B2 - 半導体ウエハと半導体素子の製造方法 - Google Patents
半導体ウエハと半導体素子の製造方法 Download PDFInfo
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- JP6460074B2 JP6460074B2 JP2016199483A JP2016199483A JP6460074B2 JP 6460074 B2 JP6460074 B2 JP 6460074B2 JP 2016199483 A JP2016199483 A JP 2016199483A JP 2016199483 A JP2016199483 A JP 2016199483A JP 6460074 B2 JP6460074 B2 JP 6460074B2
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- 239000004065 semiconductor Substances 0.000 title claims description 153
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 230000002093 peripheral effect Effects 0.000 claims description 112
- 238000000034 method Methods 0.000 claims description 25
- 230000036961 partial effect Effects 0.000 claims description 6
- 235000012431 wafers Nutrition 0.000 description 90
- 239000000126 substance Substances 0.000 description 23
- 230000000694 effects Effects 0.000 description 14
- 230000007423 decrease Effects 0.000 description 12
- 239000007788 liquid Substances 0.000 description 9
- 230000002829 reductive effect Effects 0.000 description 8
- 239000000243 solution Substances 0.000 description 6
- 238000002474 experimental method Methods 0.000 description 5
- 230000001629 suppression Effects 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000008155 medical solution Substances 0.000 description 3
- 239000011265 semifinished product Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02021—Edge treatment, chamfering
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Grinding Of Cylindrical And Plane Surfaces (AREA)
Description
10a:半導体ウエハの第1の主面
10b:半導体ウエハの第2の主面
10c:半導体ウエハの中央領域
10e:半導体ウエハの外周面
10t:半導体ウエハの厚肉領域
12:第1電極層
14:第2電極層
20:傾斜面
20a:傾斜面の外周部分
20b:傾斜面の内周部分
20c:傾斜面の中間部分
20e:傾斜面の外周縁
20f:傾斜面の内周縁
W:傾斜面の幅寸法
θ:傾斜面の傾斜角度
θ1:傾斜面の外周部分の傾斜角度
θ2:傾斜面の内周部分の傾斜角度
θ3:傾斜面の中間部分の傾斜角度
Claims (7)
- 外周面に沿って中央領域よりも厚みのある厚肉領域を有する半導体ウエハであって、
前記半導体ウエハの一方の主面は、前記中央領域と前記厚肉領域との間に位置する傾斜面を有し、
前記傾斜面は、前記中央領域側に位置する内周縁と前記厚肉領域側に位置する外周縁とを有し、前記内周縁から前記外周縁に向かうにつれて、前記半導体ウエハの厚みが増加するように傾斜しており、
前記傾斜面は、前記内周縁を含む内周部分と、前記外周縁を含む外周部分と、前記内周部分と前記外周部分との間に位置する中間部分とを有し、
前記中間部分の傾斜角度は90度未満であり、
前記外周部分と前記内周部分の少なくとも一方の傾斜角度は、前記中間部分の傾斜角度よりも小さい、
半導体ウエハ。 - 前記外周部分の前記傾斜角度は、前記中間部分の前記傾斜角度よりも小さい、請求項1に記載の半導体ウエハ。
- 前記内周部分の前記傾斜角度は、前記中間部分の前記傾斜角度に等しい、請求項2に記載の半導体ウエハ。
- 前記内周部分の前記傾斜角度は、前記中間部分の前記傾斜角度よりも小さい、請求項1に記載の半導体ウエハ。
- 前記外周部分の前記傾斜角度は、前記中間部分の前記傾斜角度に等しい、請求項4に記載の半導体ウエハ。
- 前記内周部分及び前記外周部分の両者の前記傾斜角度は、前記中間部分の前記傾斜角度よりも小さい、請求項1に記載の半導体ウエハ。
- 半導体素子の製造方法であって、
半導体ウエハの中央領域に、前記半導体素子の一部の構造を形成する工程と、
前記半導体ウエハを一方の主面側から研削することにより、前記半導体ウエハの外周縁に沿って前記中央領域よりも厚みのある厚肉領域を形成する工程と、
前記半導体ウエハの前記一方の主面側から、前記半導体ウエハの前記中央領域に前記半導体素子の一部の構造を形成する工程と、を備え、
前記厚肉領域を形成する工程では、前記半導体ウエハの前記一方の主面において、前記中央領域と前記厚肉領域との間に傾斜面をさらに形成し、
前記傾斜面は、前記中央領域側に位置する内周縁と前記厚肉領域側に位置する外周縁とを有し、前記内周縁から前記外周縁に向かうにつれて、前記半導体ウエハの厚みが増加するように傾斜しており、
前記傾斜面は、前記内周縁を含む内周部分と、前記外周縁を含む外周部分と、前記内周部分と前記外周部分との間に位置する中間部分とを有し、
前記中間部分の傾斜角度は90度未満であり、
前記内周部分と前記外周部分の少なくとも一方の傾斜角度は、前記中間部分の傾斜角度よりも小さい、
半導体素子の製造方法。
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JP2016199483A JP6460074B2 (ja) | 2016-10-07 | 2016-10-07 | 半導体ウエハと半導体素子の製造方法 |
US15/681,696 US9954059B1 (en) | 2016-10-07 | 2017-08-21 | Semiconductor wafer and method of manufacturing semiconductor element |
CN201710859278.8A CN107919382B (zh) | 2016-10-07 | 2017-09-21 | 半导体晶片和半导体元件的制造方法 |
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JP2016199483A JP6460074B2 (ja) | 2016-10-07 | 2016-10-07 | 半導体ウエハと半導体素子の製造方法 |
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JP2018060983A JP2018060983A (ja) | 2018-04-12 |
JP6460074B2 true JP6460074B2 (ja) | 2019-01-30 |
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JP (1) | JP6460074B2 (ja) |
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US8048775B2 (en) * | 2007-07-20 | 2011-11-01 | Alpha And Omega Semiconductor Incorporated | Process of forming ultra thin wafers having an edge support ring |
JP2009096698A (ja) * | 2007-10-19 | 2009-05-07 | Toshiba Corp | ウェーハ及びその製造方法 |
JP2009253143A (ja) * | 2008-04-09 | 2009-10-29 | Fuji Electric Device Technology Co Ltd | 半導体ウェハ研削用砥石、半導体ウェハ研削装置および半導体装置の製造方法 |
JP5012632B2 (ja) * | 2008-04-15 | 2012-08-29 | 富士電機株式会社 | 半導体装置の製造方法 |
JP5266869B2 (ja) * | 2008-05-19 | 2013-08-21 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP2011054808A (ja) * | 2009-09-03 | 2011-03-17 | Disco Abrasive Syst Ltd | ウエーハの加工方法及び該加工方法により加工されたウエーハ |
JP5441587B2 (ja) * | 2009-09-25 | 2014-03-12 | 株式会社ディスコ | ウエーハの加工方法 |
JP5772092B2 (ja) * | 2011-03-11 | 2015-09-02 | 富士電機株式会社 | 半導体製造方法および半導体製造装置 |
JP5796412B2 (ja) * | 2011-08-26 | 2015-10-21 | 三菱電機株式会社 | 半導体素子の製造方法 |
JP2014107312A (ja) * | 2012-11-26 | 2014-06-09 | Mitsubishi Electric Corp | 半導体ウェハの薄厚加工方法 |
JP6360750B2 (ja) * | 2014-08-26 | 2018-07-18 | 株式会社ディスコ | ウエーハの加工方法 |
JP6671246B2 (ja) * | 2016-06-01 | 2020-03-25 | 株式会社ディスコ | ウェーハの加工方法 |
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CN107919382A (zh) | 2018-04-17 |
US9954059B1 (en) | 2018-04-24 |
US20180102410A1 (en) | 2018-04-12 |
JP2018060983A (ja) | 2018-04-12 |
CN107919382B (zh) | 2020-12-04 |
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