JP6419500B2 - 半導体パッケージ - Google Patents
半導体パッケージ Download PDFInfo
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- JP6419500B2 JP6419500B2 JP2014187826A JP2014187826A JP6419500B2 JP 6419500 B2 JP6419500 B2 JP 6419500B2 JP 2014187826 A JP2014187826 A JP 2014187826A JP 2014187826 A JP2014187826 A JP 2014187826A JP 6419500 B2 JP6419500 B2 JP 6419500B2
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Description
Claims (5)
- 基板と、前記基板の上に配置された第1パターン部と、前記基板の上に配置され、前記第1パターン部の上面を露出させる開口部を有するはんだレジストパターンとを含み、第1素子が実装される下部パッケージと、
前記第1パターン部の上に配置される第2パターン部と、
前記第2パターン部を介して前記下部パッケージに接続され、少なくとも一つの金属材料部を含む金属ポストと、
第2素子が実装され、はんだボールを介して前記金属ポストに接続される上部パッケージと、
を含み、
前記第2パターン部は、前記第1パターン部の上面の少なくとも一部を露出させ、前記第1パターン部の上面、前記開口部の内壁及び前記はんだレジストパターンの上面の上に配置され、
前記金属ポストは、前記開口部を介して露出された前記第1パターン部の上に配置され、第1金属材料を含むはんだ部と、前記はんだ部の上に配置され、第2金属材料を含む金属材料部とを含み、
前記はんだ部は、前記開口部内に配置される第1部分と、前記第1部分の上に配置され、前記はんだレジストパターンの上に突出した第2部分とを含み、
前記第1部分の側面は、前記第2パターン部と直接接触し、
前記第1部分の下面は、前記第1パターン部と直接接触する半導体パッケージ。 - 前記はんだ部の前記第2部分は、上部に行くほど幅が減少し、前記第2部分の上端の幅が下端の幅の50%〜90%に形成される請求項1に記載の半導体パッケージ。
- 前記はんだ部は、側面が前記下部パッケージの基板の表面に対して5°〜45°に傾斜する請求項2に記載の半導体パッケージ。
- 前記はんだ部は、錫(Sn)と銅(Cu)の合金材料又は錫(Sn)と銀(Ag)の合金材料で構成される請求項1から3のいずれか一項に記載の半導体パッケージ。
- 前記はんだ部は、230℃〜250℃の溶融点を有する請求項1から4のいずれか一項に記載の半導体パッケージ。
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
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KR10-2013-0110974 | 2013-09-16 | ||
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KR102152865B1 (ko) * | 2014-02-06 | 2020-09-07 | 엘지이노텍 주식회사 | 인쇄회로기판, 이를 포함하는 패키지 기판 및 이의 제조 방법 |
JP2016171190A (ja) * | 2015-03-12 | 2016-09-23 | イビデン株式会社 | パッケージ−オン−パッケージ用プリント配線板 |
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JPH11145327A (ja) * | 1997-11-07 | 1999-05-28 | Shinko Electric Ind Co Ltd | 半導体装置および該半導体装置の実装構造 |
US6818545B2 (en) * | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
JP2007194436A (ja) * | 2006-01-19 | 2007-08-02 | Elpida Memory Inc | 半導体パッケージ、導電性ポスト付き基板、積層型半導体装置、半導体パッケージの製造方法及び積層型半導体装置の製造方法 |
JP4917874B2 (ja) * | 2006-12-13 | 2012-04-18 | 新光電気工業株式会社 | 積層型パッケージ及びその製造方法 |
JP5003260B2 (ja) * | 2007-04-13 | 2012-08-15 | 日本電気株式会社 | 半導体装置およびその製造方法 |
JP5217043B2 (ja) * | 2007-07-11 | 2013-06-19 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP5056718B2 (ja) * | 2008-10-16 | 2012-10-24 | 株式会社デンソー | 電子装置の製造方法 |
JP5193898B2 (ja) * | 2009-02-12 | 2013-05-08 | 新光電気工業株式会社 | 半導体装置及び電子装置 |
KR20100121231A (ko) * | 2009-05-08 | 2010-11-17 | 삼성전자주식회사 | 회로패턴 들뜸 현상을 억제하는 패키지 온 패키지 및 그 제조방법 |
US20110024899A1 (en) * | 2009-07-28 | 2011-02-03 | Kenji Masumoto | Substrate structure for cavity package |
US8482111B2 (en) * | 2010-07-19 | 2013-07-09 | Tessera, Inc. | Stackable molded microelectronic packages |
JP5599276B2 (ja) * | 2010-09-24 | 2014-10-01 | 新光電気工業株式会社 | 半導体素子、半導体素子実装体及び半導体素子の製造方法 |
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US8531021B2 (en) * | 2011-01-27 | 2013-09-10 | Unimicron Technology Corporation | Package stack device and fabrication method thereof |
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US9368438B2 (en) * | 2012-12-28 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package (PoP) bonding structures |
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US9252112B2 (en) | 2016-02-02 |
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TW201517222A (zh) | 2015-05-01 |
EP2849226A3 (en) | 2015-04-29 |
EP2849226B1 (en) | 2018-08-22 |
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