JP6057498B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6057498B2 JP6057498B2 JP2011050938A JP2011050938A JP6057498B2 JP 6057498 B2 JP6057498 B2 JP 6057498B2 JP 2011050938 A JP2011050938 A JP 2011050938A JP 2011050938 A JP2011050938 A JP 2011050938A JP 6057498 B2 JP6057498 B2 JP 6057498B2
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- 239000004065 semiconductor Substances 0.000 title claims description 42
- 239000000758 substrate Substances 0.000 claims description 62
- 229920005989 resin Polymers 0.000 claims description 57
- 239000011347 resin Substances 0.000 claims description 57
- 239000000919 ceramic Substances 0.000 claims description 54
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 27
- 229910052802 copper Inorganic materials 0.000 claims description 27
- 239000010949 copper Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 10
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 238000001721 transfer moulding Methods 0.000 claims description 3
- 238000012360 testing method Methods 0.000 description 7
- 230000008602 contraction Effects 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- 230000001154 acute effect Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 241000287463 Phalacrocorax Species 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 238000005242 forging Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000009291 secondary effect Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
2…ベース体
25…凹部
31…セラミック基板
32,33…銅板
4…半導体チップ
5…パッケージ(モールド樹脂)
Claims (8)
- 剛性を有する板状のベース体と、
前記ベース体上面に配置される外周端を露出させて表裏面に銅板が張り合わされた前記ベース体上面よりも幅の短いセラミック基板と、
を有し、
前記ベース体、前記セラミック基板および前記銅板がトランスファーモールド法によりモールド樹脂で封止される半導体装置において、
前記セラミック基板は、その周囲が前記銅板の外側に突出するよう面積が前記銅板よりも大きく設定され、且つ、前記セラミック基板の端部と前記ベース体上面との間には、前記モールド樹脂の一部が介在しており、
前記ベース体上面の少なくとも前記セラミック基板のコーナー部と対応する位置に屋根部が設けられており、前記屋根部と前記ベース体底面との連結で形成された庇状の凸部が前記ベース体側面に設けられ、
前記屋根部と前記底面とを連結する連結面を有し、当該連結面が、前記モールド樹脂の冷却時の収縮方向に対して垂直方向に傾斜していることを特徴とする、半導体装置。 - 前記ベース体底面に垂直な下部垂直面が形成されており、前記凸部が、前記下部垂直面を介した前記屋根部と前記底面との連結で形成されていることを特徴とする、請求項1記載の半導体装置。
- 前記屋根部に垂直な上部垂直面が形成されており、前記凸部が、前記上部垂直面を介した前記屋根部と前記底面との連結で形成されていることを特徴とする、請求項1又は2記載の半導体装置。
- 前記屋根部に連続して円弧状の円弧面が形成されており、前記凸部が、前記円弧面を介した前記屋根部と前記底面との連結で形成されていることを特徴とする、請求項1又は2記載の半導体装置。
- 前記屋根部と前記底面とを連結する連結面を有し、当該連結面が前記セラミック基板に対して傾斜していることを特徴とする、請求項1〜4のいずれかに記載の半導体装置。
- 前記凸部が、前記ベース体の側面全面に設けられていることを特徴とする、請求項1〜5のいずれかに記載の半導体装置。
- 前記凸部が、前記ベース体の側面の前記セラミック基板のコーナー部と対応する位置の間にも設けられていることを特徴とする、請求項1〜5のいずれかに記載の半導体装置。
- 前記ベース体と前記モールド樹脂の界面が粗く加工されていることを特徴とする、請求項1〜7のいずれかに記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011050938A JP6057498B2 (ja) | 2011-03-09 | 2011-03-09 | 半導体装置 |
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JP2011050938A JP6057498B2 (ja) | 2011-03-09 | 2011-03-09 | 半導体装置 |
Publications (2)
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JP2012190866A JP2012190866A (ja) | 2012-10-04 |
JP6057498B2 true JP6057498B2 (ja) | 2017-01-11 |
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JP2011050938A Active JP6057498B2 (ja) | 2011-03-09 | 2011-03-09 | 半導体装置 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7287706B2 (ja) | 2018-09-03 | 2023-06-06 | エルアール-シップデザイン・アーゲー | 船体の底面の領域に***部を有する船体 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004072126A (ja) * | 1992-06-03 | 2004-03-04 | Seiko Epson Corp | 半導体装置及びその製造方法 |
US5367196A (en) * | 1992-09-17 | 1994-11-22 | Olin Corporation | Molded plastic semiconductor package including an aluminum alloy heat spreader |
JP2000236048A (ja) * | 1999-02-16 | 2000-08-29 | Shindengen Electric Mfg Co Ltd | 樹脂封止型半導体装置 |
JP3630070B2 (ja) * | 2000-03-30 | 2005-03-16 | 株式会社デンソー | 半導体チップおよび半導体装置 |
JP4220641B2 (ja) * | 2000-01-13 | 2009-02-04 | 電気化学工業株式会社 | 樹脂モールド用回路基板と電子パッケージ |
JP2003158226A (ja) * | 2001-11-20 | 2003-05-30 | Sony Corp | 半導体装置 |
JP4333505B2 (ja) * | 2004-04-14 | 2009-09-16 | 株式会社デンソー | 半導体装置 |
JP2005332937A (ja) * | 2004-05-19 | 2005-12-02 | Mitsui High Tec Inc | 放熱部材付きリードフレーム及びその製造方法 |
JP4407489B2 (ja) * | 2004-11-19 | 2010-02-03 | 株式会社デンソー | 半導体装置の製造方法ならびに半導体装置の製造装置 |
JP2009064806A (ja) * | 2007-09-04 | 2009-03-26 | Mitsubishi Electric Corp | 回路基板及びその製造方法並びに半導体モジュール |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP7287706B2 (ja) | 2018-09-03 | 2023-06-06 | エルアール-シップデザイン・アーゲー | 船体の底面の領域に***部を有する船体 |
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