JP5715835B2 - 半導体パッケージ及びその製造方法 - Google Patents
半導体パッケージ及びその製造方法 Download PDFInfo
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Description
[第1の実施の形態に係る半導体パッケージの構造]
図1は、第1の実施の形態に係る半導体パッケージを例示する断面図である。図1を参照するに、半導体パッケージ10は、半導体チップ20と、第1配線層31と、第1絶縁層32と、第2配線層33と、第2絶縁層34と、第3配線層35と、第3絶縁層36と、第4配線層37と、ソルダーレジスト層38と、外部接続端子39とを有する。
次に、第1の実施の形態に係る半導体パッケージの製造方法について説明する。図3〜図16は、第1の実施の形態に係る半導体パッケージの製造工程を例示する図である。
次に、第1の実施の形態に係る半導体パッケージの実装例について説明する。図17は、第1の実施の形態に係る半導体パッケージの実装例を示す断面図である。図17を参照するに、マザーボード100上に半導体パッケージ101が実装され、更に半導体パッケージ101上に半導体パッケージ102が実装されている。なお、図17では、便宜上、半導体パッケージ101及び102は別符号としているが、何れも半導体パッケージ10(図1参照)と同一構造の半導体パッケージである。又、図17において、半導体パッケージ101及び102は、図1に示す半導体パッケージ10とは上下が反転した状態で描かれている。
第1の実施の形態の変形例1では、第1絶縁層32(封止絶縁層)から最も遠い絶縁層にあたるソルダーレジスト層に、ガラスクロス40を内蔵する例を示す。なお、第1の実施の形態の変形例1において、既に説明した実施の形態と同一構成部品についての説明は省略する。
第1の実施の形態の変形例2では、第1電極パッド31を設けない例を示す。なお、第1の実施の形態の変形例2において、既に説明した実施の形態と同一構成部品についての説明は省略する。
第1の実施の形態の変形例3では、第1電極パッド31を第1絶縁層32の下面より窪んだ位置に設ける例を示す。なお、第1の実施の形態の変形例3において、既に説明した実施の形態と同一構成部品についての説明は省略する。
図1において第2配線層33と第2絶縁層34との間に、更に絶縁層と配線層を交互に3層ずつ挿入した、全部で7つの配線層及び7つの絶縁層(1つのソルダーレジスト層を含む)を有する半導体パッケージ(便宜上、半導体パッケージ10Dとする)について、反りのシミュレーションを実行した。
20 半導体チップ
21 半導体基板
22 電極パッド
23 突起電極
31 第1配線層
31a 第1層
31b 第2層
32 第1絶縁層
32x 第1ビアホール
32y 第2ビアホール
32z 凹部
33 第2配線層
34 第2絶縁層
34x 第3ビアホール
35 第3配線層
36、46 第3絶縁層
36x 第4ビアホール
37 第4配線層
37x 凹部
38、48 ソルダーレジスト層
38x、48x、52x 開口部
39 外部接続端子
40 ガラスクロス
40a、40b ガラス繊維束
51 支持体
52 レジスト層
53 犠牲層
100 マザーボード
110 電極パッド
Claims (13)
- 半導体チップの回路形成面及び側面を封止する封止絶縁層と、
前記封止絶縁層の前記回路形成面側の面である第1面に交互に積層された複数の配線層及び複数の絶縁層と、を有し、
前記第1面に形成された配線層は、前記半導体チップと電気的に接続されており、
最外層の絶縁層は、最外層の配線層を露出する開口部を備え、
前記最外層の絶縁層が、織布又は不織布からなる補強部材を内蔵しているソルダーレジスト層である半導体パッケージ。 - 前記補強部材がガラスクロスである請求項1記載の半導体パッケージ。
- 前記開口部の側壁の断面が凹型R形状である請求項1又は2記載の半導体パッケージ。
- 前記開口部内に露出する前記最外層の配線層に、前記凹型R形状と連続した凹部が形成されている請求項3記載の半導体パッケージ。
- 前記補強部材を内蔵する絶縁層が、織布又は不織布に絶縁性樹脂を含浸させてなる請求項1乃至4の何れか一項記載の半導体パッケージ。
- 前記第1面に積層された最外層の配線層に第1の電極パッドが設けられ、
前記最外層の絶縁層に、前記第1の電極パッドを露出する開口が設けられている請求項1乃至5の何れか一項記載の半導体パッケージ。 - 前記封止絶縁層に、前記半導体チップの電極を露出するビアホールが形成され、
前記封止絶縁層の第1面に形成されている配線層と前記電極とを接続するビアが、前記ビアホール内に形成されている請求項1乃至6の何れか一項記載の半導体パッケージ。 - 前記封止絶縁層の第1面の反対面である第2面から露出する第2の電極パッドと、
前記封止絶縁層を貫通し、前記第1面に形成されている配線層と前記第2の電極パッドとを電気的に接続する貫通配線と、を更に有する請求項1乃至7の何れか一項記載の半導体パッケージ。 - 前記半導体チップの裏面及び前記第2の電極パッドの露出面は、前記第2面と面一である請求項8記載の半導体パッケージ。
- 前記半導体チップの裏面は、前記第2面と面一であり、
前記第2の電極パッドの露出面は、前記第2面よりも窪んでいる請求項8記載の半導体パッケージ。 - 支持体の一方の面に半導体チップを回路形成面を上にして配置する第1工程と、
前記半導体チップの回路形成面及び側面を封止するように、前記支持体の一方の面に封止絶縁層を形成する第2工程と、
前記封止絶縁層の前記回路形成面側の面である第1面に、複数の配線層及び複数の絶縁層を交互に積層し、最外層の絶縁層に最外層の配線層を露出する開口部を形成する第3工程と、
前記支持体を除去する第4工程と、を有し、
前記第3工程は、前記第1面に前記半導体チップと電気的に接続するように配線層を形成する工程と、前記最外層の絶縁層として織布又は不織布からなる補強部材を内蔵しているソルダーレジスト層を積層する工程と、を含む半導体パッケージの製造方法。 - 前記第3工程では、ブラスト処理により、側壁の断面が凹型R形状の開口部を形成する請求項11記載の半導体パッケージの製造方法。
- 前記第2工程よりも前に、前記支持体の一方の面に電極パッドを形成し、
前記第2工程では、前記半導体チップの回路形成面及び側面、並びに、前記電極パッドの上面及び側面を封止するように、前記支持体の一方の面に封止絶縁層を形成し、
前記第2工程と前記第3工程との間に、前記封止絶縁層を貫通し、前記電極パッドの上面を露出する貫通孔を形成し、
前記第3工程で前記第1面に形成する配線層は、前記貫通孔内に形成され前記電極パッドと電気的に接続される貫通配線を含む請求項11又は12記載の半導体パッケージの製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2011013180A JP5715835B2 (ja) | 2011-01-25 | 2011-01-25 | 半導体パッケージ及びその製造方法 |
US13/354,663 US9142524B2 (en) | 2011-01-25 | 2012-01-20 | Semiconductor package and method for manufacturing semiconductor package |
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US11882652B2 (en) | 2021-05-06 | 2024-01-23 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board |
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