JP5474218B2 - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 145
- 239000010410 layer Substances 0.000 claims description 300
- 239000002344 surface layer Substances 0.000 claims description 103
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- 239000012535 impurity Substances 0.000 description 18
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
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Description
本発明にかかる前提技術としての半導体装置(SBD)について、図15を用いて説明する。
ここでは、本発明にかかる半導体装置としてのショットキーバリアダイオード(SBD)について説明する。
次に、本発明にかかる半導体装置(SBD)の製造方法について、製造工程中の半導体装置の断面図を用いて以下説明する。以下に示す図6〜11の(a)は、SBDの外周端部とコンタクトセル7を含むA−A’間を含む部分断面図、図6〜11の(b)はSBDの外周端部と通常セル6のB−B’間を含む部分断面図である。図12〜図14はA−A’間とB−B’間を含むSBDの部分上面図である。
本発明にかかる実施の形態1によれば、通常セル6の配列中にコンタクトセル7が点在するセル配列を備える半導体装置であって、n+型半導体基板1上のn-型半導体層2と、n-型半導体層2内に埋没したp型埋め込み層5と、通常セル6、コンタクトセル7それぞれの中央部に形成されたp型表面層4とを備え、コンタクトセル7において、p型埋め込み層5はp型表面層4と接触し、コンタクトセル7のp型表面層4上に形成された、p+型コンタクト層8と、n-型半導体層2上にショットキー接合され、p+型コンタクト層8とオーミック接合されたアノード電極3とをさらに備え、p型埋め込み層5とアノード電極3とは、p型表面層4とp+型コンタクト層8とを介して接続されることで、電界強度低減によるリーク電流の低減、電流経路の拡大によるオン抵抗の低減、空乏層消滅までの時間を短縮することによるスイッチング時の高速動作を可能とする。
Claims (7)
- 第1セル(6)の配列中に第2セル(7)が点在するセル配列を備える、ショットキーバリアダイオードである半導体装置であって、
第1導電型の半導体基板(1)上にエピタキシャル成膜された第1導電型の半導体層(2)と、
前記半導体層(2)内に埋没した、第2導電型の半導体からなる埋め込み層(5)とを備え、
前記埋め込み層(5)は、前記第1セル(6)の周辺部に設けられるとともに、前記第2セル(7)の全面に設けられ、
前記半導体層(2)表面において、前記第2セル(7)の中央部に形成された第2導電型の半導体からなる第1表面層(4、4a、4b)、前記半導体層(2)表面において、前記第2セル(7)の中央部に形成された第2導電型の半導体からなるコンタクト層(8、8a)のうち少なくとも一方と、
前記半導体層(2)表面において、前記第1セル(6)の中央部に形成された第2導電型の半導体からなる第2表面層(4)とをさらに備え、
前記第2セル(7)において、前記埋め込み層(5)は前記第1表面層(4、4a、4b)、前記コンタクト層(8、8a)のうち少なくとも一方と接触し、
前記半導体層(2)上にショットキー接合され、前記第1表面層(4、4a、4b)、前記コンタクト層(8、8a)のうち少なくとも一方とオーミック接合されたアノード電極(3)をさらに備え、
前記埋め込み層(5)と前記アノード電極(3)とは、前記第1表面層(4、4a、4b)、前記コンタクト層(8、8a)のうち少なくとも一方を介して接続されることを特徴とする、
半導体装置。 - 前記第1表面層(4a)を備え、前記コンタクト層(8、8a)を備えない場合、
前記第1表面層(4a)の下層領域の濃度が、その上層領域の濃度よりも低いことを特徴とする、
請求項1に記載の半導体装置。 - 前記第1表面層(4、4b)および前記コンタクト層(8、8a)の双方を備える場合、
前記コンタクト層(8)が、前記第1表面層(4)上に形成され、
前記第2セル(7)において、前記埋め込み層(5)は前記第1表面層(4)と接触し、
前記埋め込み層(5)と前記アノード電極(3)とは、前記第1表面層(4)および前記コンタクト層(8)の双方を介して接続されることを特徴とする、
請求項1に記載の半導体装置。 - 前記コンタクト層(8)が、前記第1表面層(4)よりも平面視における占める幅が広いことを特徴とする、
請求項3に記載の半導体装置。 - 前記第1表面層(4、4b)および前記コンタクト層(8、8a)の双方を備える場合、
前記第1表面層(4b)が、前記コンタクト層(8a)を平面視上囲んで形成され、
前記第2セル(7)において、前記埋め込み層(5)は前記第1表面層(4b)および前記コンタクト層(8a)の双方と接触し、
前記埋め込み層(5)と前記アノード電極(3)とは、前記第1表面層(4b)および前記コンタクト層(8a)の双方を介して接続されることを特徴とする、
請求項1に記載の半導体装置。 - 前記アノード電極(3)の端部における、前記半導体層(2)表面に形成されたガードリング層(9)と、
前記アノード電極(3)の端部および前記ガードリング層(9)を覆って形成された絶縁膜(10)と、
前記半導体基板(1)下にオーミック接合されたカソード電極(11)とをさらに備えることを特徴とする、
請求項1〜5のいずれかに記載の半導体装置。 - 前記埋め込み層(5)が、前記ガードリング層(9)と接触して形成されることを特徴とする、
請求項6に記載の半導体装置。
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JP6029397B2 (ja) | 2012-09-14 | 2016-11-24 | 三菱電機株式会社 | 炭化珪素半導体装置 |
DE102013019851B4 (de) * | 2013-11-26 | 2015-10-22 | Infineon Technologies Ag | Schottky-Diode mit reduzierter Flussspannung |
CN104078516A (zh) * | 2014-04-21 | 2014-10-01 | 西安电子科技大学 | 基于离子注入的沟槽式浮动结碳化硅sbd器件及其制造方法 |
CN104201212B (zh) * | 2014-04-21 | 2017-12-01 | 西安电子科技大学 | 具有块状沟槽和埋层的浮动结碳化硅sbd器件 |
CN104037236B (zh) * | 2014-04-21 | 2017-10-13 | 西安电子科技大学 | 一种具有深沟槽的浮动结碳化硅sbd器件 |
CN104037237B (zh) * | 2014-04-21 | 2017-01-18 | 西安电子科技大学 | 一种具有环形块状埋层的沟槽式浮动结碳化硅sbd器件 |
JP6758987B2 (ja) * | 2016-08-04 | 2020-09-23 | 株式会社日立製作所 | 半導体装置 |
JP6666224B2 (ja) * | 2016-09-21 | 2020-03-13 | 株式会社東芝 | 半導体装置 |
US10157980B1 (en) * | 2017-10-25 | 2018-12-18 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device having diode devices with different barrier heights and manufacturing method thereof |
CN112216746B (zh) * | 2019-07-11 | 2024-05-14 | 即思创意股份有限公司 | 碳化硅半导体器件 |
CN114284343B (zh) * | 2021-12-23 | 2023-04-07 | 电子科技大学 | 一种适用于高温环境的碳化硅结势垒肖特基二极管 |
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US9117739B2 (en) * | 2010-03-08 | 2015-08-25 | Cree, Inc. | Semiconductor devices with heterojunction barrier regions and methods of fabricating same |
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JPH03248563A (ja) * | 1990-02-27 | 1991-11-06 | Shindengen Electric Mfg Co Ltd | ショットキバリア半導体装置 |
JP2002076370A (ja) * | 2000-09-05 | 2002-03-15 | Fuji Electric Co Ltd | 超接合ショットキーダイオード |
JP2004006723A (ja) * | 2002-03-25 | 2004-01-08 | Toshiba Corp | 高耐圧半導体装置及びその製造方法 |
JP2005229070A (ja) * | 2004-02-16 | 2005-08-25 | Matsushita Electric Ind Co Ltd | ショットキーバリアダイオードおよびその製造方法 |
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JP2010040857A (ja) * | 2008-08-06 | 2010-02-18 | Toshiba Corp | 半導体装置 |
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US8963276B2 (en) | 2015-02-24 |
DE112011104631B4 (de) | 2020-06-04 |
DE112011104631T5 (de) | 2013-10-02 |
JPWO2012090861A1 (ja) | 2014-06-05 |
WO2012090861A1 (ja) | 2012-07-05 |
CN103443925A (zh) | 2013-12-11 |
CN103443925B (zh) | 2016-03-09 |
US20130221477A1 (en) | 2013-08-29 |
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