JP5305980B2 - 不揮発性半導体記憶装置、及びその製造方法 - Google Patents
不揮発性半導体記憶装置、及びその製造方法 Download PDFInfo
- Publication number
- JP5305980B2 JP5305980B2 JP2009042748A JP2009042748A JP5305980B2 JP 5305980 B2 JP5305980 B2 JP 5305980B2 JP 2009042748 A JP2009042748 A JP 2009042748A JP 2009042748 A JP2009042748 A JP 2009042748A JP 5305980 B2 JP5305980 B2 JP 5305980B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- memory device
- semiconductor memory
- layers
- contact plug
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 206
- 238000004519 manufacturing process Methods 0.000 title claims description 56
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000003860 storage Methods 0.000 claims abstract description 13
- 230000007423 decrease Effects 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 17
- 230000006870 function Effects 0.000 claims description 15
- 238000010030 laminating Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 585
- 229910052751 metal Inorganic materials 0.000 description 51
- 239000002184 metal Substances 0.000 description 51
- 239000011229 interlayer Substances 0.000 description 46
- 230000004888 barrier function Effects 0.000 description 26
- 230000000694 effects Effects 0.000 description 23
- 229910004298 SiO 2 Inorganic materials 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 230000001681 protective effect Effects 0.000 description 17
- 229910052814 silicon oxide Inorganic materials 0.000 description 17
- 229910052581 Si3N4 Inorganic materials 0.000 description 12
- 239000010949 copper Substances 0.000 description 12
- 239000011572 manganese Substances 0.000 description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 12
- 239000010936 titanium Substances 0.000 description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 12
- 229910052721 tungsten Inorganic materials 0.000 description 12
- 239000010937 tungsten Substances 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 230000000052 comparative effect Effects 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- 101100292586 Caenorhabditis elegans mtr-4 gene Proteins 0.000 description 6
- 102100038712 Cap-specific mRNA (nucleoside-2'-O-)-methyltransferase 1 Human genes 0.000 description 6
- 101710203121 Cap-specific mRNA (nucleoside-2'-O-)-methyltransferase 1 Proteins 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 238000001459 lithography Methods 0.000 description 6
- 229910052748 manganese Inorganic materials 0.000 description 6
- 150000002736 metal compounds Chemical class 0.000 description 6
- 229910052707 ruthenium Inorganic materials 0.000 description 6
- 229910052715 tantalum Inorganic materials 0.000 description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 102100038716 Cap-specific mRNA (nucleoside-2'-O-)-methyltransferase 2 Human genes 0.000 description 1
- 101710203126 Cap-specific mRNA (nucleoside-2'-O-)-methyltransferase 2 Proteins 0.000 description 1
- 101150081243 STA1 gene Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Description
(第1実施形態に係る不揮発性半導体記憶装置100の構成)
先ず、図1を参照して、第1実施形態に係る不揮発性半導体記憶装置100の構成について説明する。図1は、本発明の第1実施形態に係る不揮発性半導体記憶装置100のブロック図である。
次に、図8〜図28を参照して、第1実施形態に係る不揮発性半導体記憶装置100の製造方法について説明する。図8〜図28は、第1実施形態に係る不揮発性半導体記憶装置100の製造工程を示す断面図である。
次に、第1実施形態に係る不揮発性半導体記憶装置100の効果について説明する。第1実施形態に係る不揮発性半導体記憶装置100は、上記積層構造に示したように高集積化可能である。
(第2実施形態に係る不揮発性半導体記憶装置の構成)
次に、図29を参照して、第2実施形態に係る不揮発性半導体記憶装置の構成について説明する。図29は、第2実施形態に係る不揮発性半導体記憶装置を示す断面図である。なお、第2実施形態において、第1実施形態と同様の構成については、同一符号を付し、その説明を省略する。
次に、図30〜図38を参照して、第2実施形態に係る不揮発性半導体記憶装置の製造方法について説明する。図30〜図38は、第2実施形態に係る不揮発性半導体記憶装置の製造工程を示す断面図である。
次に、第2実施形態に係る不揮発性半導体記憶装置の効果について説明する。第2実施形態に係る不揮発性半導体記憶装置は、第1実施形態と同様の特徴を有し、第1実施形態と同様の効果を奏する。
(第3実施形態に係る不揮発性半導体記憶装置の構成)
次に、図39を参照して、第3実施形態に係る不揮発性半導体記憶装置の構成について説明する。図39は、第3実施形態に係る不揮発性半導体記憶装置を示す断面図である。なお、第3実施形態において、第1及び第2実施形態と同様の構成については、同一符号を付し、その説明を省略する。
次に、第3実施形態に係る不揮発性半導体記憶装置の効果について説明する。第3実施形態に係る不揮発性半導体記憶装置は、第1実施形態と同様の特徴を有し、第1実施形態と同様の効果を奏する。
(第4実施形態に係る不揮発性半導体記憶装置の構成)
次に、図40を参照して、第4実施形態に係る不揮発性半導体記憶装置の構成について説明する。図40は、第4実施形態に係る不揮発性半導体記憶装置を示す断面図である。なお、第2実施形態において、第1〜第3実施形態と同様の構成については、同一符号を付し、その説明を省略する。
第4実施形態に係る不揮発性半導体記憶装置は、所定幅L20〜L24(L20>L21>L22>L23>L24)をもつステップSTa0〜STa4を有する。したがって、第2実施形態に係る不揮発性半導体記憶装置は、第1実施形態と比較して、第2コンタクトプラグ層55b〜55gの間の間隔を十分にとって配置することができる。これにより、第2実施形態に係る不揮発性半導体記憶装置は、第2コンタクトプラグ層55b〜58fが互いに接して生じるショートを抑制することができる。すなわち、第4実施形態に係る不揮発性半導体記憶装置は、第1実施形態よりも、その信頼性を高めることができる。
(第5実施形態に係る不揮発性半導体記憶装置の構成)
次に、図41を参照して、第5実施形態に係る不揮発性半導体記憶装置の構成について説明する。図41は、第5実施形態に係る不揮発性半導体記憶装置の第2コンタクトプラグ層55Ab〜55Agを示す上面図である。なお、第5実施形態において、第1〜第4実施形態と同様の構成については、同一符号を付し、その説明を省略する。
第5実施形態に係る不揮発性半導体記憶装置は、第1実施形態と同様の効果を奏する。さらに、第5実施形態に係る不揮発性半導体記憶装置は、ロウ方向から所定角度をもった方向に一列に並ぶ第2コンタクトプラグ層55Ab〜55Agを有する。したがって、第5実施形態に係る不揮発性半導体記憶装置は、第1実施形態と比較して、第2コンタクトプラグ層55Ab〜55Afの間の間隔を十分にとって配置することができる。よって、第5実施形態に係る不揮発性半導体記憶装置は、第2コンタクトプラグ層の間で起こりうるショートの抑制、及びリソグラフィ解像度の向上が可能となり、第1実施形態よりも、その信頼性を高めることができる。
(第6実施形態に係る不揮発性半導体記憶装置の構成)
次に、図42を参照して、第6実施形態に係る不揮発性半導体記憶装置の構成について説明する。図42は、第6実施形態に係る不揮発性半導体記憶装置の第2コンタクトプラグ層55Ab〜55Agを示す上面図である。なお、第6実施形態において、第1〜第5実施形態と同様の構成については、同一符号を付し、その説明を省略する。
第6実施形態に係る不揮発性半導体記憶装置は、第5実施形態と同様の特徴を有し、第5実施形態と同様の効果を奏する。さらに、第6実施形態に係る不揮発性半導体記憶装置は、ステップSTa0〜STa4を有し、第4実施形態と同様、占有面積を縮小させ且つ第2コンタクトプラグ層55Ab〜55Agの接触を抑制させることができる。
(第7実施形態に係る不揮発性半導体記憶装置の構成)
次に、図43及び図44を参照して、第7実施形態に係る不揮発性半導体記憶装置の構成について説明する。図43は、第7実施形態に係る不揮発性半導体記憶装置の第2コンタクトプラグ層55Bb〜55Bgを示す上面図である。図44は、第7実施形態に係る不揮発性半導体記憶装置の第2配線層53Ab〜53Agを示す上面図である。なお、第7実施形態において、第1〜第6実施形態と同様の構成については、同一符号を付し、その説明を省略する。
第7実施形態に係る不揮発性半導体記憶装置は、第5及び第6実施形態に係る不揮発性半導体記憶装置と同様の効果を奏する。また、第7実施形態に係る不揮発性半導体記憶装置において、第2コンタクトプラグ層55Bb〜55Bgの上端は、ステップSTb0〜STb4の設けられた直上の領域からはみ出すように形成されている。これにより、第7実施形態に係る不揮発性半導体記憶装置は、第5及び第6実施形態よりも第2コンタクトプラグ層55Bb〜55Bfをロウ方向に間隔を詰めて配置することができ、もって占有面積を縮小化することができる。
(第8実施形態に係る不揮発性半導体記憶装置の構成)
次に、図45を参照して、第8実施形態に係る不揮発性半導体記憶装置の構成について説明する。図45は、第8実施形態に係る不揮発性半導体記憶装置の第2配線層53Bb〜53Bgを示す上面図である。なお、第7実施形態において、第1〜第7実施形態と同様の構成については、同一符号を付し、その説明を省略する。
第8実施形態に係る不揮発性半導体記憶装置は、第7実施形態と同様の特徴を有し、第7実施形態と同様の効果を奏する。
(第9実施形態に係る不揮発性半導体記憶装置の構成)
次に、図46を参照して、第9実施形態に係る不揮発性半導体記憶装置の構成について説明する。図46は、第9実施形態に係る不揮発性半導体記憶装置の第2コンタクトプラグ層55Cb〜55Cgを示す上面図である。なお、第9実施形態において、第1〜第8実施形態と同様の構成については、同一符号を付し、その説明を省略する。
第9実施形態に係る不揮発性半導体記憶装置は、第5及び第6実施形態と同様の効果を奏する。
(第10実施形態に係る不揮発性半導体記憶装置の構成)
次に、図47を参照して、第10実施形態に係る不揮発性半導体記憶装置の構成について説明する。図47は、第10実施形態に係る不揮発性半導体記憶装置の第2コンタクトプラグ層55Cb〜55Cgを示す上面図である。なお、第10実施形態において、第1〜第9実施形態と同様の構成については、同一符号を付し、その説明を省略する。
第10実施形態に係る不揮発性半導体記憶装置は、第9実施形態と同様の特徴を有し、第9実施形態と同様の効果を奏する。さらに、第10実施形態に係る不揮発性半導体記憶装置は、ステップSTa0〜STa4を有し、第4実施形態と同様、占有面積を縮小させ且つ第2コンタクトプラグ層55Cb〜55Cgの接触を抑制させることができる。
以上、不揮発性半導体記憶装置の一実施形態を説明してきたが、本発明は、上記実施形態に限定されるものではなく、発明の趣旨を逸脱しない範囲内において種々の変更、追加、置換等が可能である。例えば、メモリ柱状半導体層37は、柱状に限られずU字状であってもよい。U字状のメモリ柱状半導体層37は、一対の柱状部、その柱状部の下端を連結する連結部を有する。
Claims (3)
- 電気的に書き換え可能な複数のメモリセルが直列に接続されたメモリストリング、及び前記メモリセルの制御電極に接続された配線を備える不揮発性半導体記憶装置であって、
前記メモリストリングは、
基板に対して垂直方向に延びる柱状部を含む半導体層と、
前記柱状部の側面を取り囲むように形成された電荷蓄積層と、
前記柱状部の側面及び前記電荷蓄積層を取り囲むように形成され、前記メモリセルの制御電極として機能する、積層された複数の第1導電層とを備え、
前記複数の第1導電層は、その端部の位置が異なるように階段状に形成された階段部を構成し、
前記配線は、
前記階段部を構成する前記第1導電層の上面から上方に延びる複数の第2導電層を備え、
前記複数の第2導電層は、それら上端が前記基板と平行な面において揃うように形成され且つその上端から下端へとその径が小さくなるように形成され、
前記複数の第2導電層は、その積層方向の長さが長いほど、その上端の径が大きくなるように形成され、
第1位置に位置する前記階段部のステップの幅は、前記第1位置よりも上層の第2位置に位置する前記階段部のステップの幅よりも大きい
ことを特徴とする不揮発性半導体記憶装置。 - 前記階段部のステップは、前記基板に平行な第1方向に一列に並び、
前記複数の第2導電層は、前記第1方向とは異なる第2方向に沿って並ぶ
ことを特徴とする請求項1記載の不揮発性半導体記憶装置。 - 電気的に書き換え可能な複数のメモリセルが直列に接続された複数のメモリストリングを有する不揮発性半導体記憶装置の製造方法であって、
複数の第1導電層を積層させる工程と、
前記複数の第1導電層を貫通させて貫通孔を形成する工程と、
前記貫通孔に面する側面に電荷蓄積層を形成する工程と、
前記貫通孔を埋めるように半導体層を形成する工程と、
前記複数の第1導電層にて、その端部の位置が異なるように階段状に形成された階段部を構成する工程と、
前記階段部を構成する前記第1導電層の上面から上方に延びる複数の第2導電層を形成する工程とを備え、
前記複数の第2導電層は、前記基板と平行な面において上端が揃うように形成されると共に上端から下端へとその径が小さくなるように形成され、且つその積層方向の長さが長いほど、その上端の径が大きくなるように形成され、
第1位置に位置する前記階段部のステップの幅が、前記第1位置よりも上層の第2位置に位置する前記階段部のステップの幅よりも大きくなるように、前記第2導電層を形成する
ことを特徴とする不揮発性半導体記憶装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009042748A JP5305980B2 (ja) | 2009-02-25 | 2009-02-25 | 不揮発性半導体記憶装置、及びその製造方法 |
US12/615,598 US7989880B2 (en) | 2009-02-25 | 2009-11-10 | Nonvolatile semiconductor memory device and method of manufacturing the same |
KR20100016752A KR101049299B1 (ko) | 2009-02-25 | 2010-02-24 | 비휘발성 반도체 메모리 장치 및 그 제조 방법 |
US13/172,330 US8759162B2 (en) | 2009-02-25 | 2011-06-29 | Nonvolatile semiconductor memory device and method of manufacturing the same |
US14/292,283 US9018696B2 (en) | 2009-02-25 | 2014-05-30 | Nonvolatile semiconductor memory device and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009042748A JP5305980B2 (ja) | 2009-02-25 | 2009-02-25 | 不揮発性半導体記憶装置、及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010199311A JP2010199311A (ja) | 2010-09-09 |
JP5305980B2 true JP5305980B2 (ja) | 2013-10-02 |
Family
ID=42630205
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009042748A Active JP5305980B2 (ja) | 2009-02-25 | 2009-02-25 | 不揮発性半導体記憶装置、及びその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (3) | US7989880B2 (ja) |
JP (1) | JP5305980B2 (ja) |
KR (1) | KR101049299B1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9773546B2 (en) | 2015-05-20 | 2017-09-26 | Samsung Electronics Co., Ltd. | Semiconductor devices including auxiliary bit lines |
US9780113B2 (en) | 2015-02-10 | 2017-10-03 | Samsung Electronics Co., Ltd. | Method for fabricating semiconductor device including a first ILD with sloped surface on a stacked structure and a second ILD on the first ILD |
Families Citing this family (93)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20100093350A (ko) * | 2009-02-16 | 2010-08-25 | 삼성전자주식회사 | 반도체 소자 및 그 형성방법 |
JP2011040706A (ja) * | 2009-07-15 | 2011-02-24 | Toshiba Corp | 不揮発性半導体記憶装置 |
KR101660944B1 (ko) | 2009-07-22 | 2016-09-28 | 삼성전자 주식회사 | 수직형의 비휘발성 메모리 소자 및 그 제조 방법 |
JP5394270B2 (ja) | 2010-01-25 | 2014-01-22 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
KR101652878B1 (ko) * | 2010-02-22 | 2016-09-01 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
JP5491982B2 (ja) * | 2010-06-21 | 2014-05-14 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
KR101744127B1 (ko) * | 2010-11-17 | 2017-06-08 | 삼성전자주식회사 | 반도체 소자 및 그 제조방법 |
KR101772572B1 (ko) * | 2010-12-06 | 2017-08-29 | 삼성전자주식회사 | 불휘발성 메모리 장치 |
US8329051B2 (en) * | 2010-12-14 | 2012-12-11 | Lam Research Corporation | Method for forming stair-step structures |
JP2012174892A (ja) * | 2011-02-22 | 2012-09-10 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JP5751552B2 (ja) * | 2011-03-04 | 2015-07-22 | マクロニクス インターナショナル カンパニー リミテッド | 積層した接続レベルを有する集積回路装置用マスク数の低減法 |
KR101721117B1 (ko) * | 2011-03-15 | 2017-03-29 | 삼성전자 주식회사 | 반도체 소자의 제조 방법 |
JP2012244180A (ja) * | 2011-05-24 | 2012-12-10 | Macronix Internatl Co Ltd | 多層接続構造及びその製造方法 |
US8530350B2 (en) | 2011-06-02 | 2013-09-10 | Micron Technology, Inc. | Apparatuses including stair-step structures and methods of forming the same |
JP5550604B2 (ja) * | 2011-06-15 | 2014-07-16 | 株式会社東芝 | 三次元半導体装置及びその製造方法 |
KR101843580B1 (ko) * | 2011-08-16 | 2018-03-30 | 에스케이하이닉스 주식회사 | 3차원 구조의 비휘발성 메모리 소자 및 그 제조 방법 |
JP2013055136A (ja) * | 2011-09-01 | 2013-03-21 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2013055142A (ja) * | 2011-09-01 | 2013-03-21 | Toshiba Corp | 不揮発性半導体記憶装置 |
KR101845511B1 (ko) | 2011-10-11 | 2018-04-05 | 삼성전자주식회사 | 수직 구조의 비휘발성 메모리 소자 제조 방법 |
JP2013131580A (ja) | 2011-12-20 | 2013-07-04 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2013187339A (ja) * | 2012-03-07 | 2013-09-19 | Toshiba Corp | 半導体装置及びその製造方法 |
KR101884002B1 (ko) | 2012-04-13 | 2018-08-01 | 삼성전자주식회사 | 콘택 구조물 형성 방법 |
JP2013258360A (ja) * | 2012-06-14 | 2013-12-26 | Toshiba Corp | 半導体装置の製造方法及び半導体装置 |
US8633099B1 (en) * | 2012-07-19 | 2014-01-21 | Macronix International Co., Ltd. | Method for forming interlayer connectors in a three-dimensional stacked IC device |
KR101970941B1 (ko) * | 2012-08-20 | 2019-08-13 | 삼성전자 주식회사 | 3차원 비휘발성 메모리 장치 및 그 제조 방법 |
KR102003529B1 (ko) | 2012-08-22 | 2019-07-25 | 삼성전자주식회사 | 적층된 전극들을 형성하는 방법 및 이를 이용하여 제조되는 3차원 반도체 장치 |
KR101974352B1 (ko) | 2012-12-07 | 2019-05-02 | 삼성전자주식회사 | 수직 셀을 갖는 반도체 소자의 제조 방법 및 그에 의해 제조된 반도체 소자 |
KR101986245B1 (ko) | 2013-01-17 | 2019-09-30 | 삼성전자주식회사 | 수직형 반도체 소자의 제조 방법 |
KR102037840B1 (ko) | 2013-04-11 | 2019-10-29 | 삼성전자주식회사 | 반도체 장치의 연결구조 및 제조 방법 |
KR102078597B1 (ko) | 2013-06-27 | 2020-04-08 | 삼성전자주식회사 | 반도체 장치 |
EP3024098A2 (en) | 2013-07-15 | 2016-05-25 | TE Connectivity AMP España S.L.U. | Telecommunications plug connector for high data rate uses |
KR20150057147A (ko) | 2013-11-18 | 2015-05-28 | 삼성전자주식회사 | 메모리 장치 |
KR20150080769A (ko) * | 2014-01-02 | 2015-07-10 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
JP5970004B2 (ja) * | 2014-01-09 | 2016-08-17 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
JP6129756B2 (ja) * | 2014-01-24 | 2017-05-17 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2015170692A (ja) | 2014-03-06 | 2015-09-28 | 株式会社東芝 | 半導体装置及びその製造方法 |
KR102171221B1 (ko) * | 2014-03-12 | 2020-10-28 | 삼성전자주식회사 | 수직형 불휘발성 메모리 장치 및 그 제조 방법 |
KR20150139255A (ko) * | 2014-06-03 | 2015-12-11 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조방법 |
KR20160015683A (ko) * | 2014-07-31 | 2016-02-15 | 에스케이하이닉스 주식회사 | 반도체 장치 |
US9601370B2 (en) * | 2014-09-12 | 2017-03-21 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method of manufacturing the same |
CN105514018B (zh) * | 2014-09-26 | 2019-02-26 | 中芯国际集成电路制造(北京)有限公司 | 制造半导体装置的方法 |
US9478546B2 (en) * | 2014-10-16 | 2016-10-25 | Macronix International Co., Ltd. | LC module layout arrangement for contact opening etch windows |
US9401369B1 (en) * | 2015-02-17 | 2016-07-26 | Macronix International Co., Ltd. | Memory device and method for fabricating the same |
KR102339740B1 (ko) * | 2015-03-10 | 2021-12-15 | 삼성전자주식회사 | 수직형 메모리 장치 |
US9673057B2 (en) | 2015-03-23 | 2017-06-06 | Lam Research Corporation | Method for forming stair-step structures |
US9613975B2 (en) | 2015-03-31 | 2017-04-04 | Sandisk Technologies Llc | Bridge line structure for bit line connection in a three-dimensional semiconductor device |
US9570392B2 (en) * | 2015-04-30 | 2017-02-14 | Kabushiki Kaisha Toshiba | Memory device and method for manufacturing the same |
US9461063B1 (en) * | 2015-05-06 | 2016-10-04 | Macronix International Co., Ltd. | Method for forming a semiconductor structure |
US9620515B2 (en) * | 2015-05-13 | 2017-04-11 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
KR102358302B1 (ko) * | 2015-05-21 | 2022-02-04 | 삼성전자주식회사 | 수직형 낸드 플래시 메모리 소자 및 그 제조 방법 |
US9780104B2 (en) * | 2015-09-10 | 2017-10-03 | Toshiba Memory Corporation | Semiconductor memory device and method of manufacturing the same |
US9991276B2 (en) | 2015-09-11 | 2018-06-05 | Toshiba Memory Corporation | Semiconductor device |
US20170147730A1 (en) * | 2015-11-23 | 2017-05-25 | Apple Inc. | Binary patterning for three-dimensional memory formation |
KR102536261B1 (ko) * | 2015-12-18 | 2023-05-25 | 삼성전자주식회사 | 3차원 반도체 장치 |
KR102497116B1 (ko) | 2015-12-30 | 2023-02-07 | 에스케이하이닉스 주식회사 | 전자 장치 및 그 제조 방법 |
US9741563B2 (en) | 2016-01-27 | 2017-08-22 | Lam Research Corporation | Hybrid stair-step etch |
US9768233B1 (en) * | 2016-03-01 | 2017-09-19 | Toshiba Memory Corporation | Semiconductor device and method of manufacturing the same |
US10396091B2 (en) * | 2016-03-17 | 2019-08-27 | Toshiba Memory Corporation | Semiconductor memory device |
US9871054B2 (en) | 2016-04-15 | 2018-01-16 | Toshiba Memory Corporation | Semiconductor device and method for manufacturing same |
KR102613511B1 (ko) * | 2016-06-09 | 2023-12-13 | 삼성전자주식회사 | 수직형 메모리 소자를 구비한 집적회로 소자 및 그 제조 방법 |
KR102619876B1 (ko) | 2016-07-19 | 2024-01-03 | 삼성전자주식회사 | 메모리 장치 |
JP7056024B2 (ja) | 2016-07-29 | 2022-04-19 | 住友化学株式会社 | 化合物、樹脂、レジスト組成物及びレジストパターンの製造方法 |
JP2018050016A (ja) | 2016-09-23 | 2018-03-29 | 東芝メモリ株式会社 | 半導体装置とその製造方法 |
KR102607595B1 (ko) | 2016-10-13 | 2023-11-30 | 삼성전자주식회사 | 유전체 층을 포함하는 반도체 소자 |
KR102650994B1 (ko) * | 2016-10-14 | 2024-03-26 | 삼성전자주식회사 | 메모리 장치 |
KR102633025B1 (ko) * | 2016-11-09 | 2024-02-05 | 에스케이하이닉스 주식회사 | 반도체 메모리 소자 |
CN106847821B (zh) * | 2017-03-07 | 2018-09-14 | 长江存储科技有限责任公司 | 半导体结构及其形成方法 |
KR20180107905A (ko) * | 2017-03-23 | 2018-10-04 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
JP2018170447A (ja) * | 2017-03-30 | 2018-11-01 | 東芝メモリ株式会社 | 半導体装置及びその製造方法 |
KR102343847B1 (ko) | 2017-04-25 | 2021-12-28 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 |
US10141330B1 (en) * | 2017-05-26 | 2018-11-27 | Micron Technology, Inc. | Methods of forming semiconductor device structures, and related semiconductor device structures, semiconductor devices, and electronic systems |
KR102421766B1 (ko) * | 2017-07-07 | 2022-07-18 | 삼성전자주식회사 | 3차원 반도체 장치 및 그 제조 방법 |
KR102428273B1 (ko) | 2017-08-01 | 2022-08-02 | 삼성전자주식회사 | 3차원 반도체 소자 |
KR102335107B1 (ko) * | 2017-10-16 | 2021-12-03 | 삼성전자 주식회사 | 로우 디코더를 포함하는 비휘발성 메모리 장치 |
CN107680972B (zh) * | 2017-11-01 | 2019-01-29 | 长江存储科技有限责任公司 | 一种3d nand存储器件及其制造方法 |
KR102565714B1 (ko) * | 2018-03-28 | 2023-08-10 | 삼성전자주식회사 | 적층 구조체를 갖는 반도체 소자 |
KR102624519B1 (ko) | 2018-04-25 | 2024-01-12 | 삼성전자주식회사 | 수직형 메모리 |
US11251191B2 (en) * | 2018-12-24 | 2022-02-15 | Sandisk Technologies Llc | Three-dimensional memory device containing multiple size drain contact via structures and method of making same |
CN109952645B (zh) * | 2019-02-11 | 2022-03-15 | 长江存储科技有限责任公司 | 利用保护层的原位形成的新颖蚀刻工艺 |
JP7134901B2 (ja) * | 2019-03-04 | 2022-09-12 | キオクシア株式会社 | 半導体記憶装置の製造方法 |
KR102598774B1 (ko) * | 2019-07-03 | 2023-11-07 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
KR20210154834A (ko) | 2019-07-16 | 2021-12-21 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | 3차원 메모리 디바이스 내의 자기 정렬 접점 및 그 형성 방법 |
KR102304931B1 (ko) * | 2019-09-04 | 2021-09-24 | 삼성전자주식회사 | 워드라인 영역의 면적을 감소시키는 3차원 플래시 메모리 |
KR20210039183A (ko) * | 2019-10-01 | 2021-04-09 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 이의 제조 방법 |
KR20210115716A (ko) | 2020-03-16 | 2021-09-27 | 삼성전자주식회사 | 스트링 선택 라인과 연결되는 선택 라인 스터드를 갖는 반도체 소자 |
US11985825B2 (en) | 2020-06-25 | 2024-05-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | 3D memory array contact structures |
US11778818B2 (en) * | 2020-07-21 | 2023-10-03 | Sandisk Technologies Llc | Three-dimensional memory device with punch-through-resistant word lines and methods for forming the same |
US11495618B2 (en) | 2020-07-30 | 2022-11-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional memory device and method |
US11716856B2 (en) | 2021-03-05 | 2023-08-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional memory device and method |
US11348640B1 (en) * | 2021-04-05 | 2022-05-31 | Micron Technology, Inc. | Charge screening structure for spike current suppression in a memory array |
JP2022159956A (ja) * | 2021-04-05 | 2022-10-18 | キオクシア株式会社 | 半導体記憶装置 |
US11715520B2 (en) | 2021-04-05 | 2023-08-01 | Micron Technology, Inc. | Socket structure for spike current suppression in a memory array |
US11862215B2 (en) | 2021-08-27 | 2024-01-02 | Micron Technology, Inc. | Access line having a resistive layer for memory cell access |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5016832B2 (ja) | 2006-03-27 | 2012-09-05 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
JP5330017B2 (ja) * | 2009-02-17 | 2013-10-30 | 株式会社東芝 | 不揮発性半導体記憶装置、及びその製造方法 |
-
2009
- 2009-02-25 JP JP2009042748A patent/JP5305980B2/ja active Active
- 2009-11-10 US US12/615,598 patent/US7989880B2/en active Active
-
2010
- 2010-02-24 KR KR20100016752A patent/KR101049299B1/ko active IP Right Grant
-
2011
- 2011-06-29 US US13/172,330 patent/US8759162B2/en active Active
-
2014
- 2014-05-30 US US14/292,283 patent/US9018696B2/en active Active
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9780113B2 (en) | 2015-02-10 | 2017-10-03 | Samsung Electronics Co., Ltd. | Method for fabricating semiconductor device including a first ILD with sloped surface on a stacked structure and a second ILD on the first ILD |
US9773546B2 (en) | 2015-05-20 | 2017-09-26 | Samsung Electronics Co., Ltd. | Semiconductor devices including auxiliary bit lines |
US10276237B2 (en) | 2015-05-20 | 2019-04-30 | Samsung Electronics Co., Ltd. | Semiconductor devices including auxiliary bit lines |
US10878901B2 (en) | 2015-05-20 | 2020-12-29 | Samsung Electronics Co., Ltd. | Semiconductor devices including auxiliary bit lines |
Also Published As
Publication number | Publication date |
---|---|
US20140264718A1 (en) | 2014-09-18 |
US20110256672A1 (en) | 2011-10-20 |
KR20100097066A (ko) | 2010-09-02 |
US7989880B2 (en) | 2011-08-02 |
KR101049299B1 (ko) | 2011-07-13 |
JP2010199311A (ja) | 2010-09-09 |
US8759162B2 (en) | 2014-06-24 |
US20100213526A1 (en) | 2010-08-26 |
US9018696B2 (en) | 2015-04-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5305980B2 (ja) | 不揮発性半導体記憶装置、及びその製造方法 | |
TWI778821B (zh) | 半導體記憶裝置 | |
JP5330017B2 (ja) | 不揮発性半導体記憶装置、及びその製造方法 | |
JP5253875B2 (ja) | 不揮発性半導体記憶装置、及びその製造方法 | |
JP2011142276A (ja) | 不揮発性半導体記憶装置、及びその製造方法 | |
JP5364394B2 (ja) | 不揮発性半導体記憶装置 | |
JP5430890B2 (ja) | 半導体記憶装置 | |
US20200176033A1 (en) | Semiconductor memory device | |
JP5550604B2 (ja) | 三次元半導体装置及びその製造方法 | |
TWI728875B (zh) | 半導體記憶裝置 | |
JP5150665B2 (ja) | 不揮発性半導体記憶装置 | |
JP2009224612A (ja) | 不揮発性半導体記憶装置、及びその製造方法 | |
JP2009004517A (ja) | 不揮発性半導体記憶装置及びその製造方法 | |
JP2013055136A (ja) | 不揮発性半導体記憶装置及びその製造方法 | |
JP2014027104A (ja) | 半導体装置及びその製造方法 | |
JP2009212280A (ja) | 不揮発性半導体記憶装置の製造方法 | |
JP5404149B2 (ja) | 半導体記憶装置 | |
JP2011054802A (ja) | 不揮発性半導体記憶装置、及びその製造方法 | |
US20130248975A1 (en) | Non-volatile semiconductor memory device and its manufacturing method | |
JP2019004146A (ja) | 半導体メモリ素子及びその製造方法 | |
JP2013131580A (ja) | 半導体装置及びその製造方法 | |
US10128267B2 (en) | Non-volatile memory device | |
TWI780515B (zh) | 半導體記憶裝置 | |
CN217955859U (zh) | 半导体存储装置 | |
US20210091002A1 (en) | Semiconductor memory device and method for manufacturing semiconductor memory device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110301 |
|
RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20130221 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130306 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130326 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130517 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130604 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130625 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 5305980 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |