JP7134901B2 - 半導体記憶装置の製造方法 - Google Patents
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- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H10B—ELECTRONIC MEMORY DEVICES
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- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Description
図1は、実施形態にかかる半導体記憶装置1の構成例を模式的に示す断面図である。図1に示すように、半導体記憶装置1は、シリコン基板等の基板10上に配置される周辺回路PERと、周辺回路PER上に配置される積層体LMと、を備える。
次に、図2~図13を用いて、実施形態の半導体記憶装置1の製造処理の例について説明する。図2~図13は、実施形態にかかる半導体記憶装置1の製造処理の手順の一例を示すフロー図である。図2~図13において、積層体LMの下層構造およびメモリ部MEMなどの一部の構成が省略される場合がある。
次に、図14を用いて、比較例の半導体記憶装置について説明する。図14は、比較例にかかる半導体記憶装置の製造処理の手順の一例を示すフロー図である。ただし、対比のため、図14右側に実施形態の半導体記憶装置1の製造処理の幾つかの段階を示す。
Claims (1)
- 複数の第1の層が第2の層を介して積層された積層体が形成された基板を準備し、
前記積層体の上層部分の前記第1の層が階段状となった第1の階段部を形成する第1の処理、
前記第1の階段部を構成する前記第1の層と同じ積層位置にある前記第1の層が階段状となった第2の階段部を形成する第2の処理、及び
前記第1の階段部と前記第2の階段部との間に前記第1の階段部を構成する前記第1の層と同じ積層位置にある前記第1の層から構成され、前記第1の階段部に対向するように配置される第3の階段部を形成する第3の処理をそれぞれ並行して実施し、
前記第1の階段部の最下段に対する最上段の位置を後退させていきながら、前記積層体の下層部分へ前記第1の階段部を延伸していく第4の処理、
前記第2の階段部の最下段に対する最上段の位置を後退させていきながら、前記積層体の下層部分へ前記第2の階段部を延伸していく第5の処理、及び
前記第3の階段部の最下段に対する最上段の位置を後退させることなく、前記積層体の下層部分へ前記第3の階段部を延伸していく第6の処理をそれぞれ並行して実施し、
前記第2の階段部の段差を維持しつつ前記第2の階段部を前記積層体の積層方向にエッチングして、前記第1の階段部を構成する前記第1の層より下層の前記第1の層を含む前記第2の階段部を形成する処理を実施する、
半導体記憶装置の製造方法。
Priority Applications (4)
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JP2019038626A JP7134901B2 (ja) | 2019-03-04 | 2019-03-04 | 半導体記憶装置の製造方法 |
TW108126526A TWI719558B (zh) | 2019-03-04 | 2019-07-26 | 半導體記憶裝置及其製造方法 |
CN201910733675.XA CN111653569B (zh) | 2019-03-04 | 2019-08-08 | 半导体存储装置及其制造方法 |
US16/561,823 US10930673B2 (en) | 2019-03-04 | 2019-09-05 | Semiconductor storage device and method for manufacturing semiconductor storage device |
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JP2019038626A JP7134901B2 (ja) | 2019-03-04 | 2019-03-04 | 半導体記憶装置の製造方法 |
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JP7134901B2 true JP7134901B2 (ja) | 2022-09-12 |
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JP2022191841A (ja) * | 2021-06-16 | 2022-12-28 | キオクシア株式会社 | 半導体記憶装置及び半導体記憶装置の製造方法 |
US11901287B2 (en) | 2021-09-02 | 2024-02-13 | Micron Technology, Inc. | Microelectronic devices with multiple step contacts extending to stepped tiers, and related systems and methods |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140021632A1 (en) | 2012-07-17 | 2014-01-23 | Jae-Goo Lee | Vertical type semiconductor device and method for manufacturing the same |
JP2014042029A (ja) | 2012-08-22 | 2014-03-06 | Samsung Electronics Co Ltd | 3次元半導体装置 |
US20140162420A1 (en) | 2012-12-07 | 2014-06-12 | Jung-Ik Oh | Method of fabricating semiconductor devices having vertical cells |
JP2015026674A (ja) | 2013-07-25 | 2015-02-05 | 株式会社東芝 | 不揮発性記憶装置およびその製造方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5305980B2 (ja) * | 2009-02-25 | 2013-10-02 | 株式会社東芝 | 不揮発性半導体記憶装置、及びその製造方法 |
KR20130072522A (ko) * | 2011-12-22 | 2013-07-02 | 에스케이하이닉스 주식회사 | 3차원 불휘발성 메모리 소자 및 그 제조 방법 |
KR20140075340A (ko) * | 2012-12-11 | 2014-06-19 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
TWI566365B (zh) * | 2014-07-07 | 2017-01-11 | 旺宏電子股份有限公司 | 接觸結構及形成方法以及應用其之回路 |
KR102333478B1 (ko) | 2015-03-31 | 2021-12-03 | 삼성전자주식회사 | 3차원 반도체 장치 |
US9786680B2 (en) * | 2015-09-10 | 2017-10-10 | Toshiba Memory Corporation | Semiconductor device |
TWI575661B (zh) * | 2015-10-02 | 2017-03-21 | 旺宏電子股份有限公司 | 具有鏡像落著區之多層三維結構 |
US10049744B2 (en) * | 2016-01-08 | 2018-08-14 | Samsung Electronics Co., Ltd. | Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same |
KR102509899B1 (ko) | 2016-01-14 | 2023-03-14 | 삼성전자주식회사 | 수직형 메모리 소자 및 그 형성 방법 |
US10269620B2 (en) * | 2016-02-16 | 2019-04-23 | Sandisk Technologies Llc | Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof |
TWI622131B (zh) * | 2016-03-18 | 2018-04-21 | Toshiba Memory Corp | Semiconductor memory device and method of manufacturing same |
CN109935593B (zh) * | 2017-03-08 | 2021-09-28 | 长江存储科技有限责任公司 | 一种3d nand存储器件及其制造方法 |
TWI678725B (zh) * | 2017-04-10 | 2019-12-01 | 旺宏電子股份有限公司 | 半導體元件及其關鍵尺寸的定義方法 |
US9960181B1 (en) * | 2017-04-17 | 2018-05-01 | Sandisk Technologies Llc | Three-dimensional memory device having contact via structures in overlapped terrace region and method of making thereof |
US10381364B2 (en) * | 2017-06-20 | 2019-08-13 | Sandisk Technologies Llc | Three-dimensional memory device including vertically offset drain select level layers and method of making thereof |
US10290645B2 (en) * | 2017-06-30 | 2019-05-14 | Sandisk Technologies Llc | Three-dimensional memory device containing hydrogen diffusion barrier layer for CMOS under array architecture and method of making thereof |
JP2019201038A (ja) | 2018-05-14 | 2019-11-21 | 東芝メモリ株式会社 | 半導体装置およびその製造方法 |
US10734400B1 (en) * | 2019-02-18 | 2020-08-04 | Sandisk Technologies Llc | Three-dimensional memory device including bit lines between memory elements and an underlying peripheral circuit and methods of making the same |
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- 2019-03-04 JP JP2019038626A patent/JP7134901B2/ja active Active
- 2019-07-26 TW TW108126526A patent/TWI719558B/zh active
- 2019-08-08 CN CN201910733675.XA patent/CN111653569B/zh active Active
- 2019-09-05 US US16/561,823 patent/US10930673B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140021632A1 (en) | 2012-07-17 | 2014-01-23 | Jae-Goo Lee | Vertical type semiconductor device and method for manufacturing the same |
JP2014042029A (ja) | 2012-08-22 | 2014-03-06 | Samsung Electronics Co Ltd | 3次元半導体装置 |
US20140162420A1 (en) | 2012-12-07 | 2014-06-12 | Jung-Ik Oh | Method of fabricating semiconductor devices having vertical cells |
JP2015026674A (ja) | 2013-07-25 | 2015-02-05 | 株式会社東芝 | 不揮発性記憶装置およびその製造方法 |
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CN111653569B (zh) | 2023-05-02 |
TW202034459A (zh) | 2020-09-16 |
US20200286912A1 (en) | 2020-09-10 |
JP2020145230A (ja) | 2020-09-10 |
CN111653569A (zh) | 2020-09-11 |
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