JP5209927B2 - 半導体構造の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 88
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 230000015654 memory Effects 0.000 claims description 112
- 238000000034 method Methods 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 2
- 238000007664 blowing Methods 0.000 claims 2
- 238000010030 laminating Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 8
- 241000920340 Pion Species 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 230000010354 integration Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Mram Or Spin Memory Techniques (AREA)
Description
チップ・セレクト・パッドP1, P2, P3, P4は、信号CS0,CSO_B,CS1,CS1_Bを、各々印加され、文字「H」は高電位を、文字「L」は低電位を、示している。信号CSO_Bは、信号CS0の逆位相信号を、信号CS1_Bは、信号CS1の逆位相信号を、表している。従って、フューズF1, F2, F3, F4の状態の組み合わせは、該当するダイ独自のアドレスとして動作する。表示されているCS0とCS1の状態は、各ダイのチップ・エネーブルCE信号が、高電位を出力するために必要とされるCS0とCS1の信号である。
D2 第2の半導体ダイ、第2のメモリ・ダイ
D3 第3の半導体ダイ、第3のメモリ・ダイ
D4 第4の半導体ダイ、第4のメモリ・ダイ
F1〜F4 フューズ
ID 識別回路
PIO1〜PIOn 入出力電導路(入出力パッド)
P1, P2, P3, P4 導電路(チップ・セレクト・パッド)
Claims (11)
- 識別回路と、シリコン貫通ビアにより構成されており、第1の半導体ダイと第2の半導体ダイの各々におけるメモリ回路に接続された複数の入出力導電路と、から各々が構成される前記第1の半導体ダイを第1の半導体ウエハに形成し、および、前記第1の半導体ダイと同一であって第2の半導体ウエハから切り取られた前記第2の半導体ダイを形成する工程と、
前記第1の半導体ダイの前記識別回路のプログラムとは異なるプログラムを、前記第2の半導体ダイの前記識別回路に書き込む工程と、
前記第1の半導体ダイおよび前記第2の半導体ダイが垂直方向に一直線上に配列されると共に、前記第1の半導体ダイにおける前記複数の入出力導電路の各々が、前記第2の半導体ダイにおける前記入出力導電路の各々に接続される状態で、前記第2の半導体ダイを前記第1の半導体ウエハの前記第1の半導体ダイ上に固着する工程と、
から構成され、
前記第2の半導体ダイの前記識別回路にプログラムを書き込む工程は、前記第2の半導体ダイを前記第1の半導体ウエハの前記第1の半導体ダイ上に固着する工程の前に行われることを特徴とする半導体構造の製造方法。 - 前記入出力導電路の各々が、前記第1の半導体ダイおよび前記第2の半導体ダイの各々の反対側における、第1の入出力パッドおよび第2の入出力パッドにより構成され、前記第1の入出力パッドおよび前記第2の入出力パッドが垂直方向に一直線上に配列されていることを特徴とする請求項1記載の半導体構造の製造方法。
- 前記第1の半導体ダイおよび前記第2の半導体ダイの一方を薄型化する工程を有することを特徴とする請求項1記載の半導体構造の製造方法。
- 前記第1および前記第2の半導体ダイと同一の、第3の半導体ダイを提供する工程と、
前記第1の半導体ダイおよび前記第2の半導体ダイの前記識別回路のプログラムとは異なったプログラムを、前記第3の半導体ダイの識別回路に書き込む工程と、
前記第2の半導体ダイ上に、前記第3の半導体ダイを固着する工程と、
を有することを特徴とする請求項1記載の半導体構造の製造方法。 - 前記第2の半導体ダイの前記識別回路に、プログラムを書き込む手段が、フューズを飛ばす手段、であることを特徴とする請求項1記載の半導体構造の製造方法。
- 前記第1の半導体ダイの前記識別回路に、プログラムを書き込む工程を有することを特徴とする請求項1記載の半導体構造の製造方法。
- 識別回路と、第1のメモリ・ダイおよび第2のメモリ・ダイの各々の反対側における第1の入出力パッドと第2の入出力パッドとから構成されており、前記第1入出力パッドおよび第2の入出力パッドが垂直方向に一直線上に配列される状態で、メモリ回路と前記識別回路に接続される複数の導電路と、から構成される、前記第1メモリ・ダイを第1の半導体ウエハに形成し、および前記第1メモリ・ダイと同一であって第2の半導体ウエハから切り取られた前記第2のメモリ・ダイを形成する工程と、
前記第1のメモリ・ダイの前記識別回路にプログラムを書き込む工程と、
前記第1のメモリ・ダイの前記識別回路の前記プログラムとは異なるプログラムを、前記第2のメモリ・ダイの前記識別回路に書き込む工程と、
前記第1のメモリ・ダイおよび前記第2のメモリ・ダイが、垂直方向に一直線上に配列される状態で、前記第2のメモリ・ダイの前記第2の入出力パッドを、前記第1のメモリ・ダイの前記第1の入出力パッドに物理的に固着することにより、前記第2のメモリ・ダイを前記第1の半導体ウエハの前記第1のメモリ・ダイの上に積層する工程と、
から構成され、
前記第1のメモリ・ダイの前記識別回路にプログラムを書き込む工程及び前記第2のメモリ・ダイの前記識別回路にプログラムを書き込む工程は、いずれも、前記第2のメモリ・ダイを前記第1の半導体ウエハの前記第1のメモリ・ダイの上に積層する工程の前に行われることを特徴とする半導体構造の製造方法。 - 前記形成する工程における前記第1のメモリ・ダイおよび前記第2のメモリ・ダイは、いずれか一方が選択されるように形成され、選択された前記第1のメモリ・ダイの前記導電路の一部または前記第2のメモリ・ダイの前記導電路の一部に、チップ・セレクト信号が印加されることを特徴とする請求項7記載の半導体構造の製造方法。
- 前記形成する工程における前記第1のメモリ・ダイおよび前記第2のメモリ・ダイは、前記チップ・セレクト信号が印加されると、前記第1のメモリ・ダイおよび前記第2のメモリ・ダイの、一方からプログラムの読み出し、または、一方へのプログラムの書き込みをするように形成されることを特徴とする請求項8記載の半導体構造の製造方法。
- 前記形成する工程における前記第1のメモリ・ダイおよび前記第2のメモリ・ダイの前記識別回路が、プログラム書き込み素子として、フューズにより構成され、前記第1のメモリ・ダイおよび前記第2のメモリ・ダイの前記識別回路へのプログラム書き込み手段が、選択されたフューズを飛ばす手段から構成されることを特徴とする請求項7記載の半導体構造の製造方法。
- 前記形成する工程における前記第1のメモリ・ダイおよび前記第2のメモリ・ダイの前記識別回路が、プログラム書き込み素子として、フラッシュ・メモリにより構成され、前記第1のメモリ・ダイおよび前記第2のメモリ・ダイの前記識別回路へのプログラム書き込み手段が、選択されたフラッシュ・メモリ・セルへの、データ書き込み手段から構成されることを特徴とする請求項7記載の半導体構造の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/716,104 US7494846B2 (en) | 2007-03-09 | 2007-03-09 | Design techniques for stacking identical memory dies |
US11/716,104 | 2007-03-09 |
Publications (2)
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JP2008227447A JP2008227447A (ja) | 2008-09-25 |
JP5209927B2 true JP5209927B2 (ja) | 2013-06-12 |
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JP2007245705A Active JP5209927B2 (ja) | 2007-03-09 | 2007-09-21 | 半導体構造の製造方法 |
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US7939941B2 (en) * | 2007-06-27 | 2011-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of through via before contact processing |
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US8749027B2 (en) * | 2009-01-07 | 2014-06-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Robust TSV structure |
US7839163B2 (en) * | 2009-01-22 | 2010-11-23 | International Business Machines Corporation | Programmable through silicon via |
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