TWI484603B - 具有散熱結構及電磁干擾屏蔽之半導體封裝件及其製造方法 - Google Patents
具有散熱結構及電磁干擾屏蔽之半導體封裝件及其製造方法 Download PDFInfo
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Description
本發明是有關於一種半導體封裝件及其製造方法,且特別是有關於一種改善散熱及屏蔽效率之半導體封裝件及其製造方法。
因為操作速度增加且裝置尺寸減少,半導體封裝件面臨電磁干擾及散熱問題。特別地,高時脈導致訊號位準(signal level)之間較多的頻率轉態(frequent transition),因而造成在高頻下或短波下較高強度的電磁放射(electromagnetic emission)。電磁放射可以從半導體元件輻射至鄰近的半導體元件。假如鄰近的半導體元件的電磁放射強度較高,此電磁放射係負面地影響半導體元件的運作。若整個電子系統內具有高密度分佈的半導體元件,則半導體元件之間的電磁干擾更顯嚴重。
一電子系統變得密集地集中,適當散熱變得困難。熱會降低效率,甚至損壞半導體封裝件及此電子系統的其它電子元件。為了因應半導體封裝件提升散熱及屏蔽效果,且避免不利地衝擊裝置可靠度、安全、週期時間(cycle time)及/或成本,一需求對應地存在。
根據本發明之一實施例,提出一種半導體封裝件。半導體封裝件包括一基板、一半導體晶片、一封裝體、一凹部、一電性連接件及一導電層。基板具有一接地元件。半導體晶片設於基板上,且具有數個銲墊(bond pad)。封裝體包覆半導體晶片。凹部位於封裝體且露出半導體晶片之一上表面的至少一部分。電性連接件設於至少二銲墊之間的凹部內,其中電性連接件超過半導體晶片之一側邊。導電層設於封裝體之一外表面之上方,其中導電層直接地接觸電性連接件與接地元件。其中,電性連接件與導電層的一組合提供半導體封裝件散熱及屏蔽電磁干擾。
根據本發明之另一實施例,提出一種半導體封裝件。半導體封裝件包括一基板、一半導體晶片、一封裝體、一凹部及一元件。基板具有接地元件。半導體晶片設於基板上,且具有數個銲墊。封裝體包覆半導體晶片。凹部位於封裝體且露出半導體晶片之一上表面的至少一部分。元件係耦接至半導體晶片該上表面與該封裝體以提供該半導體封裝件散熱及電磁干擾屏蔽之功能。
根據本發明之另一實施例,提出一種半導體封裝的製造方法。製造方法包括以下步驟。設置一半導體晶片於一基板,其中半導體晶片具有一側面及一上表面,且基板包
括一接地元件;形成一封裝件包覆半導體晶片之側面,其中封裝體定義一凹部露出半導體晶片之上表面;切割封裝體、基板及接地元件,以露出接地元件之一側壁;以及,形成一導電層覆蓋封裝體之一外表面及從凹部露出之半導體晶片之上表面,且接觸露出之接地元件。
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式,作詳細說明如下:
請參照第1A圖,其繪示數個實施例之一者的半導體封裝件的剖視圖。半導體封裝件100包括一基板110、一晶片120、位於封裝體140中之一凹部125、一導電層130及數個銲線150。
基板110包括至少一接地元件111、至少一導通孔112及至少一銲墊113,且具有相對之上表面110u與下表面110b。接地元件111位於基板110之上表面110u與下表面110b之間,但與上表面110u及下表面110b隔離。即,接地元件111設於基板110內。然而,另一實施例之接地元件111可延伸至基板110的上表面110u及下表面110b之至少一者。接地元件111的一外表面111s從基板110的一外側面110s露出。一些實施例中,接地元件111可包括一環,其實質上係一沿基板110的邊界延伸的連續圖案,且
從基板110的外側面110s露出。一些實施例中,接地元件111可包括一部分導通孔。
如第1A圖所示,基板110的外側面110s、封裝體140之外側面140s、接地元件111的外側面111s實質上共面。然而,其它實施例中此些表面並非全部需要共面。
導通孔112延伸於基板110之上表面110u與下表面110b之間。銲墊113形成於基板110之上表面110u。接地元件111、導通孔112與銲墊113中至少二者可透過形成於基板110之上表面110u的一走線層(未繪示)彼此電性連接,或透過一銲線層(未繪示)與形成於基板110中的走線層彼此電性連接。此外,此些導通孔112之一者可電性連接於一外部接地電壓,使接地元件111可電性連接於該外部接地電壓。
半導體晶片120係以朝上方位(face-up)設於基板110上,且具有側面120s及上表面120u並包括至少一銲墊121。本例中,上表面120u係晶片120之主動面,銲墊121形成於上表面120u上。銲線150連接半導體晶片120之銲墊121與基板110之銲墊113。另一實施例中,半導體晶片120可以是以朝下方位(face-down)設於基板110上並以銲球(bone ball)電性連接於基板110,此種半導體晶片120稱為”覆晶(flip chip)”
導電層130包括位於凹部125內的電性連接件131,
及全覆蓋屏蔽件(conformal shielding)132,其中凹部125係位於晶片120上方。凹部125露出晶片120之上表面120u,且電性連接件131覆蓋晶片120之上表面120u。電性連接件131可包括鋁、銅、鉻、錫、金、銀、鎳、不銹鋼及/或其合金,或任何其它材料。此外,電性連接件131可包括相似或相同於全覆蓋屏蔽件132的材料。較佳地,導電層130包括具有高熱傳導係數及高導電性的材料。
如第1A圖所示,導電層130覆蓋封裝體140的外表面、接地元件111的外表面111s及從凹部125露出之晶片120之上表面120u。藉由晶片120與導電層130直接接觸,從晶片120產生的熱便可以透過導電層130有效率地傳送至外部。此外,導電層130可同時用作一散熱元件及一電磁干擾屏蔽元件。
電性連接件131可如圖所示完全地填滿凹部125。例如,電性連接件131的上表面131u與封裝體140之上表面140u實質上共面。填入凹部125的電性連接件131可作為一緩衝層(buffer layer),以緩和封裝體140變形所導致的應力。另一例中,電性連接件131可突出於封裝體140之上表面140u上方。另一例中,電性連接件131可只填入凹部125之一部分。
全覆蓋屏蔽件132覆蓋封裝體140的外表面(上表面140u及外側面140s)、電性連接件131的上表面131u及接
地元件111。全覆蓋屏蔽件132可包括上述關於電性連接件131的任一材料或任何其它材料。全覆蓋屏蔽件132可以是單層或多層結構。當全覆蓋屏蔽件132係多層結構,例如是三層結構,其內層、中間層及外層分別是不銹鋼層、銅層及不銹鋼層。一實施例中,全覆蓋屏蔽件132係雙層結構,其內層係銅層,而其外層係不銹鋼層。此外,全覆蓋屏蔽件132的厚度較佳但非限定地大於50微米,以同時提高全覆蓋屏蔽件132的散熱效果及屏蔽效果。
封裝體140包覆晶片120之側面120s。封裝體140可包括酚醛基樹脂(Novolac-based resin)、環氧基樹脂(epoxy-based resin)、矽基樹脂(silicone-based resin)或其他適當之包覆劑。封裝體140亦可包括適當之填充劑,例如是粉狀之二氧化矽。一實施例中,封裝體140係封膠(molding compound)或預浸材疊層(prepreg lamination)。
請參照第1B圖,其繪示第1A圖之俯視圖。數個接地元件111環繞半導體晶片120。本例中,凹部125及電性連接件131完全地延伸穿越封裝體140。此外,電性連接件131未接觸銲墊113或銲線150,以避免電性短路。然而,另一例之凹部125及電性連接件131可部分地延伸穿越封裝體140。例如,如第2圖所示,其繪示依照本發明另一實施例之半導體封裝件之俯視圖。此例中,凹部125及電性連接件131延伸於封裝體140之相對的數個外側面
140s之間,但此非用以限制本發明實施例。
請參照第3圖,其繪示第1A圖之導電層130在不同操作頻率下的屏蔽效果圖。曲線S1顯示當凹部125未形成於封裝體140時,導電層130在第一共振頻率f1產生最差的屏蔽效果。曲線S2顯示當凹部125形成於半導體封裝件時,導電層130產生最差屏蔽效果的頻率轉移至一共振頻率f2。因此,藉由凹部125的設計,可以增加對應最差屏蔽效果的共振頻率,使其超過晶片120的操作頻率,因此提升導電層130的屏蔽效果。
如第4圖所示,其繪示依照本發明另一實施例之半導體封裝件的剖視圖。半導體封裝件200包括基板110、半導體晶片120、凹部125、封裝體140、導電層230及多條銲線150。導電層230包括填充物231及全覆蓋屏蔽件232。填充物231覆蓋位於凹部125內之全覆蓋屏蔽件232。全覆蓋屏蔽件232均勻地覆蓋封裝體140的外表面、接地元件111的外側面111s、從凹部125露出之晶片120之上表面120u。更特別地,全覆蓋屏蔽件232直接接觸晶片120從凹部125露出之上表面120u。
填充物231可以是導電性或絕緣性,且可包括例如是一金屬,如銅或一高聚物(high polymer)。此外,凹部125內之填充物231可作為一緩衝層,以減緩任何封裝體140變形所導致的應力集中。填充物231完全地填入凹部125,
使填充物231之上表面231u與全覆蓋屏蔽件232之上表面132u實質上共面。另一例中,填充物231之上表面231u可突出於全覆蓋屏蔽件232之上表面132u。另一例中,填充物231可填入凹部125之一部分,使填充物231之上表面231u陷入至全覆蓋屏蔽件232之上表面132u以下。
如第4圖所示,藉由透過凹部125而直接設置全覆蓋屏蔽件232於晶片120之上表面120u,可提升散熱性。凹部125的設計可增加對應於最差屏蔽效果的頻率,從而提升屏蔽效果。
請參照第5圖,其繪示依照本發明另一實施例之半導體封裝件的剖視圖。半導體封裝件300包括基板110、半導體晶片120、凹部125、封裝體140、導電層330及多條銲線150。封裝體140之一外表面包括一上表面140u及一外側面140s。導電層330包括一導電材料331及一全覆蓋屏蔽件132。導電材料331覆蓋晶片120之上表面120u、封裝體140之上表面140u及凹部125。全覆蓋屏蔽件132覆蓋導電材料331之上表面331u、封裝體140之外側面140s及接地元件111。
如第5圖所示,導電材料331包括一第一電性連接件3311及一第二電性連接件3312。第一電性連接件3311填入凹部125,且第二電性連接件3312覆蓋第一電性連接件3311之上表面3311u及封裝體140之上表面140u。第一電
性連接件3311及第二電性連接件3312可相似於如上所述之電性連接件131。
請參照第6圖,其繪示依照本發明另一實施例之半導體封裝件的剖視圖。半導體封裝件400包括基板110、半導體晶片120、凹部125、封裝體440、導電層430及銲線150。導電層430覆蓋晶片120之上表面120u、封裝體440之外側面440s及基板110之上表面110u的一部分。導電層430具有一外側面430s,其與基板110之外側面110s實值上共面。導電層430覆蓋接地元件111從基板110之上表面110u露出的上表面,且導電層430因此電連接於一接地電壓。此外,導電層430可覆蓋一導通孔銲墊,其透過導通孔112電連接於一接地電壓,且未被封裝體440覆蓋。
封裝體440形成於半導體晶片120之邊緣,且包覆銲線150、晶片120之銲墊121、基板110之上表面110u未被導電層430覆蓋的部分及基板110之銲墊113。封裝體440因此防止導電層430電性連接於銲線150或銲墊113、121。如此一來,封裝體440可包括數個分離設置之子封裝體,其中,各子封裝體包覆對應之銲線150及銲墊113、121。本例之封裝體440的外側面440s係一曲面。例如,封裝體440之剖面可以是一橢圓形或一圓形,或任何其它包括非曲面的外形。
請參照第7圖,其繪示依照本發明另一實施例之半導
體封裝件的剖視圖。半導體封裝件500包括基板110、半導體晶片120、凹部125、封裝體440、導電層430及多條銲線150。除了封裝體440之外側面440s係平面外,第7圖之實施例相似於第6圖。例如,封裝體440之剖面輪廓可以是矩形或多邊形。封裝體440之結構視共振頻率而定,且較佳地避免導電層與半導體晶片之間的短路。
請參照第8圖,其繪示依照本發明另一實施例之半導體封裝件的剖視圖。半導體封裝件600包括基板110、半導體晶片120、凹部125、封裝體440、導電層430、多條銲線150及圍牆(dam)660。圍牆660環繞銲線150、半導體晶片120之銲墊121及基板110的銲墊113。封裝體440填入圍牆660所定義的空間,且更包覆銲線150。透過圍牆660的設計,可有效地控制封裝體440的外形,以防止導電層430電性連接銲線150與銲墊113、121。另外,圍牆660可包括數個分離之子圍牆,而定義出凹部125,其中填入凹部125之各子封裝體包覆對應之銲線150及銲墊113、121。
圍牆660可以是框架,其透過表面黏貼技術(surface adhesive technology,SMT)或塗佈技術形成於晶片120上。此外,圍牆660可以是導電性或絕緣性,例如是金屬或相似於導電層430的材料。
請參照第9A圖,其繪示依照本發明另一實施例之半
導體封裝件的剖視圖。半導體封裝件700包括基板110、半導體晶片120、封裝體140、導電層130及銲線150。導電層130包括填充物231及全覆蓋屏蔽件132。填充物231佔據且填入全覆蓋屏蔽件132之凹部725。全覆蓋屏蔽件132均勻地覆蓋封裝體140的外表面、接地元件111及晶片120的上表面120u。
如第9A圖所示,凹部725可以是一圖案化凹部,且包數個子凹部726。至少一子凹部726與晶片120之上表面120u隔離,且至少一子凹部726接觸晶片120之上表面120u。另一例中,所有的子凹部726可接觸晶片120之上表面120u。
請參照第9B圖,其繪示第9A圖之半導體封裝件700的俯視圖。各子凹部726呈長條矩形(rectangular strip),相較於其它具有相同長度的子凹部726,位於中間的子凹部726具有一較長長度。雖然圖未繪示,另一例中,凹部725可排列成一開放或封閉環形,例如是圓形、橢圓、多邊形或一曲線形。
請參照第9C圖,其繪示第9A圖之半導體封裝件700之俯視圖。如圖所示,各子凹部726的外形,如從上方看去,為一圓形。另一例中,各子凹部726的剖面形狀可以是多邊形及/或曲線形,其中多邊形為矩形、而曲線形為橢圓形或任何其它曲線形。
請參照第10圖,其繪示依照本發明另一實施例之半導體封裝件的剖視圖。半導體封裝件800包括基板110、半導體晶片120、凹部125、封裝體140、導電層130及銲線150。封裝體140具有彼此平行而非共面之第一外側面140s1及第二外側面140s2。基板110之外側面110s與第一外側面140s1共面。如此結構可由半穿切(half-cut)形成,且所有實施例之半導體封裝件皆可採用類似方法形成相似第10圖之半穿切結構。
請參照第11圖,其繪示依照本發明另一實施例之半導體封裝件的剖視圖。半導體封裝件900包括基板110、半導體晶片120、凹部125、封裝體140、導電層130及多條銲線150。基板110具有第一外側面110s1與第二外側面110s2,其中第一外側面110s1與第二外側面110s2間隔一距離,而非共面。基板110之第二外側面110s2與封裝體140之外側面140s2共面。如此的結構係由”半穿切”方法形成,且所有實施例之半導體封裝件亦可採用類似方法形成相似第11圖之半穿切結構。請參照第12A圖,其繪示第1圖之半導體封裝件100之熱阻(TR)的模擬數據圖。半導體封裝件100的尺寸以10×10毫米,而晶片120的尺寸以5×5×0.1毫米為例。封裝體140之厚度H1介於0.45與1.17毫米之間。半導體封裝件100之電性連接件131之厚度H2介於約0.325與1.045毫米之間。導電層130的厚
度與封裝體140的厚度決定熱阻(TR)。
請參照第12B圖,其繪示第5圖之半導體封裝件300之熱阻(TR)的模擬數據圖。半導體封裝件300的尺寸以10×10毫米,而晶片120的尺寸以5×5×0.1毫米為例。封裝體140之厚度H1及第二材料3312的厚度介於0.45與1.17毫米之間。考慮到銲線150,第一電性連接件3311的厚度H3約0.1毫米,而第二電性連接件3312的厚度H4介於0.225與0.945之間。第一電性連接件3311的厚度及第二電性連接件3312的厚度決定熱阻(TR)。
由於半導體封裝件300之導電層330的厚度及面積大於半導體封裝件100之導電層130的厚度及面積,故半導體封裝件300的熱阻(TR)低於半導體封裝件100。因此,相較於半導體封裝件100,半導體封裝件300具有較佳熱傳導性(TR愈低,熱傳導性愈佳)。如第12A圖所示,當封裝體140的厚度約為1.17毫米,半導體封裝件100具有最大熱傳導性能。如第12B圖所示,當封裝體140及第二電性連接件3312的厚度約為1.17毫米,半導體封裝件300具有最大熱傳導性能。
請參照第13A至13F圖,其繪示第1A圖之半導體封裝件100的製造步驟圖。如第13A圖所示,設置半導體晶片120於基板110,例如使用黏貼層。晶片120具有側面120s及上表面120u,且基板110包括至少一接地元件111。
銲線150連接半導體晶片120與基板110。
如第13B圖所示,可採用例如是壓縮成型(compression molding)、注射成型(injection molding)、轉注成型(transfer molding)或任何其它製程,形成封裝體140以包覆半導體晶片120及銲線150。如第13C圖所示,可採用例如是圖案化技術或任何其它製程,形成凹部125於封裝體140中,其中凹部125露出半導體晶片120之部分上表面120u。圖案化技術例如是微影製程(photolithography)、化學蝕刻(chemical etching)、雷射鑽孔(laser drilling)、機械鑽孔(mechanical drilling)、磨削等。
如第13D圖所示,增加電性連接件131填入凹部125且覆蓋露出之晶片120之上表面120u。電性連接件131可採用例如是點膠、塗佈方法或任何其它製程形成。一些實施例中,電性連接件131可與全覆蓋屏蔽件132於如後所述之第13E圖的切割製程後之同一製程形成。本例中,電性連接件131之上表面131u及封裝體140之上表面140u係共面。
如第13E圖所示,基板110設於載板160之後,沿經過封裝體140、基板110及接地元件111的路徑P,切割封裝體的任一側面。切割以露出接地元件111,且可採用雷射、刀片或任何其它手段。本例中,係以全穿切(full-cut)
方法形成切割封裝體140及基板110的切割路徑P,。然而,本實施例之切割方法不受本例所限。
如第13F圖所示,形成全覆蓋屏蔽件132覆蓋封裝體140之外表面、電性連接件131之上表面131u、接地部111露出之外側面111s及基板110之外側面110s。全覆蓋屏蔽件132與電性連接件131構成導電層130。電性連接件131全覆蓋屏蔽件132連同電性連接件131形成導電層130。形成全覆蓋屏蔽件132的方法包括化學氣相沈積、無電鍍法(electroless plating)、電解電鍍(electrolytic plating)、印刷、旋塗、噴塗、濺鍍(sputtering)、真空沈積法(vacuum deposition)或任何其它方法。
請參照第14圖,其繪示第4圖之半導體封裝件200的製造步驟圖。在切割後,形成全覆蓋屏蔽件132均勻地覆蓋封裝體140的數個外表面、接地部111露出之數個外側面111s及基板110之數個外側面110s。全覆蓋屏蔽件132可採用如上所述之第13F圖的方法形成。雖然未繪示,半導體封裝件200之填充物231形成於凹部125而覆蓋凹部125內之全覆蓋屏蔽件132之部分。填充物231可部分地或完全地填入凹部125。
請參照第15A至15C圖,其繪示第5圖之半導體封裝件300的製造步驟圖。如第15A圖所示,在切割前,形成電性連接件331覆蓋半導體晶片120之上表面120u及封裝
體140之上表面140u,且填入凹部125。電性連接件331可採用例如是如上所述之第13D及13F圖的方法形成。導電材料331包括位於凹部125內的第一電性連接件3311,及覆蓋第一導電材料3311之上表面3311u及封裝體140之上表面140u的第二電性連接件3312。封裝體140可採用如上所述之第13B圖的方法形成。
如第15B圖所示,沿經過導電材料331、封裝體140、基板110及接地元件111的路徑P,切割封裝體的任一側面。露出接地元件111的切割方式可採用如上所述之第13F圖的方法形成。
如第15C圖所示,形成全覆蓋屏蔽件132覆蓋電性連接件331之上表面331u、封裝體140的上表面140u、接地元件111之露出之外側面111s及基板110之外表面110s。全覆蓋屏蔽件132可採用如上所述之第13F圖的方法形成。
請參照第16A至16B圖,其繪示第6圖之半導體封裝件400的製造步驟圖。如第16A圖所示,形成封裝體440以包覆半導體晶片120之側面120s、銲線150、銲墊113及121。封裝體440可採用如上所述之第13B圖的方法形成。封裝體440覆蓋部分基板110之上表面110u及晶片120的上表面120u,以避免銲線150、銲墊113、121與後續形成之導電層430電性接觸。本例中,封裝體140形成一環形(從上方看去)且定義凹部125。如第16B圖所示,形
成導電層430包覆晶片120及封裝體440。導電層430覆蓋部分基板110之上表面110u及晶片120的上表面120u,但未受到封裝體140覆蓋。導電層430可採用如上所述之第13F圖的方法形成。
請參照第17A至17B圖,其繪示第8圖之半導體封裝件600的製造步驟圖。如第17A圖所示,形成至少一圍牆660圍繞銲線150、銲墊121及113。圍牆660可採用例如是表面黏貼技術(SMT)、塗佈技術或任何其它方法形成。圍牆660界定出後續形成之封裝體440的範圍。如第17B圖所示,形成封裝體440填入圍牆660所界定的區域,且包覆銲線150、銲墊121及113。封裝體440避免銲線150、銲墊113、121與後續形成之導電層430(第8圖)的電性接觸。
請參照第18A至18C圖,其繪示第10圖之半導體封裝件800的製造步驟圖。如第18A圖所示,沿經過封裝體140的路徑P,切割封裝體的任一側面。切割方法可採用如上所述之第13F圖的方法形成。切割路徑P1形成後,封裝體140形成一第二外側面140s2,且部分之接地元件111從第二外側面140s2露出。本例中,接地元件111突出於基板110之上表面110u。因此,切割路徑P1可切割接地元件111而不用經過整個封裝體140。這樣的切割方法稱為”半穿切”。然而,另一例中,切割路徑P1可通經過整個
封裝體140。其它例子中,當接地元件111內埋於基板110時,切割路徑P1經過整個封裝體140及部分基板110,而露出設於基板110內的接地元件111。
如第18B圖所示,形成全覆蓋屏蔽件132覆蓋封裝體140之外表面、電性連接件131之上表面131u及接地元件111之露出的外側面111s。全覆蓋屏蔽件132連同電性連接件131形成導電層130。
如第18C圖所示,沿經過封裝體140及基板110的路徑P2,切割封裝體的任一側面。切割可採用如上所述之第13F圖的方法形成。切割後,封裝體140形成一第一外側面140s1,且基板110形成一外側面110s,其中第一外側面140s1與外側面110s實質上共面。由於切割路徑P1及P2分別形成,封裝體140之第一外側面140s1平行於第二外側面140s2,但與第二外側面140s2不共面。
本例中,數個如第1A圖之導電層130導電層提供將熱與電流遠離晶片120的接地路徑及熱傳導路徑。熱及電流從晶片120藉由設置於晶片120之上表面120u的電性連接件131導向全覆蓋屏蔽件132。熱量透過全覆蓋屏蔽件132往外散逸,而電流流向接地元件111。因此除了EMI屏蔽之外,全覆蓋屏蔽件132亦提供散熱及接地的功能。其它例子的傳導路徑稍微不同,例如,第4圖之例中,熱量及電流首先流經接觸晶片120之上表面120u的全覆蓋屏
蔽件232,然後流經凹部125內之填充物231。
綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100、200、300、400、500、600、700、800、900‧‧‧半導體封裝件
110‧‧‧基板
111‧‧‧接地元件
112‧‧‧導通孔
113、121‧‧‧銲墊
110u、131u、120u、140u、231u、331u、3311u‧‧‧上表面
110b‧‧‧下表面
110s、111s、140s、430s、440s‧‧‧外側面
110s1‧‧‧第一外側面
110s2‧‧‧第二外側面
120‧‧‧半導體晶片
125、725‧‧‧凹部
120s‧‧‧側面
113、121‧‧‧接墊
130、230、330、430‧‧‧導電層
131、331‧‧‧電性連接件
132、232‧‧‧全覆蓋屏蔽件
140、440‧‧‧封裝體
140s1‧‧‧第一外側面
140s2‧‧‧第二外側面
150‧‧‧銲線
160‧‧‧載板
231‧‧‧填充物
331‧‧‧導電材料
3311‧‧‧第一電性連接件
3312‧‧‧第二電性連接件
660‧‧‧圍牆
726‧‧‧子凹部
H1、H2、H3、H4‧‧‧厚度
P、P1、P2‧‧‧路徑
TR‧‧‧熱阻
第1A圖繪示數個實施例之一者的半導體封裝件的剖視圖。
第1B圖繪示第1A圖之俯視圖。
第2圖所示繪示依照本發明另一實施例之半導體封裝件之俯視圖。
第3圖繪示第1A圖之導電層130的屏蔽效果圖。
第4圖所示繪示依照本發明另一實施例之半導體封裝件的剖視圖。
第5圖繪示依照本發明另一實施例之半導體封裝件的剖視圖。
第6圖繪示依照本發明另一實施例之半導體封裝件的剖視圖。
第7圖繪示依照本發明另一實施例之半導體封裝件的剖視圖。
第8圖繪示依照本發明另一實施例之半導體封裝件的剖視圖。
第9A圖繪示依照本發明另一實施例之半導體封裝件的剖視圖。
第9B圖繪示第9A圖之半導體封裝件700的俯視圖。
第9C圖繪示第9A圖之半導體封裝件700之俯視圖。
第10圖繪示依照本發明另一實施例之半導體封裝件的剖視圖。
第11圖繪示依照本發明另一實施例之半導體封裝件的剖視圖。
第12A圖繪示第1圖之半導體封裝件100之熱阻(TR)的模擬數據圖。
第12B圖繪示第5圖之半導體封裝件300之TR的模擬數據圖。
第13A至13F圖繪示第1A圖之半導體封裝件100的製造步驟圖。
第14圖繪示第4圖之半導體封裝件200的製造步驟圖。
第15A至15C圖繪示第5圖之半導體封裝件300的製造步驟圖。
第16A至16B圖繪示第6圖之半導體封裝件400的製造步驟圖。
第17A至17B圖繪示第8圖之半導體封裝件600的製造步驟圖。
第18A至18C圖繪示第10圖之半導體封裝件的製造步驟圖。
100‧‧‧半導體封裝件
110‧‧‧基板
111‧‧‧接地元件
112‧‧‧導通孔
113、121‧‧‧銲墊
110u、120u、131u、140u‧‧‧上表面
110b‧‧‧下表面
110s、111s、140s‧‧‧外側面
120‧‧‧晶片
125‧‧‧凹部
120s‧‧‧側面
130‧‧‧導電層
131‧‧‧電性連接件
132‧‧‧全覆蓋屏蔽件
140‧‧‧封裝體
150‧‧‧銲線
H1、H2‧‧‧厚度
Claims (20)
- 一種半導體封裝件,包括:一基板,具有一接地元件;一半導體晶片,設於該基板上,且具有複數個銲墊;一封裝體,包覆該半導體晶片;一凹部,形成於該封裝體中並露出該半導體晶片之一上表面的至少一部分;一電性連接件,設於至少二該銲墊之間的該凹部內,其中該電性連接件超過該半導體晶片之一側邊;以及一導電層,設於該封裝體之一外表面上,其中該導電層直接接觸該電性連接件與該接地元件;其中,該電性連接件與該導電層的一組合提供半導體封裝件散熱及電磁干擾之屏蔽。
- 如申請專利範圍第1項所述之半導體封裝件,其中該電性連接件直接接觸該半導體晶片之該上表面。
- 如申請專利範圍第2項所述之半導體封裝件,其中一散熱路徑直接從該半導體晶片延伸至該電性連接件,且直接從該電性連接件至該導電層。
- 如申請專利範圍第1項所述之半導體封裝件,其中 該凹部係增加該封裝件對應於一最差電磁干擾(EMI)屏蔽效果的一共振頻率(resonant frequency),使該共振頻率超過該半導體晶片的一操作頻率。
- 如申請專利範圍第1項所述之半導體封裝件,其中該導電層直接接觸該半導體晶片之該上表面。
- 如申請專利範圍第1項所述之半導體封裝件,其中該凹部包括複數個子凹部,該些子凹部與該半導體晶片之該上表面隔離。
- 如申請專利範圍第1項所述之半導體封裝件,其中該接地元件未延伸經過該基板。
- 如申請專利範圍第2項所述之半導體封裝件,其中該接地元件包括具有一側壁的一部分導通孔(partial via),該側壁從該基板露出。
- 一種半導體封裝件,包括:一基板,具有一接地元件;一半導體晶片,設於該基板上,且具有複數個銲墊;一封裝體,包覆該半導體晶片; 一凹部,形成於該封裝體中且露出該半導體晶片之一上表面的至少一部分之;以及一元件,耦接至該半導體晶片之該上表面及該封裝體,且提供該半導體封裝件散熱及電磁干擾屏蔽的功能。
- 如申請專利範圍第9項所述之半導體封裝件,其中該元件包括一凹部、一電性連接件及一全覆蓋屏蔽件(conformal shield),該凹部形成於該封裝體且位於該半導體晶片上方,該電性連接件設於該凹部內,該全覆蓋屏蔽件位於該電性連接件上方。
- 如申請專利範圍第10項所述之半導體封裝件,其中一散熱路徑直接從該半導體晶片延伸至該電性連接件,且直接從該電性連接件至該導電層。
- 如申請專利範圍第10項所述之半導體封裝件,其中該凹部係增加該封裝件對應於一最差電磁干擾屏蔽效果的一共振頻率,使該共振頻率超過該半導體晶片的一操作頻率。
- 如申請專利範圍第9項所述之半導體封裝件,其中該元件包括一全覆蓋屏蔽件及一填充物(filler),該全覆 蓋屏蔽件覆蓋該封裝體之一外表面及從該凹部露出之該半導體晶片之該上表面,該填充物與該全覆蓋屏蔽件位於該凹部內,該全覆蓋屏蔽件設於該填充部與該半導體晶片之該上表面之間。
- 如申請專利範圍第13項所述之半導體封裝件,其中一熱路徑從該半導體晶片直接延伸至該電性連接件,且從該電性連接件直接延伸至該導電層。
- 如申請專利範圍第13項所述之半導體封裝件,其中該凹部係增加該封裝件對應於一最差電磁干擾屏蔽效果的一共振頻率,使該共振頻率超過該半導體晶片的一操作頻率。
- 如申請專利範圍第9項所述之半導體封裝件,其中該元件包括一電性連接件及一全覆蓋屏蔽件,該電性連接件覆蓋該半導體晶片之該上表面及該封裝體之一上表面,該全覆蓋屏蔽件覆蓋該電性連接件及該封裝體。
- 如申請專利範圍第9項所述之半導體封裝件,其中該接地元件包括具有一側壁的一部分導通孔,該側壁從該基板露出。
- 一種半導體封裝件之製造方法,包括:設置一半導體晶片於一基板,其中該半導體晶片具有一側面及一上表面,且該基板包括一接地元件;形成一封裝體包覆該半導體晶片之該側面,其中該封裝體定義一露出該半導體晶片之該上表面之凹部;切割該封裝體、該基板及該接地元件,以露出該接地元件之一側壁;以及形成一導電層覆蓋該封裝體之一外表面及從該凹部露出之該半導體晶片之該上表面,且接觸露出之該接地元件。
- 如申請專利範圍第18項所述之製造方法,其中形成該導電層之該步驟包括:形成一電性連接件覆蓋該半導體晶片之該上表面;以及形成一全覆蓋屏蔽件覆蓋該封裝體之該外表面及該電性連接件之一上表面,且接觸露出之該接地元件。
- 如申請專利範圍第18項所述之製造方法,其中形成該導電層之該步驟包括:形成一全覆蓋屏蔽件覆蓋該封裝體之該外表面及從 該凹部露出之該半導體晶片之該上表面,且接觸該接地元件;以及形成一填充部於該凹部內。
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Also Published As
Publication number | Publication date |
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CN103219298A (zh) | 2013-07-24 |
US8704341B2 (en) | 2014-04-22 |
CN106449556A (zh) | 2017-02-22 |
US20130307128A1 (en) | 2013-11-21 |
CN103219298B (zh) | 2016-12-28 |
CN106449556B (zh) | 2021-04-16 |
TW201347109A (zh) | 2013-11-16 |
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