JP5038885B2 - 高電圧pmosトランジスタの製造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000000034 method Methods 0.000 claims description 25
- 230000000873 masking effect Effects 0.000 claims description 17
- 238000002513 implantation Methods 0.000 claims description 16
- 150000002500 ions Chemical class 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims 2
- 239000000758 substrate Substances 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 230000005684 electric field Effects 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- -1 boron ions Chemical class 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
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Description
文献 R. Stengl および U. Goesele 著:"Variation of lateral Doping - A New Concept to Avoid High Voltage Sreakdown of Planar Junctions"(International Electron Devices Meeting, Technical Digest, 1. 〜 4. Dezember 1985, page 154 〜 157)(XP002013050)には、生成すべきウェルの中央領域と縁領域との間において部分的に付加的なカバー部が設けられている、p形導電ウェルを製造するためのマスキングが記載されている。
US6455893B1から、比較的僅かなスペースを必要とするラテラルな高電圧トランジスタが必要である。というのは、高ドーピングされたドレインにおいて発生する電界強度は僅かにドーピングされているドレイン拡張部およびフィールドプレートを用いて低減されるからである。このトランジスタは1μmより僅かなストラクチャ幅を有するCMOSプロセスに対しても使用可能である。しかしこの刊行物には、トランジスタの耐圧が制限されていることが述べられている。その理由は、ドレイン拡張部の縁領域における逆行する(retrograde)インプランテーションプロフィールにより、あまり適していないドーピングパターンが生じるからである。
第1図は本発明の高電圧PMOSトランジスタの断面を略示し、
第2図はnウェル、殊にトランジスタヘッドにnウェルを製造するためのマスクの一部を略示し、
第3図はpウェルを製造するためのマスキングの一部を略示し、
第4図は従来技術に依拠している高電圧PMOSトランジスタを略示している。
Claims (10)
- 高電圧PMOSトランジスタのn形導電ウェル(11)およびp形導電ウェル(12)を製造するための方法であって、
前記高電圧PMOSトランジスタは、n形導電ウェル(11)内のp形導電ソース領域(15)と、n形導電ウェル(11)内に配置されているp形導電ウェル(12)内のp形ドレイン領域(14)とを有しており、
ドレイン領域(14)の下方のn形導電ウェルの深さ(A′−B′)がソース領域(15)の下方のn形導電ウェルの深さより浅くなるように、かつp形導電ウェルの深さ(A′−C′)が、ドレイン領域(14)の下方において最大となるように、かつp形導電ウェル(12)がドレイン領域(14)においてトランジスタチャネル(K)に向かう外側領域よりも高くドーピングされるように、マスク(Mn,Mp)によるマスキングを用いてイオンのインプランテーションを行う方法において、
n形導電ウェルを形成するイオンのインプランテーションは、ドレイン領域の下方におけるn形導電ウェルの深度がソース領域の下方のn形導電ウェル領域における深度よりも浅くなるように行われ、
前記n形導電ウェルを形成するイオンのインプランテーションの際に用いるマスク(Mn)は、ドレイン領域を覆うドレインカバー部(21)を有しており、
前記ドレインカバー部(21)によってウェハのドレイン領域が形成される領域がカバーされ、かつ前記ドレインカバー部(21)から距離をおいて、ウェハのドレイン領域およびソース領域が形成される位置の間を覆う別のカバー部(22)を有していることを特徴とする方法。 - 前記別のカバー部(22)はストライプ形状に形成されている請求項1記載の方法。
- 前記ドレインカバー部(21)は、円弧状又は多角形状であるトランジスタヘッドの領域(TK)と矩形状である領域とからなり、前記ドレインカバー部における前記トランジスタヘッド(TK)の領域は矩形状領域よりも拡幅されている請求項1または2記載の方法。
- 前記ドレインカバー部(21)は前記トランジスタヘッド(TK)の領域が円弧状である請求項1から3までのいずれか1項記載の方法。
- 前記別のカバー部(22)は、前記トランジスタヘッドの領域において、前記トランジスタヘッドの領域に対して間隔をおいて前記ドレインカバー部の形状に沿って配置されている請求項3または4記載の方法。
- p形導電ウェルを形成するイオンのインプランテーションの際に用いるマスク(Mp)には、前記ドレインカバー部に対応する中央領域(Z)と生成すべきp形導電ウェルの縁領域との間において部分的に付加的なカバー部(24,25)が設けられており、該付加的なカバー部のうち前記ドレインカバーにおける矩形状領域と対向する部分(24)は、ソース領域からドレイン領域の方向に向かって拡幅されておりかつ相互に離間している複数の領域からなる請求項1から5のいずれか1項記載の方法。
- 前記付加的なカバー部のうち前記ドレインカバーにおける矩形状領域と対向する部分(24)はドレインカバー領域に対向する部分が下底となる台形が複数配置されている請求項6記載の方法。
- 前記付加的なカバー部のうち前記トランジスタヘッドの領域と対向する部分(25)は、相互に離間し前記トランジスタヘッドの領域の外形に沿って延在するストライプである請求項6または7記載の方法。
- 前記付加的なカバー部のうち前記トランジスタヘッドの領域と対向する部分(25)は、円弧状に延在している複数のストライプである請求項8記載の方法。
- 前記付加的なカバー部のうち前記トランジスタヘッドの領域と対向する部分(25)は、少なくとも部分的に平行に延在している請求項9記載の方法。
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Application Number | Priority Date | Filing Date | Title |
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DE102004009521.3A DE102004009521B4 (de) | 2004-02-27 | 2004-02-27 | Hochvolt-PMOS-Transistor, Maske zur Herstellung einer Wanne und Verfahren zur Herstellung eines Hochvolt-PMOS-Transistors |
DE102004009521.3 | 2004-02-27 | ||
PCT/EP2005/002112 WO2005083794A2 (de) | 2004-02-27 | 2005-02-28 | Hochvolt-pmos-transistor |
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JP2007535139A JP2007535139A (ja) | 2007-11-29 |
JP2007535139A5 JP2007535139A5 (ja) | 2010-10-28 |
JP5038885B2 true JP5038885B2 (ja) | 2012-10-03 |
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US (1) | US7663203B2 (ja) |
EP (1) | EP1719184B1 (ja) |
JP (1) | JP5038885B2 (ja) |
KR (1) | KR100826714B1 (ja) |
CN (1) | CN101124680B (ja) |
DE (1) | DE102004009521B4 (ja) |
WO (1) | WO2005083794A2 (ja) |
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Publication number | Priority date | Publication date | Assignee | Title |
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EP1852916A1 (en) | 2006-05-05 | 2007-11-07 | Austriamicrosystems AG | High voltage transistor |
US8497167B1 (en) * | 2007-01-17 | 2013-07-30 | National Semiconductor Corporation | EDS protection diode with pwell-nwell resurf |
US20090111252A1 (en) * | 2007-10-30 | 2009-04-30 | United Microelectronics Corp. | Method for forming deep well region of high voltage device |
DE102009053065A1 (de) | 2009-11-13 | 2011-05-19 | Austriamicrosystems Ag | Hochvolttransistor, ESD-Schutzschaltung und Verwendung eines Hochvolttransistors in einer ESD-Schutzschaltung |
EP2402998B1 (en) * | 2010-07-01 | 2020-04-08 | ams AG | Method of producing a p-channel LDMOS transistor |
US9077365B2 (en) | 2010-10-15 | 2015-07-07 | S.C. Johnson & Son, Inc. | Application specific integrated circuit including a motion detection system |
DE102011009487B4 (de) | 2011-01-26 | 2017-10-19 | Austriamicrosystems Ag | Asymmetrischer Hochvolt-JFET und Herstellungsverfahren |
DE102011056412B4 (de) * | 2011-12-14 | 2013-10-31 | Austriamicrosystems Ag | Hochvolttransistorbauelement und Herstellungsverfahren |
CN103280460B (zh) | 2013-05-22 | 2016-09-07 | 矽力杰半导体技术(杭州)有限公司 | 注入形成具有叠加漂移区的高压pmos晶体管及其制造方法 |
EP2876686B1 (en) * | 2013-11-22 | 2019-03-20 | ams AG | High-voltage semiconductor device and method of producing the same |
DE102014009980B4 (de) | 2014-07-03 | 2019-03-21 | Elmos Semiconductor Aktiengesellschaft | MOS-Transistor mit hoher Ausgangsspannungsfestigkeit und niedrigem Ein-Widerstand (Ron) |
KR102313728B1 (ko) * | 2018-04-09 | 2021-10-15 | 주식회사 키 파운드리 | 접합 트랜지스터와 고전압 트랜지스터를 포함한 반도체 소자 |
CN106601819B (zh) * | 2017-01-04 | 2019-06-11 | 上海华虹宏力半导体制造有限公司 | Pldmos器件及其制造方法 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02172220A (ja) * | 1988-12-26 | 1990-07-03 | Hitachi Ltd | イオン打込み方法 |
JP3206026B2 (ja) * | 1991-07-19 | 2001-09-04 | 富士電機株式会社 | 高電圧用misfetを備える半導体装置 |
EP0537684B1 (en) * | 1991-10-15 | 1998-05-20 | Texas Instruments Incorporated | Improved performance lateral double-diffused MOS transistor and method of fabrication thereof |
JPH05172220A (ja) | 1991-12-18 | 1993-07-09 | Daihatsu Motor Co Ltd | 変速機のリバースアイドラギヤ潤滑構造 |
JPH05304169A (ja) * | 1992-04-28 | 1993-11-16 | Nec Corp | 半導体装置の製造方法 |
JP2997377B2 (ja) * | 1993-01-06 | 2000-01-11 | シャープ株式会社 | 半導体装置及びその製造方法 |
JPH0730107A (ja) * | 1993-07-13 | 1995-01-31 | Sony Corp | 高耐圧トランジスタ及びその製造方法 |
US5512495A (en) * | 1994-04-08 | 1996-04-30 | Texas Instruments Incorporated | Method of manufacturing extended drain resurf lateral DMOS devices |
DE19536753C1 (de) * | 1995-10-02 | 1997-02-20 | El Mos Elektronik In Mos Techn | MOS-Transistor mit hoher Ausgangsspannungsfestigkeit |
GB2309336B (en) * | 1996-01-22 | 2001-05-23 | Fuji Electric Co Ltd | Semiconductor device |
JP3185656B2 (ja) * | 1996-03-22 | 2001-07-11 | 富士電機株式会社 | 横型電界効果トランジスタおよびその製造方法 |
JP3061023B2 (ja) * | 1997-11-28 | 2000-07-10 | 日本電気株式会社 | 半導体装置 |
JPH11297996A (ja) * | 1998-04-08 | 1999-10-29 | Sony Corp | 半導体装置およびその製造方法 |
US6455893B1 (en) | 1998-06-26 | 2002-09-24 | Elmos Semiconductor Ag | MOS transistor with high voltage sustaining capability and low on-state resistance |
US6111291A (en) * | 1998-06-26 | 2000-08-29 | Elmos Semiconductor Ag | MOS transistor with high voltage sustaining capability |
KR100300069B1 (ko) * | 1999-05-10 | 2001-09-26 | 김영환 | 반도체 소자 및 그 제조방법 |
SE519382C2 (sv) * | 2000-11-03 | 2003-02-25 | Ericsson Telefon Ab L M | Integrering av självinriktade MOS-högspänningskomponenter samt halvledarstruktur innefattande sådana |
GB2374456A (en) * | 2000-12-09 | 2002-10-16 | Esm Ltd | High-voltage metal oxide semiconductor device and method of forming the device |
US6468870B1 (en) * | 2000-12-26 | 2002-10-22 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a LDMOS transistor |
US6448625B1 (en) * | 2001-03-16 | 2002-09-10 | Semiconductor Components Industries Llc | High voltage metal oxide device with enhanced well region |
JP2002353444A (ja) * | 2001-05-28 | 2002-12-06 | Fuji Electric Co Ltd | 半導体装置 |
JPWO2003092078A1 (ja) * | 2002-04-25 | 2005-09-02 | サンケン電気株式会社 | 半導体素子及びその製造方法 |
DE10345347A1 (de) * | 2003-09-19 | 2005-04-14 | Atmel Germany Gmbh | Verfahren zur Herstellung eines DMOS-Transistors mit lateralem Driftregionen-Dotierstoffprofil |
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2004
- 2004-02-27 DE DE102004009521.3A patent/DE102004009521B4/de not_active Expired - Lifetime
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2005
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- 2005-02-28 KR KR1020067017130A patent/KR100826714B1/ko active IP Right Grant
- 2005-02-28 US US10/591,001 patent/US7663203B2/en active Active
- 2005-02-28 WO PCT/EP2005/002112 patent/WO2005083794A2/de active Application Filing
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Also Published As
Publication number | Publication date |
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CN101124680B (zh) | 2010-06-16 |
US7663203B2 (en) | 2010-02-16 |
DE102004009521A1 (de) | 2005-09-15 |
EP1719184B1 (de) | 2018-08-29 |
EP1719184A2 (de) | 2006-11-08 |
US20070278573A1 (en) | 2007-12-06 |
DE102004009521B4 (de) | 2020-06-10 |
WO2005083794A3 (de) | 2005-12-15 |
WO2005083794A2 (de) | 2005-09-09 |
CN101124680A (zh) | 2008-02-13 |
KR100826714B1 (ko) | 2008-04-30 |
KR20060121983A (ko) | 2006-11-29 |
JP2007535139A (ja) | 2007-11-29 |
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