JP4881620B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP4881620B2 JP4881620B2 JP2006001027A JP2006001027A JP4881620B2 JP 4881620 B2 JP4881620 B2 JP 4881620B2 JP 2006001027 A JP2006001027 A JP 2006001027A JP 2006001027 A JP2006001027 A JP 2006001027A JP 4881620 B2 JP4881620 B2 JP 4881620B2
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- semiconductor chip
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- wire
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Description
図1は本発明の実施の形態1の半導体装置の構造の一例を封止体を透過して示す平面図、図2は図1に示す半導体装置の構造の一例を示す断面図、図3は図2に示すA部の構造を示す拡大部分断面図、図4は図3に示すワイヤ接合部の構造の一例を示す拡大部分断面図、図5〜図8は図4に示すワイヤリング時のキャピラリの移動軌跡の一例を示す断面図である。また、図9は図1に示す半導体装置に組み込まれる配線基板の主面側の配線パターンの一例を示す平面図、図10は図9に示す配線基板の裏面側の配線パターンの一例を示す裏面図、図11は図9に示す配線基板の構造の一例を示す断面図、図12は図11に示すA部の構造を示す拡大部分断面図である。さらに、図13は図1に示す半導体装置の組み立てにおける樹脂モールドまでの組み立ての一例を示す製造プロセスフロー図、図14は図1に示す半導体装置の組み立てにおける樹脂モールド後の組み立ての一例を示す製造プロセスフロー図、図15は図1に示す半導体装置の組み立てにおける樹脂モールド後の組み立ての変形例を示す製造プロセスフロー図である。
図23は本発明の実施の形態2の半導体装置の構造の一例を封止体を透過して示す平面図、図24は図23に示す半導体装置の構造の一例を示す断面図、図25は図24に示すA部の構造を示す拡大部分断面図、図26は図24に示すB部の構造を示す拡大部分断面図である。
1a 主面
1b 裏面
1c パッド(電極)
2 ダイボンド用フィルム
3 パッケージ基板(配線基板)
3a 主面
3b 裏面
3c コア材
3d ランド
3e スルーホール
3f ソルダレジスト膜
3g 銅配線
3h ボンディングリード(端子)
3i 開口部
3j 給電線
4 ワイヤ
4a ワイヤ接続部
4b ループの頂点
5 一括封止体
6 封止体
7 CSP(半導体装置)
8 半田バンプ(外部端子)
9 多数個取り基板
10 マーキング
11 ダイシングブレード
12 ダイシングテープ
13 中心線
14 CSP(半導体装置)
15 第2ワイヤ(他のワイヤ)
15a ワイヤ接続部
15b ループの頂点
16 第3ワイヤ
17 第2の半導体チップ(他の半導体チップ)
17a 主面
17b 裏面
17c パッド(電極)
18 キャピラリ
19 金バンプ
20 樹脂成形金型
20a キャビティ
30 小型パッケージ
Claims (11)
- 平面形状が矩形状から成る上面、前記上面とは反対側の下面、及び前記上面の上面辺に沿うように、前記上面に配置された複数の端子を有する配線基板と、
平面形状が矩形状から成る第1主面、前記第1主面とは反対側の第1裏面、及び前記第1主面の第1主面辺に沿うように、前記第1主面に配置された複数の第1パッドを有し、前記複数の端子から成る端子列よりも前記配線基板の内側に位置し、かつ前記第1裏面が前記配線基板の前記上面と対向するように、前記配線基板の前記上面に搭載された第1半導体チップと、
前記第1半導体チップの前記複数の第1パッドと前記配線基板の前記複数の端子とをそれぞれ電気的に接続する複数の第1ワイヤと、
前記第1半導体チップの前記第1主面側に位置する表面を有し、前記第1半導体チップ及び前記複数の第1ワイヤを封止する封止体と、
前記配線基板の前記下面に設けられた複数の外部接続用端子と、
を含み、
前記複数の第1ワイヤのそれぞれは、前記配線基板の前記複数の端子のそれぞれと接続される第1ワイヤ接続部を有し、
前記複数の第1ワイヤのそれぞれの一部は、前記第1ワイヤ接続部より前記配線基板の前記上面における前記上面辺側に配置されており、
前記複数の第1ワイヤのそれぞれは、前記配線基板の前記端子から前記第1半導体チップの前記第1パッドに向かってループ状に形成され、
前記ループ状に形成された第1ワイヤは、断面視において、前記第1半導体チップの前記第1主面より前記封止体の前記表面側に位置する頂点部を有し、
前記頂点部は、前記第1ワイヤ接続部より前記配線基板の前記上面における前記上面辺側に配置されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記配線基板の前記上面には、前記複数の端子のそれぞれと繋がる配線が形成されており、
前記配線は、前記端子から前記配線基板の内側に向かって形成されており、
前記配線基板の前記上面には、前記配線を覆うように、ソルダレジスト膜が形成されており、
前記ソルダレジスト膜は、前記端子と前記配線基板の前記上面における前記上面辺との間には形成されていないことを特徴とする半導体装置。 - 請求項2記載の半導体装置において、
前記配線基板の前記上面には、前記複数の端子のそれぞれと繋がる給電線が形成されており、
前記給電線は、前記端子から前記配線基板の前記上面における前記上面辺に向かって形成されており、
前記給電線は、前記ソルダレジスト膜から露出していることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1半導体チップの前記第1主面上には、平面形状が矩形状から成る第2主面、前記第2主面とは反対側の第2裏面、及び前記第2主面の第2主面辺に沿うように、前記第2主面に配置された複数の第2パッドを有する第2半導体チップが、前記第1半導体チップの前記複数の第1パッドから成るパッド列よりも前記第1半導体チップの内側に位置し、前記第2裏面が前記第1半導体チップの前記第1主面と対向するように、前記第1半導体チップの前記第1主面に積層されており、
前記第2半導体チップの前記複数の第2パッドは、複数の第2ワイヤを介して前記配線基板の前記複数の端子とそれぞれ電気的に接続されており、
前記複数の第1ワイヤのそれぞれの一部は、前記複数の第2ワイヤのそれぞれより前記配線基板の前記上面における前記上面辺側に配置されていることを特徴とする半導体装置。 - 請求項4記載の半導体装置において、
前記第2半導体チップの前記複数の第2パッドは、複数の第3ワイヤを介して前記第1半導体チップの前記複数の第1パッドとそれぞれ電気的に接続されており、
前記複数の第3ワイヤのそれぞれは、前記第1半導体チップの前記複数の第1パッドとそれぞれ接続される第3ワイヤ接続部を有し、
前記複数の第3ワイヤのそれぞれの一部は、前記第3ワイヤ接続部より前記配線基板の前記上面における前記上面辺側に配置されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1半導体チップの前記複数の第1パッドのそれぞれには、バンプが形成されており、
前記複数の第1ワイヤのそれぞれは、前記バンプを介して、前記第1半導体チップの前記第1パッドと電気的に接続されていることを特徴とする半導体装置。 - 以下の工程を含むことを特徴とする半導体装置の製造方法:
(a)平面形状が矩形状から成る上面、前記上面とは反対側の下面、及び前記上面の上面辺に沿うように、前記上面に配置された複数の端子を有する配線基板を準備する工程;
(b)平面形状が矩形状から成る第1主面、前記第1主面とは反対側の第1裏面、及び前記第1主面の第1主面辺に沿うように、前記第1主面に配置された複数の第1パッドを有する第1半導体チップを、前記複数の端子から成る端子列よりも前記配線基板の内側に位置し、かつ前記第1裏面が前記配線基板の前記上面と対向するように、前記配線基板の前記上面に搭載する工程;
(c)前記第1半導体チップの前記複数の第1パッドと前記配線基板の前記複数の端子とを、複数の第1ワイヤを介してそれぞれ電気的に接続する工程;
(d)前記第1半導体チップ及び前記複数の第1ワイヤを樹脂で封止することで、前記第1半導体チップの前記第1主面側に位置する表面を有する封止体を形成する工程;
(e)前記配線基板の前記下面に複数の外部接続用端子を設ける工程;
ここで、
前記複数の第1ワイヤのそれぞれは、前記第1ワイヤの第1部分を前記配線基板の前記端子と接続してから、前記第1ワイヤの前記第1部分とは異なる第2部分を前記第1半導体チップの前記第1パッドと接続することで、形成され、
前記複数の第1ワイヤのそれぞれは、前記複数の第1ワイヤのそれぞれの一部が、前記第1ワイヤの前記第1部分より前記配線基板の前記上面における前記上面辺側に位置するように、形成され、
前記複数の第1ワイヤのそれぞれは、断面視において、前記第1半導体チップの前記第1主面より前記封止体の前記表面側に位置する頂点部を有するように、前記配線基板の前記端子から前記第1半導体チップの前記第1パッドに向かってループ状に形成され、
前記複数の第1ワイヤのそれぞれは、前記頂点部が、前記第1ワイヤの前記第1部分より前記配線基板の前記上面における前記上面辺側に位置するように、形成されることを特徴とする半導体装置の製造方法。 - 平面形状が矩形状から成る第1主面、前記第1主面とは反対側の第1裏面、及び前記第1主面の第1主面辺に沿うように、前記第1主面に配置された複数の第1パッドを有する第1半導体チップと、
平面形状が矩形状から成る第2主面、前記第2主面とは反対側の第2裏面、及び前記第2主面の第2主面辺に沿うように、前記第2主面に配置された複数の第2パッドを有し、前記複数の第1パッドから成る端子列よりも前記第1半導体チップの内側に位置し、かつ前記第2裏面が前記第1半導体チップの前記第1主面と対向するように、前記第1半導体チップの前記第1主面に積層された第2半導体チップと、
前記第2半導体チップの前記複数の第2パッドと前記第1半導体チップの前記複数の第1パッドとをそれぞれ電気的に接続する複数の第1ワイヤと、
前記第2半導体チップの前記第2主面側に位置する表面を有し、前記第1半導体チップ、前記第2半導体チップ及び前記複数の第1ワイヤを封止する封止体と、
を含み、
前記複数の第1ワイヤのそれぞれは、前記第1半導体チップの前記複数の第1パッドのそれぞれと接続される第1ワイヤ接続部を有し、
前記複数の第1ワイヤのそれぞれの一部は、前記第1ワイヤ接続部より前記第1半導体チップの前記第1主面における前記第1主面辺側に配置されており、
前記複数の第1ワイヤのそれぞれは、前記第1半導体チップの前記第1パッドから前記第2半導体チップの前記第2パッドに向かってループ状に形成され、
前記ループ状に形成された第1ワイヤは、断面視において、前記第2半導体チップの前記第2主面より前記封止体の前記表面側に位置する頂点部を有し、
前記頂点部は、前記第1ワイヤ接続部より前記第1半導体チップの前記第1主面における前記第1主面辺側に配置されていることを特徴とする半導体装置。 - 請求項8記載の半導体装置において、
前記第1半導体チップは、前記第1半導体チップの前記第1裏面が、平面形状が矩形状から成る上面、前記上面とは反対側の下面、及び前記上面の上面辺に沿うように、前記上面に配置された複数の端子を有する配線基板の前記上面と対向し、かつ前記複数の端子から成る端子列よりも前記配線基板の内側に位置するように、前記配線基板の前記上面に搭載されており、
前記第2半導体チップの前記複数の第2パッドは、前記複数の第1ワイヤを介して前記第1半導体チップの前記複数の第1パッドと、複数の第2ワイヤを介して前記配線基板の前記複数の端子と、それぞれ電気的に接続されており、
前記複数の第2ワイヤのそれぞれは、前記配線基板の前記複数の端子のそれぞれと接続される第2ワイヤ接続部を有し、
前記複数の第2ワイヤのそれぞれは、前記第2ワイヤ接続部より前記配線基板の前記上面における前記上面辺側に配置される部分を有していないことを特徴とする半導体装置。 - 以下の工程を含むことを特徴とする半導体装置の製造方法:
(a)平面形状が矩形状から成る第1主面、前記第1主面とは反対側の第1裏面、及び前記第1主面の第1主面辺に沿うように、前記第1主面に配置された複数の第1パッドを有する第1半導体チップを準備する工程;
(b)平面形状が矩形状から成る第2主面、前記第2主面とは反対側の第2裏面、及び前記第2主面の第2主面辺に沿うように、前記第2主面に配置された複数の第2パッドを有する第2半導体チップを、前記複数の第1パッドから成る端子列よりも前記第1半導体チップの内側に位置し、かつ前記第2裏面が前記第1半導体チップの前記第1主面と対向するように、前記第1半導体チップの前記第1主面に積層する工程;
(c)前記第2半導体チップの前記複数の第2パッドと前記第1半導体チップの前記複数の第1パッドとを、複数の第1ワイヤを介してそれぞれ電気的に接続する工程;
(d)前記第1半導体チップ、前記第2半導体チップ及び前記複数の第1ワイヤを樹脂で封止することで、前記第2半導体チップの前記第2主面側に位置する表面を有する封止体を形成する工程;
ここで、
前記複数の第1ワイヤのそれぞれは、前記第1ワイヤの第1部分を前記第1半導体チップの前記第1パッドと接続してから、前記第1ワイヤの前記第1部分とは異なる第2部分を前記第2半導体チップの前記第2パッドと接続することで、形成され、
前記複数の第1ワイヤのそれぞれは、前記複数の第1ワイヤのそれぞれの一部が、前記第1ワイヤの前記第1部分より前記第1半導体チップの前記第1主面における前記第1主面辺側に位置するように、形成され、
前記複数の第1ワイヤのそれぞれは、断面視において前記第2半導体チップの前記第2主面より前記封止体の前記表面側に位置する頂点部を有するように、前記第1半導体チップの前記第1パッドから前記第2半導体チップの前記第2パッドに向かってループ状に形成され、
前記複数の第1ワイヤのそれぞれは、前記頂点部が、前記第1ワイヤの前記第1部分より前記第1半導体チップの前記第1主面における前記第1主面辺側に位置するように、形成されることを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記第1半導体チップは、前記第1半導体チップの前記第1裏面が、平面形状が矩形状から成る上面、前記上面とは反対側の下面、及び前記上面の上面辺に沿うように、前記上面に配置された複数の端子を有する配線基板の前記上面と対向し、かつ前記複数の端子から成る端子列よりも前記配線基板の内側に位置するように、前記配線基板の前記上面に搭載されており、
前記工程(b)の後、かつ前記工程(d)の前に、前記第2半導体チップの前記複数の第2パッドと前記配線基板の前記複数の端子とを、複数の第2ワイヤを介してそれぞれ電気的に接続し、
さらに、前記第2半導体チップと前記配線基板とを電気的に接続する工程では、前記複数の第2ワイヤのそれぞれが、前記第2ワイヤのうちの前記配線基板の前記端子と接続される部分より前記配線基板の前記上面における前記上面辺側に配置される部分を有さないように、行うことを特徴とする半導体装置の製造方法。
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US11/606,027 US7889513B2 (en) | 2006-01-06 | 2006-11-30 | Semiconductor device |
TW095144886A TWI404148B (zh) | 2006-01-06 | 2006-12-04 | Semiconductor device and manufacturing method thereof |
TW102125650A TWI531016B (zh) | 2006-01-06 | 2006-12-04 | Semiconductor device and manufacturing method thereof |
TW105106184A TWI598971B (zh) | 2006-01-06 | 2006-12-04 | Semiconductor device |
CNA2006101562406A CN1996584A (zh) | 2006-01-06 | 2006-12-27 | 半导体器件及其制造方法 |
KR1020070001430A KR101286874B1 (ko) | 2006-01-06 | 2007-01-05 | 반도체 장치 및 그 제조 방법 |
US12/985,815 US20110159644A1 (en) | 2006-01-06 | 2011-01-06 | Semiconductor device and a method of manufacturing the same |
US14/820,282 US9991229B2 (en) | 2006-01-06 | 2015-08-06 | Semiconductor device |
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US20180277522A1 (en) | 2018-09-27 |
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US7889513B2 (en) | 2011-02-15 |
KR20070074489A (ko) | 2007-07-12 |
US20110159644A1 (en) | 2011-06-30 |
US10515934B2 (en) | 2019-12-24 |
TW201347061A (zh) | 2013-11-16 |
TWI404148B (zh) | 2013-08-01 |
TWI598971B (zh) | 2017-09-11 |
KR101286874B1 (ko) | 2013-07-16 |
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US20150348944A1 (en) | 2015-12-03 |
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