JP4846272B2 - 半導体集積回路装置 - Google Patents
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Description
本発明の半導体集積回路装置に関する実施の形態1について、図1〜図5を用いて説明する。
本発明の半導体集積回路装置に関する実施の形態2について、図6,図7を用いて説明する。
本発明の半導体集積回路装置に関する実施の形態3について、図8,図9を用いて説明する。
本発明の半導体集積回路装置に関する実施の形態4について、図10,図11を用いて説明する。
本発明の半導体集積回路装置に関する実施の形態5について、図12を用いて説明する。
本発明の半導体集積回路装置に関する実施の形態6について、図13を用いて説明する。
本発明の半導体集積回路装置に関する実施の形態7について、図14,図15を用いて説明する。
本発明の半導体集積回路装置に関する実施の形態8について、図16を用いて説明する。
本発明の半導体集積回路装置に関する実施の形態9について、図17を用いて説明する。
本発明の半導体集積回路装置に関する実施の形態10について、図18を用いて説明する。
本発明の半導体集積回路装置に関する実施の形態11について、図19〜図22を用いて説明する。
本発明の半導体集積回路装置に関する実施の形態12について、図23〜図25を用いて説明する。
本発明の半導体集積回路装置に関する実施の形態13について、図26を用いて説明する。
本発明の半導体集積回路装置に関する実施の形態14について、図27を用いて説明する。
本発明の半導体集積回路装置に関する実施の形態15について、図28を用いて説明する。
Claims (14)
- 第1の電源と、それぞれ前記第1の電源および他の機能ブロックで使用される電源とは異なる第2乃至第M+1の電源とで動作する第1乃至第Mの機能ブロックを備え、前記第1乃至第Mの機能ブロックがひとつのチップ上に集積された半導体集積回路装置であって、
前記第2乃至第M+1の電源は、互いに独立して電源が供給され、
前記第1乃至第Mの機能ブロックは、それぞれ独立して電源遮断の制御が可能で、それぞれ電源遮断の優先度が付与され、前記優先度は信号結線の関係をもとに関係付けられ、前記信号結線は階層化されて実施され、
前記第1乃至第Mの機能ブロックのうち、下位の階層にある第Jおよび第Kの機能ブロックと、前記第Jおよび第Kの機能ブロックの上位の階層にある第Lの機能ブロックとの間において、前記第Jの機能ブロックから前記第Kの機能ブロックへの信号の授受を実施する際には前記第Lの機能ブロックの内部に設けられた信号中継用のバッファ回路を経由して伝達され、前記第Jの機能ブロックから前記第Lの機能ブロックへ信号を伝達する際には不定信号伝播防止回路を経由し、前記第Lの機能ブロックから前記第Kの機能ブロックへ信号を伝達する際には不定信号伝播防止回路を不要とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記下位の階層の機能ブロックが形成された第1の領域の内部には、前記上位の階層の機能ブロックが形成され、
前記上位の階層の機能ブロックのレイアウトは、基本的な回路セルの電源配線である、最下層の電源配線とは直角の方向に複数の回路セルが設けられるようにレイアウトされ、
前記上位の階層の機能ブロックの電源は、前記下位の階層の機能ブロックの電源と同様に、電源電圧のドロップが最小限となるようにチップ内部でメッシュ状に配線される半導体集積回路装置。 - 請求項2記載の半導体集積回路装置において、
前記下位の階層の複数の機能ブロックの内部に設置された前記上位の階層の機能ブロックの電源を共通化してまとめてひとつの機能ブロックとして扱う半導体集積回路装置。 - 請求項2または3記載の半導体集積回路装置において、
前記上位の階層の機能ブロックの電源遮断の優先度は、前記下位の階層の機能ブロックよりも低い半導体集積回路装置。 - 請求項4記載の半導体集積回路装置において、
前記上位の階層の機能ブロックの内部には、長距離信号の配線における中継バッファ回路が搭載される半導体集積回路装置。 - 請求項4記載の半導体集積回路装置において、
前記上位の階層の機能ブロックの内部には、クロック信号分配用のクロックバッファ回路が搭載される半導体集積回路装置。 - 請求項6記載の半導体集積回路装置において、
前記上位の階層の機能ブロックの内部には、前記クロック信号分配用のクロックバッファ回路のうち、クロック発生器に近い階層のクロックバッファ回路のみが搭載される半導体集積回路装置。 - 請求項4記載の半導体集積回路装置において、
前記上位の階層の機能ブロックには、前記下位の階層の機能ブロックが電源遮断される際の情報をバックアップするためのラッチ回路が搭載される半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記上位の階層の機能ブロックは、信号増幅回路を含む半導体集積回路装置。 - 請求項1または9記載の半導体集積回路装置において、
前記上位の階層の機能ブロックは、クロック信号分配用のクロックバッファ回路を含む半導体集積回路装置。 - 請求項1、9または10の何れか1項記載の半導体集積回路装置において、
前記上位の階層の機能ブロックは、前記下位の階層の機能ブロックが保持する情報を保持するラッチ回路を有し、
前記ラッチ回路は、前記下位の階層の機能ブロックの電源遮断時に保持する情報を格納する半導体集積回路装置。 - 請求項1、9、10または11の何れか1項記載の半導体集積回路装置において、
前記上位の階層の機能ブロックの電源遮断の優先度は、前記下位の階層の機能ブロックよりも低い半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記下位の階層の機能ブロックは、フリップフロップ回路を有し、
前記上位の階層の機能ブロックは、前記下位の階層の機能ブロックの前記フリップフロップ回路が保持する情報を、前記下位の階層の機能ブロックの電源遮断時に格納するためのラッチ回路を有する半導体集積回路装置。 - 請求項13記載の半導体集積回路装置において、
前記ラッチ回路は、前記下位の階層の機能ブロックが電源遮断から復帰する時、前記ラッチ回路が保持する情報を前記下位の階層の機能ブロックのフリップフロップ回路へ出力される半導体集積回路装置。
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US12/566,323 US8026570B2 (en) | 2005-06-07 | 2009-09-24 | Semiconductor integrated circuit device having power switch controller with gate insulator thickness for controlling multiple power switches |
US13/225,401 US8169036B2 (en) | 2005-06-07 | 2011-09-02 | Semiconductor integrated circuit device |
US13/438,347 US8441095B2 (en) | 2005-06-07 | 2012-04-03 | Semiconductor device having a ring oscillator and MISFET for converting voltage fluctuation to frequency fluctuation |
US13/865,662 US8683414B2 (en) | 2005-06-07 | 2013-04-18 | Semiconductor integrated circuit device with independent power domains |
US14/187,030 US9087818B2 (en) | 2005-06-07 | 2014-02-21 | Semiconductor integrated circuit device with independent power domains |
US14/746,920 US9455699B2 (en) | 2005-06-07 | 2015-06-23 | Semiconductor integrated circuit device |
US15/246,796 US10014320B2 (en) | 2005-06-07 | 2016-08-25 | Semiconductor integrated circuit device |
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US20130228939A1 (en) | 2013-09-05 |
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