JP4745108B2 - 不揮発性半導体記憶装置 - Google Patents
不揮発性半導体記憶装置 Download PDFInfo
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- JP4745108B2 JP4745108B2 JP2006105739A JP2006105739A JP4745108B2 JP 4745108 B2 JP4745108 B2 JP 4745108B2 JP 2006105739 A JP2006105739 A JP 2006105739A JP 2006105739 A JP2006105739 A JP 2006105739A JP 4745108 B2 JP4745108 B2 JP 4745108B2
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- 239000004065 semiconductor Substances 0.000 title claims description 58
- 230000015654 memory Effects 0.000 claims description 136
- 239000003990 capacitor Substances 0.000 claims description 124
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 38
- 229910052710 silicon Inorganic materials 0.000 claims description 38
- 239000010703 silicon Substances 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 30
- 239000004020 conductor Substances 0.000 claims description 15
- 210000004027 cell Anatomy 0.000 description 377
- 239000010410 layer Substances 0.000 description 33
- 238000009792 diffusion process Methods 0.000 description 32
- 238000000034 method Methods 0.000 description 27
- 230000015572 biosynthetic process Effects 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 7
- 230000000295 complement effect Effects 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 5
- 230000001771 impaired effect Effects 0.000 description 4
- 238000010030 laminating Methods 0.000 description 4
- 230000010287 polarization Effects 0.000 description 4
- 101100535994 Caenorhabditis elegans tars-1 gene Proteins 0.000 description 3
- 210000002777 columnar cell Anatomy 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
Description
図4に示したように、ワード線方向(図4では、紙面左右方向。)に繰り返し配置されるセルブロック13は絶縁材料で分離されており、さらに、底部のシリコン基板11は少なくとも拡散層領域16が分離できる程度の深さまで溝で分離されている。
図5に示したように、ワード線方向(図5では、紙面左右方向。)に繰り返し配置された各セルブロック13で、WL0〜WL15およびPS、/PSは共用されている。また、各セルブロック13においてPSおよび/PSが構成する2つのトランジスタのうち1つはDTとして形成されている。
まず、待機時には、WL0〜WL15を“H”にしてセルトランジスタ20を全てON状態にし、/BSおよびBSを“L”にしてブロック選択トランジスタ14を全てOFF状態にし、/PSおよびPSを“H”にしてプレート選択トランジスタ15を全てON状態にする。
まず、待機時には、WL0〜WL15を“H”にしてセルトランジスタ20を全てON状態にし、/BSおよびBSを“L”にしてブロック選択トランジスタ34を全てOFF状態にする。
まず、待機時には、実施例3と同様に、WL0〜WL15を“H”にして、/BSおよびBSを“L”にする。これにより、全ての強誘電体キャパシタ26は、分極が安定に保持される。また、待機時には、Eql0およびEql1を“H”にして、BL0、/BL0、BL1、および/BL1を“L”にプリチャージする。
12 シリコン柱(Si柱)
13 セルブロック
14 ブロック選択トランジスタ
15 プレート選択トランジスタ
16 拡散層領域
19 メモリセル
20 セルトランジスタ
21 強誘電体膜
22 キャパシタ電極
23 セルキャパシタブロック
24 セルコンタクト
26 強誘電体キャパシタ
BL、/BL ビット線
PL、/PL プレート線
Claims (4)
- 導電性材料からなる電極の間に強誘電体膜を設けてなる強誘電体キャパシタと、
シリコン基板の主面に対して垂直方向に前記強誘電体キャパシタの前記電極および前記強誘電体膜が複数積層されてなるセルキャパシタブロックと、
ドレイン電極およびソース電極に前記強誘電体キャパシタが電気的に並列接続されたセルトランジスタと、
前記強誘電体キャパシタおよび前記セルトランジスタからなるメモリセルと、
複数の前記メモリセルが、前記ドレイン電極およびソース電極を端子として電気的に直列に接続されたセルブロックと、を有し、
複数の前記セルトランジスタのゲート電極が前記シリコン基板主面に対して垂直方向に繰り返し形成されていることを特徴とする不揮発性半導体記憶装置。 - 前記シリコン基板主面に等間隔で形成された四角柱状のシリコン柱をさらに有し、
前記セルブロックの前記セルトランジスタは前記シリコン柱の側面に形成されていることを特徴とする請求項1に記載の不揮発性半導体記憶装置。 - 前記シリコン柱上部に形成されたブロック選択トランジスタをさらに有し、
前記セルブロックの一端は、前記ブロック選択トランジスタを介して電気的にビット線に接続されていることを特徴とする請求項2に記載の不揮発性半導体記憶装置。 - 前記シリコン柱上部に形成されたプレート選択トランジスタをさらに有し、
前記セルブロックの一端は、前記プレート選択トランジスタを介して電気的にプレート線に接続されていることを特徴とする請求項3に記載の不揮発性半導体記憶装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2006105739A JP4745108B2 (ja) | 2006-04-06 | 2006-04-06 | 不揮発性半導体記憶装置 |
US11/689,725 US7649763B2 (en) | 2006-04-06 | 2007-03-22 | Nonvolatile ferroelectric memory |
Applications Claiming Priority (1)
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---|---|---|---|
JP2006105739A JP4745108B2 (ja) | 2006-04-06 | 2006-04-06 | 不揮発性半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
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JP2007281198A JP2007281198A (ja) | 2007-10-25 |
JP4745108B2 true JP4745108B2 (ja) | 2011-08-10 |
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JP2006105739A Expired - Fee Related JP4745108B2 (ja) | 2006-04-06 | 2006-04-06 | 不揮発性半導体記憶装置 |
Country Status (2)
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US (1) | US7649763B2 (ja) |
JP (1) | JP4745108B2 (ja) |
Families Citing this family (52)
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JP4945248B2 (ja) * | 2007-01-05 | 2012-06-06 | 株式会社東芝 | メモリシステム、半導体記憶装置及びその駆動方法 |
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JP5462490B2 (ja) | 2009-01-19 | 2014-04-02 | 株式会社日立製作所 | 半導体記憶装置 |
JP2010219409A (ja) * | 2009-03-18 | 2010-09-30 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP4929332B2 (ja) | 2009-09-24 | 2012-05-09 | 株式会社東芝 | 電子部品の製造方法 |
US8835990B2 (en) * | 2011-08-12 | 2014-09-16 | Winbond Electronics Corp. | 3D memory array |
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CN113689904A (zh) * | 2020-07-03 | 2021-11-23 | 长江存储科技有限责任公司 | 用于对三维FeRAM中的存储单元进行读取和写入的方法 |
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JP2000022010A (ja) * | 1998-06-30 | 2000-01-21 | Toshiba Corp | 半導体記憶装置 |
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-
2006
- 2006-04-06 JP JP2006105739A patent/JP4745108B2/ja not_active Expired - Fee Related
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- 2007-03-22 US US11/689,725 patent/US7649763B2/en active Active
Patent Citations (4)
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JP2000022010A (ja) * | 1998-06-30 | 2000-01-21 | Toshiba Corp | 半導体記憶装置 |
JP2001168294A (ja) * | 1999-12-09 | 2001-06-22 | Seiko Epson Corp | メモリデバイス及びその製造方法、並びに電子機器 |
JP2002217381A (ja) * | 2000-11-20 | 2002-08-02 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JP2005268438A (ja) * | 2004-03-17 | 2005-09-29 | Sharp Corp | 電界効果トランジスタおよびその作製方法 |
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JP2007281198A (ja) | 2007-10-25 |
US7649763B2 (en) | 2010-01-19 |
US20070236979A1 (en) | 2007-10-11 |
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