JP4651815B2 - ダマシン配線および半導体装置 - Google Patents
ダマシン配線および半導体装置 Download PDFInfo
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- JP4651815B2 JP4651815B2 JP2000529004A JP2000529004A JP4651815B2 JP 4651815 B2 JP4651815 B2 JP 4651815B2 JP 2000529004 A JP2000529004 A JP 2000529004A JP 2000529004 A JP2000529004 A JP 2000529004A JP 4651815 B2 JP4651815 B2 JP 4651815B2
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- Prior art keywords
- pad groove
- closing
- groove
- insulating film
- conductive film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05546—Dual damascene structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Description
意されたい。
11 …ダマシン配線部
12 …半導体基板
14,28 …絶縁膜
16 …配線溝
18 …パッド溝
20 …突起(島状突起,突条,突部)
22,30 …導電膜
24 …レジスト
26 …コンタクトホール
Claims (6)
- 絶縁膜に形成された配線溝およびこれに連通するパッド溝、
前記パッド溝中において前記絶縁膜を部分的に除去しないことによって前記絶縁膜で形成されるかつ前記パッド溝の実質的な開口面積を小さくする複数の閉鎖突条、
前記配線溝および前記パッド溝中に埋め込まれる導電膜、および
前記パッド溝中に形成されるかつ前記導電膜と前記絶縁膜の下に配置されている別の導電膜とを電気的に接続するコンタクトホールを備えるダマシン配線において、
前記複数の閉鎖突条は、それぞれ異なる大きさを有し、閉鎖する範囲の大きい前記閉鎖突条が閉鎖する範囲の小さい前記閉鎖突条を囲み、少なくとも前記パッド溝の中央部を閉鎖するように設け、
前記パッド溝内には閉鎖突条として、前記複数の閉鎖突条のみ設けられたことを特徴とする、ダマシン配線。 - 前記複数の閉鎖突条を、前記パッド溝の中央を中心として上下に分断する第1突条をさらに備える、請求項1記載のダマシン配線。
- 前記複数の閉鎖突条を、前記パッド溝の中央を中心として左右に分断する第2突条をさらに備える、請求項1または2記載のダマシン配線。
- 半導体基板、
前記半導体基板上に形成される絶縁膜、
前記絶縁膜上に形成されかつ半導体素子に通じる配線溝、
前記絶縁膜上に形成されかつ前記配線溝に通じるパッド溝、
前記パッド溝中において前記絶縁膜を部分的に除去しないことによって前記絶縁膜で形成されるかつ前記パッド溝の実質的な開口面積を小さくする複数の閉鎖突条、
前記配線溝および前記パッド溝中に埋め込まれる導電膜、および
前記パッド溝中に形成されるかつ前記導電膜と前記絶縁膜の下に配置されている別の導電膜とを電気的に接続するコンタクトホールを備える半導体装置において、
前記複数の閉鎖突条は、それぞれ異なる大きさを有し、閉鎖する範囲の大きい前記閉鎖突条が閉鎖する範囲の小さい前記閉鎖突条を囲み、少なくとも前記パッド溝の中央部を閉鎖するように設け、
前記パッド溝内には閉鎖突条として、前記複数の閉鎖突条のみ設けられたことを特徴とする、半導体装置。 - 前記複数の閉鎖突条を、前記パッド溝の中央を中心として上下に分断する第1突条をさらに備える、請求項4記載の半導体装置。
- 前記複数の閉鎖突条を、前記パッド溝の中央を中心として左右に分断する第2突条をさらに備える、請求項4または5記載の半導体装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1135498 | 1998-01-23 | ||
PCT/JP1999/000225 WO1999038204A1 (fr) | 1998-01-23 | 1999-01-22 | Interconnexion damasquinee et dispositif a semi-conducteur |
Publications (1)
Publication Number | Publication Date |
---|---|
JP4651815B2 true JP4651815B2 (ja) | 2011-03-16 |
Family
ID=11775707
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000529004A Expired - Fee Related JP4651815B2 (ja) | 1998-01-23 | 1999-01-22 | ダマシン配線および半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (2) | US6879049B1 (ja) |
JP (1) | JP4651815B2 (ja) |
TW (1) | TW410392B (ja) |
WO (1) | WO1999038204A1 (ja) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
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WO1999038204A1 (fr) * | 1998-01-23 | 1999-07-29 | Rohm Co., Ltd. | Interconnexion damasquinee et dispositif a semi-conducteur |
JP3685722B2 (ja) | 2001-02-28 | 2005-08-24 | 三洋電機株式会社 | 半導体装置及びその製造方法 |
EP1635399B1 (en) * | 2004-09-08 | 2011-05-04 | STMicroelectronics Srl | Lateral MOS device and method of making the same |
US7791199B2 (en) * | 2006-11-22 | 2010-09-07 | Tessera, Inc. | Packaged semiconductor chips |
US8569876B2 (en) | 2006-11-22 | 2013-10-29 | Tessera, Inc. | Packaged semiconductor chips with array |
JP5584474B2 (ja) * | 2007-03-05 | 2014-09-03 | インヴェンサス・コーポレイション | 貫通ビアによって前面接点に接続された後面接点を有するチップ |
US8134235B2 (en) * | 2007-04-23 | 2012-03-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional semiconductor device |
JP2010535427A (ja) | 2007-07-31 | 2010-11-18 | テッセラ,インコーポレイテッド | 貫通シリコンビアを使用する半導体実装プロセス |
US8053900B2 (en) * | 2008-10-21 | 2011-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate vias (TSVs) electrically connected to a bond pad design with reduced dishing effect |
US8796135B2 (en) | 2010-07-23 | 2014-08-05 | Tessera, Inc. | Microelectronic elements with rear contacts connected with via first or via middle structures |
US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
US8791575B2 (en) | 2010-07-23 | 2014-07-29 | Tessera, Inc. | Microelectronic elements having metallic pads overlying vias |
US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
US8610259B2 (en) | 2010-09-17 | 2013-12-17 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
KR101059490B1 (ko) * | 2010-11-15 | 2011-08-25 | 테세라 리써치 엘엘씨 | 임베드된 트레이스에 의해 구성된 전도성 패드 |
US8587126B2 (en) | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
US8736066B2 (en) | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
US8637968B2 (en) | 2010-12-02 | 2014-01-28 | Tessera, Inc. | Stacked microelectronic assembly having interposer connecting active chips |
US8610264B2 (en) | 2010-12-08 | 2013-12-17 | Tessera, Inc. | Compliant interconnects in wafers |
US8841675B2 (en) | 2011-09-23 | 2014-09-23 | Semiconductor Energy Laboratory Co., Ltd. | Minute transistor |
Citations (5)
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JPH1092779A (ja) * | 1996-09-18 | 1998-04-10 | Toshiba Corp | 半導体装置及びその製造方法 |
JPH10229085A (ja) * | 1997-02-14 | 1998-08-25 | Hitachi Ltd | 半導体装置及びその製造方法 |
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-
1999
- 1999-01-22 WO PCT/JP1999/000225 patent/WO1999038204A1/ja active Application Filing
- 1999-01-22 TW TW088100951A patent/TW410392B/zh not_active IP Right Cessation
- 1999-01-22 JP JP2000529004A patent/JP4651815B2/ja not_active Expired - Fee Related
- 1999-01-22 US US09/600,931 patent/US6879049B1/en not_active Expired - Lifetime
-
2005
- 2005-02-22 US US11/063,148 patent/US7042100B2/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06318590A (ja) * | 1993-05-10 | 1994-11-15 | Nec Corp | 半導体装置の製造方法 |
JPH09148329A (ja) * | 1995-09-14 | 1997-06-06 | Canon Inc | 半導体装置及びアクティブマトリクス基板およびそれらの製造方法 |
JPH1064938A (ja) * | 1996-08-21 | 1998-03-06 | Toshiba Corp | 半導体装置及びその製造方法 |
JPH1092779A (ja) * | 1996-09-18 | 1998-04-10 | Toshiba Corp | 半導体装置及びその製造方法 |
JPH10229085A (ja) * | 1997-02-14 | 1998-08-25 | Hitachi Ltd | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
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WO1999038204A1 (fr) | 1999-07-29 |
US6879049B1 (en) | 2005-04-12 |
US20050156332A1 (en) | 2005-07-21 |
TW410392B (en) | 2000-11-01 |
US7042100B2 (en) | 2006-05-09 |
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