JPH0727921B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

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Publication number
JPH0727921B2
JPH0727921B2 JP62190096A JP19009687A JPH0727921B2 JP H0727921 B2 JPH0727921 B2 JP H0727921B2 JP 62190096 A JP62190096 A JP 62190096A JP 19009687 A JP19009687 A JP 19009687A JP H0727921 B2 JPH0727921 B2 JP H0727921B2
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JP
Japan
Prior art keywords
film
semiconductor device
temperature
bonding
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62190096A
Other languages
English (en)
Other versions
JPS6436038A (en
Inventor
公麿 吉川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62190096A priority Critical patent/JPH0727921B2/ja
Priority to US07/224,603 priority patent/US4933305A/en
Publication of JPS6436038A publication Critical patent/JPS6436038A/ja
Publication of JPH0727921B2 publication Critical patent/JPH0727921B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01L23/00Details of semiconductor or other solid state devices
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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特にワイヤボン
ディングを改善した半導体装置の製造方法に関する。
〔従来の技術〕
従来、半導体装置に設けたボンディングパッドを外部導
出用のリードに電気的に接続する方法として、ボンディ
ングパッドとリードとを金線等のワイヤで接続するワイ
ヤボンディング工程が施される。このワイヤボンディン
グ技術としては、所謂NTC法(ネイルヘッド・サーモコ
ンプレションボンディング法)と呼ばれる熱圧着法が一
般に用いられていた。
〔発明が解決しようとする問題点〕
上述した従来のNTC法では、金線をアルミニウムパッド
に熱エネルギーによって圧着しているので、圧着歩留り
を上げるため、圧着時の温度は350℃〜375℃の高温で形
成している。
しかるに、第2図に示すように、半導体装置のシリコン
基板11上に設けたPSG膜12上の絶縁膜としてポリイミド
等の有機膜13が用いられ、更にその耐湿性パッシベーシ
ョン膜として不透水性の窒化膜15が用いられるようにな
ると、ウェハー工程での最終加熱温度は高々320℃とな
り、この熱処理温度に比較して上述したワイヤボンディ
ング温度が高くなる。このため、ワイヤボンディング時
の高熱によって有機膜から水を主成分とするアウトガス
が発生し、これが窒化膜との間に溜まって第2図のよう
に、ウェハー工程では発生しない窒化膜の膨れや剥がれ
発生し、絶縁効果やパッシベーション効果が低下される
という問題がある。
本発明は、このような絶縁膜の膨れや剥がれを防止して
絶縁効果やパッシベーション効果の高い半導体装置を製
造することができる方法を提供することを目的としてい
る。
〔問題点を解決するための手段〕
本発明の半導体装置の製造方法は、半導体基体主面上に
有機絶縁膜と無機絶縁膜を積層し、かつ電極パッドにワ
イヤを接続してなる半導体装置の製造に際し、ワイヤの
ボンディング温度を無機絶縁膜の生成温度よりも低温に
設定し、ボンディング処理によるアウトガスの発生を防
止している。
〔実施例〕
次に、本発明を図面を参照して説明する。
第1図は本発明の一実施例の縦断面図である。素子を形
成した(100)結晶軸のP形シリコン基板1上に4モル
%濃度のPSG(リンシリケートガラス)膜2を約1μm
化学気相成長法により形成し、シリコン基板1に形成し
た素子上に図外のコンタクトホールを開設する。
また、図示は省略するが、このPSG膜2上にアルミニウ
ム膜を直流スパッタ法により約1μm形成し、これをパ
ターニングして第1層アルミニウム配線を形成する。
そして、この上に層間絶縁膜として (R1:4価の炭素環式芳香族)で表されるテトラカルボン
酸二無水物と、 NH2−R2−NH2 (R2:炭素数6〜30個の芳香脂肪族気基または炭素環式
芳香族基)で表されるジアミンと、 (R3,R4:それぞれ独立の炭素数1〜6のアルキル基ま
たはフェニル基1≦K≦3)で表されるアミノシリコン
化合物とを混合反応したものを用いる。
そして、この混合反応することにより形成されたポリア
ミド酸シリコン型中間体を含む溶液を、前記半導体基板
の主面に毎分4000回転で30秒間回転塗布し、窒素ガス雰
囲気で,100℃,1時間、続いて240℃で30分間のプリベー
クを行い、更に窒素ガス雰囲気中で400℃,1時間のポス
トベークして1μmの絶縁膜を形成する。
続いて、図示は省略するが、前面にチタン膜を形成し、
フォトリソグラフィによりフォトレジストをマスクにCC
l4ガスを用いてこのチタン膜をエッチングする。そし
て、このチタンをマスクにCF4+O2の混合ガスで前記有
機樹脂膜をエッチングする。更に、この上に第2層目の
アルミルウム膜4を1μmスパッタしてその一部にパッ
ド4を形成し、更にこの上に耐湿性パッシベーションと
してのシリコン窒化膜5をSiH4=180sccm,NH3=1080scc
mのガス流量で320℃のプラズマ反応炉中で約1.0μm形
成し、フォトリソグラフィにより(図示せず)パターニ
ングする。
組立は、直径35μmのワイヤ(金線)6をNTCの一種で2
00℃に加熱して、周波数66KHz,0.6Wのパワーの超音波を
5〜15msec印加しながら、アルミニウムパッド4にボン
ディングする。
したがって、この方法ではボンディング時の温度がパッ
シベーションとしてのシリコン窒化膜5の生成温度より
も低い温度であるため、ボンディング工程によっても有
機絶縁膜からアウトガスが発生することはなく、パッシ
ベーション膜における膨れや押上等の不具合の発生を防
止できる。
また、本発明の他の実施例としては、層間有機樹脂膜上
の耐湿性パッシベーション膜として、オキシナイトライ
ドを320℃でSiH4=180sccm,NH3=972sccm,N2O=108scc
mのガス流量で、2Torrの圧力で約1.0μm形成する。そ
して、この膜をフォトリソグラフィによりパターニング
した後、35μm径の金線をNTC法により309℃でアルミニ
ウムパッドに圧着する。
〔発明の効果〕
以上説明したように本発明は、ワイヤのボンディング温
度を有機絶縁膜上に形成した無機絶縁膜の生成温度より
も低い温度にしているので、ボンディング中の熱処理に
より有機樹脂層間膜からの水を主成分とするアウトガス
が発生してパッシベーション膜を押上げたり膨れを発生
させることを防止できる効果がある。
【図面の簡単な説明】
第1図は本発明の一実施例の縦断面図、第2図は従来方
法による窒化膜膨れ不良を示す断面図である。 1……シリコン基板、2……PSG膜、3……ポリイミド
膜、4……アルミニウムパッド、5……窒化膜、6……
ワイヤ、11……シリコン基板、12……PSG膜、13……ポ
リイミド膜、14……窒化膜。

Claims (1)

    【特許請求の範囲】
  1. 【請求項1】半導体基体主面上に有機絶縁膜と無機絶縁
    膜を積層し、かつ電極パッドにワイヤを接続してなる半
    導体装置の製造に際し、前記ワイヤのボンディング温度
    を前記無機絶縁膜の生成温度よりも低温に設定したこと
    を特徴とする半導体装置の製造方法。
JP62190096A 1987-07-31 1987-07-31 半導体装置の製造方法 Expired - Lifetime JPH0727921B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP62190096A JPH0727921B2 (ja) 1987-07-31 1987-07-31 半導体装置の製造方法
US07/224,603 US4933305A (en) 1987-07-31 1988-07-27 Process of wire bonding for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62190096A JPH0727921B2 (ja) 1987-07-31 1987-07-31 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS6436038A JPS6436038A (en) 1989-02-07
JPH0727921B2 true JPH0727921B2 (ja) 1995-03-29

Family

ID=16252304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62190096A Expired - Lifetime JPH0727921B2 (ja) 1987-07-31 1987-07-31 半導体装置の製造方法

Country Status (2)

Country Link
US (1) US4933305A (ja)
JP (1) JPH0727921B2 (ja)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0821579B2 (ja) * 1989-04-19 1996-03-04 旭硝子株式会社 半導体素子・集積回路装置
JPH0423485A (ja) * 1990-05-18 1992-01-27 Cmk Corp プリント配線板とその製造法
JPH0695593B2 (ja) * 1990-09-28 1994-11-24 富士通株式会社 プリント基板の改造方法
US5109320A (en) * 1990-12-24 1992-04-28 Westinghouse Electric Corp. System for connecting integrated circuit dies to a printed wiring board
JP2593965B2 (ja) * 1991-01-29 1997-03-26 三菱電機株式会社 半導体装置
JP2550248B2 (ja) * 1991-10-14 1996-11-06 株式会社東芝 半導体集積回路装置およびその製造方法
US5567981A (en) * 1993-03-31 1996-10-22 Intel Corporation Bonding pad structure having an interposed rigid layer
US5486657A (en) * 1994-06-09 1996-01-23 Dell Usa, L.P. Beveled edge circuit board with channeled connector pads
IL110261A0 (en) * 1994-07-10 1994-10-21 Schellcase Ltd Packaged integrated circuit
US5661082A (en) * 1995-01-20 1997-08-26 Motorola, Inc. Process for forming a semiconductor device having a bond pad
US5900668A (en) * 1995-11-30 1999-05-04 Advanced Micro Devices, Inc. Low capacitance interconnection
US6879049B1 (en) * 1998-01-23 2005-04-12 Rohm Co., Ltd. Damascene interconnection and semiconductor device
US6187680B1 (en) 1998-10-07 2001-02-13 International Business Machines Corporation Method/structure for creating aluminum wirebound pad on copper BEOL
TW426980B (en) * 1999-01-23 2001-03-21 Lucent Technologies Inc Wire bonding to copper
WO2012099771A1 (en) * 2011-01-17 2012-07-26 Orthodyne Electronics Corporation Systems and methods for processing ribbon and wire in ultrasonic bonding systems
US8800846B2 (en) * 2012-01-27 2014-08-12 Apple Inc. Ultrasonic bonding
US9129951B2 (en) * 2013-10-17 2015-09-08 Freescale Semiconductor, Inc. Coated lead frame bond finger
DE102018105462A1 (de) * 2018-03-09 2019-09-12 Infineon Technologies Ag Halbleitervorrichtung, die ein bondpad und einen bonddraht oder -clip enthält

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56137658A (en) * 1980-03-31 1981-10-27 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor device
JPS57209911A (en) * 1981-06-22 1982-12-23 Toyo Ink Mfg Co Ltd Production of polyethylene resin molding
JPS60102780A (ja) * 1983-11-09 1985-06-06 Hitachi Ltd 磁気抵抗素子

Also Published As

Publication number Publication date
US4933305A (en) 1990-06-12
JPS6436038A (en) 1989-02-07

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