JP4393312B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4393312B2 JP4393312B2 JP2004248221A JP2004248221A JP4393312B2 JP 4393312 B2 JP4393312 B2 JP 4393312B2 JP 2004248221 A JP2004248221 A JP 2004248221A JP 2004248221 A JP2004248221 A JP 2004248221A JP 4393312 B2 JP4393312 B2 JP 4393312B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- stiffener
- thermal expansion
- adhesive
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10568—Integral adaptations of a component or an auxiliary PCB for mounting, e.g. integral spacer element
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
- H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
- H05K3/305—Affixing by adhesive
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
12…基板
14…半導体素子
16…スティフナ
18…接着剤
20…バンプ
22…アンダーフィル
24…外部端子
26…電気部品
30…プリント基板
32…端子
34…ヒートシンク
36…フィン
38…熱伝導部材
40…支持板
42…ねじ
44…スプリング
Claims (6)
- 基板と、
前記基板に搭載された半導体素子と、
前記基板の前記半導体素子が搭載された面とは反対側の面に接着剤により取付けられたスティフナとを備え、
前記スティフナは前記半導体素子の外形とほぼ同じ外形を有する枠形状のものであり、
前記接着剤の熱膨張率は前記基板の熱膨張率及び前記スティフナの熱膨張率よりも小さく、かつ、前記接着剤の縦弾性係数は10GPa以上であることを特徴とする半導体装置。 - 基板と、
前記基板に搭載された半導体素子と、
前記基板の前記半導体素子とは反対側の面に接着剤により取付けられたスティフナとを備え、
前記スティフナは前記半導体素子の外形とほぼ同じ外形を有する枠形状のものであり、
前記接着剤の熱膨張率は前記基板の熱膨張率及び前記スティフナの熱膨張率よりも大きく、かつ、前記接着剤の縦弾性係数は10GPa以下であることを特徴とする半導体装置。 - 前記基板の熱膨張率と前記スティフナの熱膨張率とが、ほぼ同じであることを特徴とする請求項1または2に記載の半導体装置。
- 前記基板の前記スティフナのまわりに外部端子が設けられ、前記スティフナの高さは前記外部端子の高さよりも小さいことを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- 前記外部端子に接続される端子を有するプリント基板をさらに備え、
前記スティフナは前記プリント基板の表面に接触していることを特徴とする請求項4に記載の半導体装置。 - 冷却部材が熱伝導部材を介して前記半導体素子に結合され、前記冷却部材は前記プリント基板に固定されることを特徴とする請求項5に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004248221A JP4393312B2 (ja) | 2004-08-27 | 2004-08-27 | 半導体装置 |
US10/992,651 US7053493B2 (en) | 2004-08-27 | 2004-11-22 | Semiconductor device having stiffener |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004248221A JP4393312B2 (ja) | 2004-08-27 | 2004-08-27 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006066693A JP2006066693A (ja) | 2006-03-09 |
JP4393312B2 true JP4393312B2 (ja) | 2010-01-06 |
Family
ID=35941901
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004248221A Expired - Fee Related JP4393312B2 (ja) | 2004-08-27 | 2004-08-27 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7053493B2 (ja) |
JP (1) | JP4393312B2 (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070020908A1 (en) * | 2005-07-18 | 2007-01-25 | Tessera, Inc. | Multilayer structure having a warpage-compensating layer |
WO2007139799A2 (en) * | 2006-05-24 | 2007-12-06 | Mayo Foundation For Medical Education And Research | Devices and methods for crossing chronic total occlusions |
JP4871676B2 (ja) * | 2006-08-30 | 2012-02-08 | 日立オートモティブシステムズ株式会社 | 電子回路装置 |
US20080079129A1 (en) * | 2006-09-29 | 2008-04-03 | Shankar Ganapathysubramanian | Shape memory based mechanical enabling mechanism |
US8952511B2 (en) * | 2007-12-18 | 2015-02-10 | Intel Corporation | Integrated circuit package having bottom-side stiffener |
JP5445340B2 (ja) * | 2010-06-10 | 2014-03-19 | 富士通株式会社 | 基板補強構造、基板組立体、及び電子機器 |
US8261618B2 (en) * | 2010-11-22 | 2012-09-11 | General Electric Company | Device for measuring properties of working fluids |
US8994192B2 (en) | 2011-12-15 | 2015-03-31 | Stats Chippac Ltd. | Integrated circuit packaging system with perimeter antiwarpage structure and method of manufacture thereof |
JP2014170819A (ja) * | 2013-03-01 | 2014-09-18 | Nikon Corp | 撮像ユニットおよび撮像装置 |
US9385091B2 (en) | 2013-03-08 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reinforcement structure and method for controlling warpage of chip mounted on substrate |
JP6421491B2 (ja) * | 2014-08-13 | 2018-11-14 | 富士通株式会社 | 電子機器 |
DE102016219423A1 (de) * | 2016-10-06 | 2018-04-12 | Robert Bosch Gmbh | Anordnung |
EP3340293A1 (de) * | 2016-12-20 | 2018-06-27 | Siemens Aktiengesellschaft | Halbleitermodul mit stützstruktur auf der unterseite |
JP2018121367A (ja) * | 2018-04-23 | 2018-08-02 | 株式会社ニコン | 撮像ユニットおよび撮像装置 |
US10403560B2 (en) * | 2018-09-28 | 2019-09-03 | Intel Corporation | Thermal cooling system |
US10756031B1 (en) | 2019-05-10 | 2020-08-25 | International Business Machines Corporation | Decoupling capacitor stiffener |
JP2020025332A (ja) * | 2019-11-06 | 2020-02-13 | 株式会社ニコン | 撮像ユニットおよび撮像装置 |
KR20210073904A (ko) | 2019-12-11 | 2021-06-21 | 삼성전기주식회사 | 기판 온 기판 구조 및 이를 포함하는 전자기기 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS6066843A (ja) * | 1983-09-22 | 1985-04-17 | Hitachi Ltd | 集積回路パツケ−ジ |
JPH0676790B2 (ja) * | 1987-07-30 | 1994-09-28 | 株式会社東芝 | イグナイタ |
JPH065699B2 (ja) * | 1987-09-16 | 1994-01-19 | 日本電気株式会社 | 半導体装置 |
JPH03295263A (ja) | 1990-04-13 | 1991-12-26 | Ibiden Co Ltd | フィルム基材を使用した半導体装置 |
JPH064579A (ja) | 1992-06-18 | 1994-01-14 | Casio Comput Co Ltd | 情報管理装置 |
JPH06204654A (ja) | 1993-01-06 | 1994-07-22 | Nec Corp | 高密度実装プリント基板 |
JP2974552B2 (ja) * | 1993-06-14 | 1999-11-10 | 株式会社東芝 | 半導体装置 |
JPH08153938A (ja) | 1994-11-29 | 1996-06-11 | Toshiba Corp | フレキシブル印刷基板 |
JP2970491B2 (ja) * | 1995-09-20 | 1999-11-02 | ソニー株式会社 | 半導体パッケージ及びその製造方法 |
JPH11260953A (ja) * | 1998-03-09 | 1999-09-24 | Shinko Electric Ind Co Ltd | 半導体チップの実装構造 |
US6194782B1 (en) * | 1998-06-24 | 2001-02-27 | Nortel Networks Limited | Mechanically-stabilized area-array device package |
JP2000174176A (ja) | 1998-12-01 | 2000-06-23 | Tokin Corp | Icモジュール用のリードフレーム、及びそれを用いたicモジュール、並びにicカード |
JP2001015561A (ja) | 1999-06-28 | 2001-01-19 | Hitachi Cable Ltd | 放熱板兼補強板付きtabテープ及び半導体装置 |
JP2001101375A (ja) | 1999-10-01 | 2001-04-13 | Denso Corp | Icカード |
JP2002231769A (ja) | 2001-01-31 | 2002-08-16 | Hitachi Cable Ltd | テープキャリア及びその製造方法 |
JP2002252301A (ja) | 2001-02-21 | 2002-09-06 | Sony Corp | 電子部品実装基板及びその製造方法 |
US7094975B2 (en) * | 2003-11-20 | 2006-08-22 | Delphi Technologies, Inc. | Circuit board with localized stiffener for enhanced circuit component reliability |
-
2004
- 2004-08-27 JP JP2004248221A patent/JP4393312B2/ja not_active Expired - Fee Related
- 2004-11-22 US US10/992,651 patent/US7053493B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US7053493B2 (en) | 2006-05-30 |
US20060043548A1 (en) | 2006-03-02 |
JP2006066693A (ja) | 2006-03-09 |
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