JP4377768B2 - Semiconductor element storage package and semiconductor device - Google Patents

Semiconductor element storage package and semiconductor device Download PDF

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JP4377768B2
JP4377768B2 JP2004220832A JP2004220832A JP4377768B2 JP 4377768 B2 JP4377768 B2 JP 4377768B2 JP 2004220832 A JP2004220832 A JP 2004220832A JP 2004220832 A JP2004220832 A JP 2004220832A JP 4377768 B2 JP4377768 B2 JP 4377768B2
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capacitor
semiconductor element
line conductor
circuit board
mounting portion
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JP2006041285A (en
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道信 飯野
隆行 白崎
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

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Description

本発明は、高周波信号で作動する半導体素子を収納するための半導体素子収納用パッケージおよび半導体素子を収納する半導体装置に関する。   The present invention relates to a semiconductor element storage package for storing a semiconductor element that operates with a high-frequency signal, and a semiconductor device that stores the semiconductor element.

従来の光通信や無線通信分野に用いられる高周波用の各種半導体素子を収納する半導体素子収納用パッケージの断面図を図３に、その平面図を図４に示す。同図において、101は基体、102は金属製の枠体、103は蓋体、104は高周波用の回路基板である。   FIG. 3 is a cross-sectional view of a package for housing a semiconductor element for housing various high-frequency semiconductor elements used in the conventional optical communication and wireless communication fields, and FIG. 4 is a plan view thereof. In the figure, 101 is a base, 102 is a metal frame, 103 is a lid, and 104 is a high-frequency circuit board.

基体101は鉄（Ｆｅ）−ニッケル（Ｎｉ）−コバルト（Ｃｏ）合金や銅（Ｃｕ）−タングステン（Ｗ）等の金属から成る四角形状の板状体であり、その上側主面には、ＩＣ，ＬＳＩ，半導体レーザ（ＬＤ），フォトダイオード（ＰＤ）等の半導体素子105や、回路基板104を載置する載置部101ａが形成されている。半導体素子105や回路基板104は、載置部101ａに、例えば銀（Ａｇ）ろう，Ａｇ−銅（Ｃｕ）ろう等のろう材や半田、樹脂接着剤によって接着固定される。   The substrate 101 is a quadrangular plate-like body made of a metal such as iron (Fe) -nickel (Ni) -cobalt (Co) alloy or copper (Cu) -tungsten (W). , LSI, semiconductor laser (LD), photodiode (PD) and other semiconductor elements 105, and a mounting portion 101a on which the circuit board 104 is mounted. The semiconductor element 105 and the circuit board 104 are bonded and fixed to the mounting portion 101a with a brazing material such as silver (Ag) brazing, Ag-copper (Cu) brazing, solder, or a resin adhesive.

半導体素子105の電極は、回路基板104に被着されている第１の線路導体104aおよび第２の線路導体104bにそれぞれボンディングワイヤ106ａ，106ｂを介して電気的に接続されている。   The electrodes of the semiconductor element 105 are electrically connected to the first line conductor 104a and the second line conductor 104b attached to the circuit board 104 via bonding wires 106a and 106b, respectively.

さらに、第２の線路導体104ｂは、回路基板104の端部に被着されている同一面接地導体108に高抵抗体部107を介して終端接続されており、高抵抗体部107の手前の第２の線路導体104ｂにチップコンデンサ110が挿入されている。チップコンデンサ110は回路基板104に鉛（Ｐｂ）−錫（Ｓｎ）合金やＳｎ−Ａｇ−Ｃｕ合金等の半田，導電性のエポキシ樹脂等で接合され第２の線路導体104ｂに電気的に直列に挿入されている。また、同一面接地導体108は、面間接続導体109を介して基体101に電気的に接続されている。   Further, the second line conductor 104b is terminated and connected to the same surface ground conductor 108 attached to the end portion of the circuit board 104 via the high resistance portion 107, and is located in front of the high resistance portion 107. A chip capacitor 110 is inserted into the second line conductor 104b. The chip capacitor 110 is joined to the circuit board 104 with solder such as lead (Pb) -tin (Sn) alloy or Sn-Ag-Cu alloy, conductive epoxy resin, etc., and is electrically connected in series to the second line conductor 104b. Has been inserted. The same-surface ground conductor 108 is electrically connected to the base 101 via the inter-surface connection conductor 109.

このように第２の線路導体104ｂの終端を高抵抗体部107を介して同一面接地導体108に接続することにより、第２の線路導体104bに流れる高周波信号の反射を防ぎ、半導体素子105が誤動作するのを防いでいる。また、チップコンデンサ110は、第２の線路導体104ｂの終端部に挿入されることにより、半導体素子105から第２の線路導体104ｂに流れる高周波信号のみを高抵抗体部107へ伝送し、直流成分を遮断する機能を有している。   In this way, the end of the second line conductor 104b is connected to the same-plane ground conductor 108 via the high-resistance element 107, thereby preventing reflection of the high-frequency signal flowing through the second line conductor 104b. Prevents malfunction. Further, the chip capacitor 110 is inserted into the terminal portion of the second line conductor 104b, so that only the high-frequency signal flowing from the semiconductor element 105 to the second line conductor 104b is transmitted to the high-resistance element 107, and the direct current component It has a function to shut off.

基体101の上側主面の外周部には載置部101ａを囲むようにして枠体102が接合されており、枠体102の内側に半導体素子105を収容する空所を形成する。枠体102は、基体101と同様にＦｅ−Ｎｉ−Ｃｏ合金やＣｕ−Ｗの焼結材等から成り、基体101と一体成形されるか、または基体101にＡｇろう，Ａｇ−Ｃｕろう等のろう材を介してろう付けされるか、またはシーム溶接法等の溶接法により接合されることによって、基体101の上側主面の外周部に設けられる。 A frame body 102 is joined to the outer peripheral portion of the upper main surface of the base body 101 so as to surround the mounting portion 101 a, and a space for accommodating the semiconductor element 105 is formed inside the frame body 102. The frame 102 is made of an Fe—Ni—Co alloy, a Cu—W sintered material, or the like, similar to the base 101, and is integrally formed with the base 101, or is made of Ag brazing, Ag—Cu brazing or the like on the base 101. It is provided on the outer peripheral portion of the upper main surface of the base 101 by brazing via a brazing material or joining by a welding method such as a seam welding method.

枠体102の側面には中心導体，誘電体，外部導体が同心円状に配置された同軸構造のガラスビーズ111が嵌着される貫通孔102ａが形成されており、貫通孔102ａ内にガラスビーズ111を嵌め込むとともに半田等の封着材を貫通孔102ａ内の隙間に挿入し、しかる後、加熱して封着材を溶融させ、溶融した封着材を毛細管現象によりガラスビーズ111と貫通孔102ａの内壁との隙間に充填させることによって、ガラスビーズ111が貫通孔102ａ内に封着材を介して嵌着接合される。   A through hole 102a into which a glass bead 111 having a coaxial structure in which a central conductor, a dielectric, and an outer conductor are concentrically arranged is fitted is formed on a side surface of the frame 102, and the glass bead 111 is inserted into the through hole 102a. And a sealing material such as solder is inserted into the gap in the through hole 102a, and then heated to melt the sealing material, and the molten sealing material is made into the glass beads 111 and the through holes 102a by capillary action. By filling the gap with the inner wall, the glass beads 111 are fitted and joined into the through hole 102a via a sealing material.

ガラスビーズ111には、中心軸部分に信号線路としてＦｅ−Ｎｉ−Ｃｏ合金等の金属から成る棒状の中心導体が挿通されて固定されている。中心導体の一端は、半田等から成る導電性接着材を介して高周波用の回路基板104の第１の線路導体104ａに電気的に接続される。そして、中心導体の他端に、外部電気回路（図示せず）に接続された同軸ケーブル（図示せず）の中心導体が装着されることによって内部に収納された半導体素子105がガラスビーズ111の中心導体を介して外部電気回路に電気的に接続されることとなる。   A rod-shaped center conductor made of a metal such as an Fe—Ni—Co alloy is inserted and fixed to the glass bead 111 as a signal line at the center axis portion. One end of the center conductor is electrically connected to the first line conductor 104a of the circuit board 104 for high frequency via a conductive adhesive made of solder or the like. Then, the other end of the center conductor is attached with the center conductor of a coaxial cable (not shown) connected to an external electric circuit (not shown), so that the semiconductor element 105 housed inside is a glass bead 111. It is electrically connected to an external electric circuit through the center conductor.

最後に、枠体102の内側の空所となっている載置部101ａに半導体素子105を収容し、枠体102の上面に蓋体103をろう付け法やシームウエルド法等の溶接法により接合し、空所を気密に封止することによって製品としての半導体装置となる。
特開２００２−３１９６４５号公報 Finally, the semiconductor element 105 is accommodated in the mounting portion 101a which is a space inside the frame body 102, and the lid body 103 is joined to the upper surface of the frame body 102 by a welding method such as a brazing method or a seam weld method. In addition, a semiconductor device as a product is obtained by hermetically sealing the void.
JP 2002-319645 A

しかしながら、従来の回路基板104を使用した半導体素子収納用パッケージにおいては、高周波用途になるにつれ、チップコンデンサ110をその大きさから集中定数的に扱えなくなり、チップコンデンサ110とそれに近接する接地導体等との間に生じる容量成分によって、高抵抗体部107から見た特性インピーダンス値が変動し、高抵抗体部107が所望の終端特性を果たさないという問題が生じる。   However, in a package for housing a semiconductor element using the conventional circuit board 104, the chip capacitor 110 cannot be handled in a lumped constant due to its size as it becomes a high frequency application. The characteristic impedance value seen from the high resistance portion 107 fluctuates due to the capacitance component generated between the high resistance portion 107 and the high resistance portion 107 does not fulfill a desired termination characteristic.

本発明は上記問題点に鑑み完成されたものであり、その目的は、回路基板の上面に線路導体より幅広のコンデンサが途中に実装された線路導体において、コンデンサおよびコンデンサの実装部と基体との間に生じる容量成分を少なくし、線路導体の特性インピーダンス値が変動しない半導体素子収納用パッケージおよび半導体装置を提供することにある。   The present invention has been completed in view of the above problems, and its purpose is to provide a capacitor having a capacitor wider than the line conductor on the upper surface of the circuit board. It is an object of the present invention to provide a package for housing a semiconductor element and a semiconductor device in which a capacitance component generated between them is reduced and a characteristic impedance value of a line conductor does not vary.

本発明の半導体素子収納用パッケージは、上側主面に、半導体素子およびコンデンサが実装されている回路基板を載置するための載置部を有する基体を具備している半導体素子収納用パッケージにおいて、前記基体は、上側主面の前記コンデンサの直下の部位に平面視で前記コンデンサおよびその実装部を含む大きさの凹部が形成されており、該凹部の底面は、該底面の外周を凹ませて中央部を凸形状とした凹凸であることを特徴とするものである。 The semiconductor element storage package of the present invention is a semiconductor element storage package comprising a base body having a mounting portion for mounting a circuit board on which a semiconductor element and a capacitor are mounted on the upper main surface. The base has a concave portion having a size including the capacitor and its mounting portion in a plan view in a portion of the upper main surface immediately below the capacitor, and the bottom surface of the concave portion is formed by denting the outer periphery of the bottom surface. and it is characterized in uneven der Rukoto of which center part is convex.

また、本発明の半導体素子収納用パッケージは、上記構成において好ましくは、前記凹部は、平面視における面積が前記コンデンサおよびその実装部の面積の１６０乃至２５０％であることを特徴とするものである。   In the semiconductor element housing package according to the present invention, preferably, the recess has an area in a plan view of 160 to 250% of the area of the capacitor and its mounting portion. .

また、本発明の半導体装置は、上記本発明の半導体素子収納用パッケージと、前記載置部に載置され、前記回路基板の回路配線に電気的に接続された前記半導体素子と、前記基体の外周部に前記載置部を囲むように接合された枠体と、前記枠体の上面に枠体の内側を塞ぐように取着された蓋体とを具備していることを特徴とするものである。   The semiconductor device of the present invention includes the semiconductor element storage package of the present invention, the semiconductor element mounted on the mounting portion and electrically connected to the circuit wiring of the circuit board, and the base A frame that is joined to the outer periphery to surround the mounting portion, and a lid that is attached to an upper surface of the frame so as to close the inside of the frame. It is.

本発明の半導体素子収納用パッケージによれば、上側主面に、半導体素子およびコンデンサが実装されている回路基板を載置するための載置部を有する基体を具備しており、基体は、上側主面のコンデンサの直下の部位に平面視でコンデンサおよびその実装部を含む大きさの凹部が形成されており、この凹部の底面は、この底面の外周を凹ませて中央部を凸形状とした凹凸であることから、基体の表面とコンデンサおよびその実装部である電極部分と線路導体との接続部との間に空間が形成され、コンデンサおよびその実装部と基体との間に生じる容量成分を少なくすることができる。また、凹部の底面は、この底面の外周を凹ませて中央部を凸形状とした凹凸であることから、コンデンサの実装部に対向する凹部の底面の外周が凹んでいるため、コンデンサの実装部分で、コンデンサの端子材の厚みやコンデンサを実装する際に使用する半田のメニスカスが生じる分、線路幅が広くなって容量成分が大きくなるとともに、コンデンサの端子材や半田の厚みの分、上下方向にも線路導体の厚みが厚くなったように見え、この厚くなっているコンデンサの実装部の側面と基体との間で電気力線が生じて容量成分が生じ、コンデンサの実装部と基体との間で容量成分が大きくなることを抑制することが可能となる。 According to the package for housing a semiconductor element of the present invention, the upper main surface includes a base having a mounting portion for mounting the circuit board on which the semiconductor element and the capacitor are mounted. A concave portion having a size including the capacitor and its mounting portion is formed in a plan view in a portion immediately below the capacitor on the main surface, and the bottom surface of the concave portion has a convex shape at the center portion with the outer periphery of the bottom surface recessed. from irregularities der Rukoto, space is formed between the connection portion between the electrode portion and the line conductor is a surface condenser and a mounting portion of the base, the capacity component generated between the capacitor and the mounting portion and the base thereof Can be reduced. In addition, the bottom surface of the recess is a concave / convex shape with the outer periphery of the bottom surface being recessed and the central portion is convex, so the outer periphery of the bottom surface of the recess facing the mounting portion of the capacitor is recessed. Therefore, the thickness of the capacitor terminal material and the solder meniscus used when mounting the capacitor are generated, the line width is increased and the capacitance component is increased, and the capacitor terminal material and the thickness of the solder are increased in the vertical direction. It appears that the thickness of the line conductor has increased, and electric lines of force are generated between the side surface of the mounting portion of the thick capacitor and the base to generate a capacitance component. It is possible to suppress the capacity component from increasing between the two.

その結果、10ＧＨｚ以上の高周波においても容量成分が少なくなり、回路基板の上側主面に形成される線路導体の特性インピーダンスが変動しないので、良好な伝送特性が実現でき、半導体素子を正常に作動させることができる。   As a result, the capacitance component is reduced even at a high frequency of 10 GHz or higher, and the characteristic impedance of the line conductor formed on the upper main surface of the circuit board does not fluctuate, so that good transmission characteristics can be realized and the semiconductor element operates normally. be able to.

また、本発明の半導体素子収納用パッケージによれば、好ましくは、凹部は、平面視における面積がコンデンサおよびその実装部の面積の１６０乃至２５０％である場合には、基体の表面とコンデンサおよびその実装部である電極部分と線路導体との接続部との間に適度な空間が形成され、コンデンサおよびその実装部と基体との間に生じる寄生容量成分を少なくすることができる。   Further, according to the package for housing a semiconductor element of the present invention, preferably, when the area in plan view is 160 to 250% of the area of the capacitor and its mounting part, the recess, the surface of the substrate, the capacitor, and its An appropriate space is formed between the electrode portion which is the mounting portion and the connection portion between the line conductor, and the parasitic capacitance component generated between the capacitor and the mounting portion and the base body can be reduced.

また、本発明の半導体装置によれば、上記本発明の半導体素子収納用パッケージと、載置部に載置され、回路基板の回路配線に電気的に接続された半導体素子と、基体の外周部に載置部を囲むように接合された枠体と、枠体の上面に枠体の内側を塞ぐように接合された蓋体とを具備していることから、回路基板の上側主面に形成される線路導体の特性インピーダンスが所望の値に近いものとなり、良好な電気特性を示す半導体装置となる。   Further, according to the semiconductor device of the present invention, the semiconductor element storage package of the present invention, the semiconductor element mounted on the mounting portion and electrically connected to the circuit wiring of the circuit board, and the outer peripheral portion of the substrate Formed on the upper main surface of the circuit board since the frame body joined to surround the mounting portion and the lid body joined to the upper surface of the frame so as to close the inside of the frame body Thus, the characteristic impedance of the line conductor is close to a desired value, and the semiconductor device exhibits good electrical characteristics.

本発明の半導体素子収納用パッケージについて以下に詳細に説明する。図１は本発明の半導体素子収納用パッケージの実施の形態の一例を示す断面図であり、図２は図１の平面図である。図１および図２において、１は基体、２は枠体、３は蓋体、４は回路基板を示す。   The semiconductor element storage package of the present invention will be described in detail below. FIG. 1 is a sectional view showing an example of an embodiment of a package for housing a semiconductor element of the present invention, and FIG. 2 is a plan view of FIG. 1 and 2, 1 is a base, 2 is a frame, 3 is a lid, and 4 is a circuit board.

そして、本発明の半導体素子収納用パッケージは、上側主面に、半導体素子５およびコンデンサ10が実装されている回路基板４を載置するための載置部１ａを有する基体１を具備しており、基体１は、上側主面のコンデンサ10の直下の部位に平面視でコンデンサ10およびその実装部を含む大きさの凹部が形成されている。   The package for housing a semiconductor element of the present invention includes a base body 1 having a mounting portion 1a for mounting a circuit board 4 on which a semiconductor element 5 and a capacitor 10 are mounted on the upper main surface. The base body 1 is formed with a recess having a size including the capacitor 10 and its mounting portion in a plan view at a portion immediately below the capacitor 10 on the upper main surface.

基体１は、Ｆｅ−Ｎｉ−Ｃｏ合金等の金属やＣｕ−Ｗの焼結材等の金属から成り、四角板状体のものである。基体１は、Ｆｅ−Ｎｉ−Ｃｏ合金等やＣｕ−Ｗの焼結材等のインゴットに圧延加工や打ち抜き加工等の従来周知の金属加工法、または切削加工等を施すことによって、所定の形状に製作される。基体１の上側主面のほぼ中央部には、ＩＣ，ＬＳＩ，ＬＤ，ＰＤ等の半導体素子５や高周波用の回路基板４を載置するための載置部１ａが形成されており、この載置部１ａに半導体素子５や回路基板４が、例えばＡｇろう，Ａｇ−Ｃｕろう等のろう材やＡｕ−Ｓｎ半田，Ｐｂ−Ｓｎ半田等の半田、樹脂系接着剤によって接着固定される。   The substrate 1 is made of a metal such as an Fe—Ni—Co alloy or a metal such as a sintered material of Cu—W, and has a rectangular plate shape. The base body 1 is formed into a predetermined shape by subjecting an ingot such as a Fe—Ni—Co alloy or the like or a sintered material of Cu—W to a conventionally known metal processing method such as rolling or punching or cutting. Produced. A mounting portion 1a for mounting a semiconductor element 5 such as an IC, LSI, LD, PD or the like and a high frequency circuit board 4 is formed at a substantially central portion of the upper main surface of the base 1. The semiconductor element 5 and the circuit board 4 are bonded and fixed to the mounting portion 1a with, for example, a brazing material such as Ag brazing or Ag—Cu brazing, solder such as Au—Sn solder or Pb—Sn solder, or a resin adhesive.

半導体素子５の電極は、回路基板４の上面に被着形成されている第１の線路導体４ａおよび第２の線路導体４ｂにそれぞれボンディングワイヤ６ａ，６ｂを介して電気的に接続される。   The electrodes of the semiconductor element 5 are electrically connected to the first line conductor 4a and the second line conductor 4b deposited on the upper surface of the circuit board 4 via bonding wires 6a and 6b, respectively.

回路基板４は、例えばアルミナ（Ａｌ２Ｏ３）質セラミックスや窒化アルミニウム（ＡｌＮ）質セラミックスから成り、アルミナ質セラミックスから成る場合、以下のようにして作製される。まず、アルミナ（Ａｌ２Ｏ３），酸化珪素（ＳｉＯ２），酸化カルシウム（ＣａＯ），酸化マグネシウム（ＭｇＯ）等の原料粉末に適当な有機バインダや可塑剤，分散剤，溶剤等を添加混合して泥漿状となす。これを従来周知のドクターブレード法等でシート状となすことによってセラミックグリーンシートを得、これを切断加工したものを積層するか、または、Ａｌ２Ｏ３，ＳｉＯ２，ＣａＯ，ＭｇＯ等の原料粉末に適当な可塑剤や分散剤，溶剤等を添加混合して金型に充填し、プレス成型することによって、所定形状のセラミック成形体を得る。しかる後、このセラミック成形体に適当な打ち抜き加工を施して得た四角平板状等の板体の上面に、第１の線路導体４ａ，第２の線路導体４ｂおよび同一面接地導体８となる金属ペーストを印刷塗布するとともに側面に面間接続導体９となる金属ペーストを印刷塗布し、還元雰囲気中で約1600℃の温度で焼成することによって製作される。第１の線路導体４ａ，第２の線路導体４ｂ，同一面接地導体８および面間接続導体９となる金属ペーストはタングステン（Ｗ），モリブデン（Ｍｏ），マンガン（Ｍｎ）等の高融点金属粉末に適当な有機バインダや添加剤，溶剤等を添加混合してペースト状となしたものから成る。 The circuit board 4 is made of, for example, alumina (Al 2 O 3 ) ceramics or aluminum nitride (AlN) ceramics. When the circuit board 4 is made of alumina ceramics, the circuit board 4 is manufactured as follows. First, an appropriate organic binder, plasticizer, dispersant, solvent, etc. are added to and mixed with raw material powders such as alumina (Al 2 O 3 ), silicon oxide (SiO 2 ), calcium oxide (CaO), and magnesium oxide (MgO). To make a mud. A ceramic green sheet is obtained by making this into a sheet by a conventionally known doctor blade method or the like, and the cut green powder is laminated, or raw material powder such as Al 2 O 3 , SiO 2 , CaO, MgO An appropriate plasticizer, dispersant, solvent, etc. are added to and mixed into a mold and press-molded to obtain a ceramic molded body having a predetermined shape. Thereafter, a metal that becomes the first line conductor 4a, the second line conductor 4b, and the coplanar ground conductor 8 is formed on the upper surface of a square plate or the like obtained by performing an appropriate punching process on the ceramic molded body. The paste is printed and applied, and a metal paste serving as the inter-surface connection conductor 9 is printed on the side surface and fired at a temperature of about 1600 ° C. in a reducing atmosphere. The metal paste used as the first line conductor 4a, the second line conductor 4b, the ground contact conductor 8 and the inter-surface connection conductor 9 is a refractory metal powder such as tungsten (W), molybdenum (Mo), manganese (Mn), etc. A suitable organic binder, additive, solvent and the like are added and mixed to form a paste.

なお、第１の線路導体４ａ，第２の線路導体４ｂおよび同一面接地導体８、面間接続導体９は薄膜形成法によって形成されていても良く、その場合、第１の線路導体４ａ，第２の線路導体４ｂおよび同一面接地導体８は、窒化タンタル（Ｔａ２Ｎ），ニクロム（Ｎｉ−Ｃｒ）合金，チタン（Ｔｉ），パラジウム（Ｐｄ），白金（Ｐｔ），金（Ａｕ）等から形成され、セラミックグリーンシートを焼成した後に従来周知の真空蒸着成膜法等によって形成される。 The first line conductor 4a, the second line conductor 4b, the same-surface ground conductor 8, and the inter-surface connection conductor 9 may be formed by a thin film forming method. In this case, the first line conductor 4a, The line conductor 4b and the same-surface ground conductor 8 are made of tantalum nitride (Ta 2 N), nichrome (Ni—Cr) alloy, titanium (Ti), palladium (Pd), platinum (Pt), gold (Au), or the like. After the ceramic green sheet is formed, it is formed by a conventionally known vacuum deposition method or the like.

また、基体１の上側主面の外周部には載置部１ａを囲むようにして枠体２が接合されており、枠体２は、その内側に半導体素子５を収容する空所を形成する。この枠体２は、基体１と同様にＦｅ−Ｎｉ−Ｃｏ合金やＣｕ−Ｗの焼結材等から成り、基体１と一体成形されるか、または基体１にＡｇろう等のろう材を介してろう付けされるか、またはシーム溶接法等の溶接法により接合されることによって、基体１の上側主面の外周部に設けられる。   Further, a frame body 2 is joined to the outer peripheral portion of the upper main surface of the base body 1 so as to surround the mounting portion 1a, and the frame body 2 forms a space for housing the semiconductor element 5 therein. The frame 2 is made of a Fe—Ni—Co alloy, a Cu—W sintered material, or the like in the same manner as the base 1 and is formed integrally with the base 1 or via a brazing material such as Ag brazing. It is provided on the outer peripheral portion of the upper main surface of the base 1 by being brazed or joined by a welding method such as a seam welding method.

なお、枠体２は上記のような金属の他にセラミックス等の誘電体材料から成っていてもよく、その表面にメタライズ層等の導体層が形成されていてもよい。   The frame 2 may be made of a dielectric material such as ceramics in addition to the metal as described above, and a conductor layer such as a metallized layer may be formed on the surface thereof.

また、外部より半導体素子５に駆動信号等を入力させる入出力端子が設けられる。このような入出力端子は、例えばまず、枠体２の側面に中心導体，誘電体，外部導体が同心円状に配置された同軸構造のガラスビーズ11が嵌着される貫通孔２ａを形成し、貫通孔２ａ内にガラスビーズ11を嵌め込むとともにＡｕ−Ｓｎ半田やＰｂ−Ｓｎ半田等の封着材を貫通孔２ａとの隙間に挿入し、しかる後、封着材を加熱して溶融させ、溶融した封着材を毛細管現象によりガラスビーズ11と貫通孔２ａの内壁との隙間に充填することによって、ガラスビーズ11が貫通孔２ａ内に半田等の封着材を介して嵌着接合される。   In addition, an input / output terminal for inputting a drive signal or the like to the semiconductor element 5 from the outside is provided. For example, such an input / output terminal first forms a through-hole 2a in which a glass bead 11 having a coaxial structure in which a central conductor, a dielectric, and an outer conductor are concentrically arranged is fitted on the side surface of the frame 2, Glass beads 11 are fitted into the through-hole 2a and a sealing material such as Au-Sn solder or Pb-Sn solder is inserted into the gap with the through-hole 2a, and then the sealing material is heated and melted. By filling the melted sealing material into the gap between the glass beads 11 and the inner walls of the through holes 2a by capillary action, the glass beads 11 are fitted and joined into the through holes 2a via a sealing material such as solder. .

ガラスビーズ11は、Ｆｅ−Ｎｉ−Ｃｏ合金等の金属から成る円筒形等の筒状の外周導体の内側にガラス等の絶縁体が充填され、さらに、中心軸にＦｅ−Ｎｉ−Ｃｏ合金等の金属から成る中心導体が固定される。そして、この中心導体は、半田等から成る導電性接着材を介して回路基板４の第１の線路導体４ａに電気的に接続される。この中心導体および筒状の外周導体に同軸ケーブルが装着されることによって、半導体素子収納用パッケージの内部に収納された半導体素子５が中心導体を介して外部電気回路に電気的に接続されることとなる。   The glass beads 11 are filled with an insulator such as glass on the inside of a cylindrical outer conductor such as a cylindrical shape made of a metal such as an Fe—Ni—Co alloy, and the central axis is made of an Fe—Ni—Co alloy or the like. A central conductor made of metal is fixed. The central conductor is electrically connected to the first line conductor 4a of the circuit board 4 through a conductive adhesive made of solder or the like. By attaching a coaxial cable to the center conductor and the cylindrical outer conductor, the semiconductor element 5 housed in the semiconductor element housing package is electrically connected to the external electric circuit via the center conductor. It becomes.

また、半導体素子５の電極と回路基板４の上面に形成された第１の線路導体４ａおよび第２の線路導体４ｂとがボンディングワイヤ６ａ，６ｂにより電気的に接続される。   Further, the electrodes of the semiconductor element 5 and the first line conductor 4a and the second line conductor 4b formed on the upper surface of the circuit board 4 are electrically connected by bonding wires 6a and 6b.

そして、本発明の半導体素子収納用パッケージにおける基体１においては、第２の線路導体４ｂに挿入されているコンデンサ10の直下の部位に回路基板４を介して平面視でコンデンサ10およびその実装部を含む大きさの凹部12が形成されている。   And in the base | substrate 1 in the package for semiconductor element accommodation of this invention, the capacitor | condenser 10 and its mounting part are planarly seen via the circuit board 4 in the site | part just under the capacitor | condenser 10 inserted in the 2nd line conductor 4b. A recess 12 having a size including the recess 12 is formed.

コンデンサ10は、例えばチップコンデンサを第２の線路導体４ｂの終端部に半田等の導電性接着材を介して第２の線路導体４ｂの途中に挿入するように接続される。   The capacitor 10 is connected, for example, so that a chip capacitor is inserted in the middle of the second line conductor 4b via a conductive adhesive such as solder at the end of the second line conductor 4b.

コンデンサ10は、十分な容量を得るためにサイズが大きく、通常は第２の線路導体４ｂの幅よりも幅広になる。従って、コンデンサ10が挿入されて接合される部位の第２の線路導体４ｂの幅は、第２の線路導体４ｂのコンデンサ10の近辺でコンデンサ10に向かって漸次広くなるように形成され、コンデンサ10が接合される部位の幅は、コンデンサ10の実装時の位置決め精度や実装後の接合強度を確保するためにコンデンサ10の幅の110〜180%とされる。   The capacitor 10 is large in size to obtain a sufficient capacity, and is usually wider than the width of the second line conductor 4b. Accordingly, the width of the second line conductor 4b at the portion where the capacitor 10 is inserted and joined is formed so as to gradually increase toward the capacitor 10 in the vicinity of the capacitor 10 of the second line conductor 4b. The width of the portion to be bonded is 110 to 180% of the width of the capacitor 10 in order to ensure the positioning accuracy when mounting the capacitor 10 and the bonding strength after mounting.

コンデンサ10が実装される部位の幅がコンデンサ10の幅の180％を越えると、コンデンサ10の実装時の位置決め精度に対して必要以上のものとなるとともに、第２の線路導体４ｂの残部の幅との差が許容範囲以上に大きくなり、電気信号の反射係数が大きくなり過ぎる傾向がある。また110％未満とすると、コンデンサ10の実装時の位置ズレを許容できにくくなり、位置ズレが発生した際に電気信号の反射係数が大きくなるとともに、コンデンサ10の回路基板４への接合強度が弱くなり、コンデンサ10が衝撃により外れたりする傾向がある。   If the width of the portion where the capacitor 10 is mounted exceeds 180% of the width of the capacitor 10, the positioning accuracy when mounting the capacitor 10 becomes more than necessary, and the width of the remaining portion of the second line conductor 4b. And the difference between and becomes larger than the allowable range, and the reflection coefficient of the electric signal tends to be too large. If it is less than 110%, it is difficult to tolerate the positional deviation when the capacitor 10 is mounted, the reflection coefficient of the electric signal becomes large when the positional deviation occurs, and the bonding strength of the capacitor 10 to the circuit board 4 is weak. Therefore, the capacitor 10 tends to come off due to an impact.

コンデンサ10の電極部分と上記幅広の第２の線路導体４ｂとの接続部から成る実装部およびコンデンサ10が第２の線路導体４ｂの残部の幅より広いため、この部分と基体１との間において第２の線路導体４ｂの残部と基体１との間より大きな容量成分をもつことになるが、凹部12が形成されているために、コンデンサ10の実装部およびコンデンサ10の部分における容量成分を低減することができ、第2の線路導体４ｂの残部の特性インピーダンス値と同程度とできる。   Since the mounting portion composed of the connection portion between the electrode portion of the capacitor 10 and the wide second line conductor 4b and the capacitor 10 are wider than the width of the remaining portion of the second line conductor 4b, between this portion and the base 1 Although it has a larger capacitance component between the remaining portion of the second line conductor 4b and the base body 1, since the recess 12 is formed, the capacitance component in the mounting portion of the capacitor 10 and the portion of the capacitor 10 is reduced. And the same characteristic impedance value as the remaining portion of the second line conductor 4b.

なお、容量成分の低減は、回路基板４の厚みを厚くすることによることも可能であるが、回路基板４の厚みが高周波信号波長の１／４以上になると、高次モードによる共振が発生するため回路基板４の厚みを上げることは好ましくない。また、容量成分を少なくするために、例えば回路基板４の下面に凹部を設けることも可能であるが、上述のように回路基板４は波長の１／４以下の厚みとすることが好ましく、そのために基板４の厚みを厚くすることができないので、回路基板４に凹部を設けると、凹部付近の回路基板４の強度が不足し、回路基板４にクラックなどが発生する。このため、凹部12は基体１上に形成することが好ましい。   The capacitance component can be reduced by increasing the thickness of the circuit board 4, but when the thickness of the circuit board 4 becomes ¼ or more of the high-frequency signal wavelength, resonance due to a higher-order mode occurs. Therefore, it is not preferable to increase the thickness of the circuit board 4. In order to reduce the capacitance component, for example, a recess can be provided on the lower surface of the circuit board 4. However, as described above, the circuit board 4 preferably has a thickness of ¼ or less of the wavelength. Since the thickness of the substrate 4 cannot be increased, if the circuit board 4 is provided with a recess, the strength of the circuit board 4 near the recess is insufficient, and a crack or the like occurs in the circuit board 4. Therefore, the recess 12 is preferably formed on the substrate 1.

また、コンデンサ10の実装部とコンデンサ10との部分における容量成分を少なくし、第2の線路導体４ｂの残部の容量成分と同程度とするために、平面視における凹部12の面積が、コンデンサ10およびその実装部の平面視における面積の160〜250％であるのが好ましく、さらに、凹部12の深さが0.2〜1.5ｍｍとするのがより好ましい。   Further, in order to reduce the capacitance component in the portion between the mounting portion of the capacitor 10 and the capacitor 10 and to have the same level as the capacitance component of the remaining portion of the second line conductor 4b, the area of the recess 12 in plan view is And it is preferable that it is 160 to 250% of the area in planar view of the mounting part, and it is more preferable that the depth of the recessed part 12 shall be 0.2 to 1.5 mm.

凹部12の面積が160%未満では、凹部12によって得られる容量成分の低減の効果が弱く、コンデンサ10とコンデンサ10の実装部とによる容量成分を打ち消しあうことができず、第２の線路導体４ｂのコンデンサ10およびその実装部の特性インピーダンス値が第２の線路導体４ｂの残部の特性インピーダンスから減少する方向に変動し、高抵抗体部７が所望の終端特性からずれやすくなる。一方、250%を超えると、第２の線路導体４ｂのコンデンサ10とコンデンサ10の実装部以外の範囲にも広く凹部12の範囲がおよび、コンデンサ10とコンデンサ10の実装部との部分に生じる容量成分よりも凹部12の容量低減効果が強く、誘導成分が大きくなり、第２の線路導体４ｂの特性インピーダンス値が増大する方向に変動し、高抵抗体部７が所望の終端特性からずれやすくなる。   If the area of the recess 12 is less than 160%, the effect of reducing the capacitance component obtained by the recess 12 is weak, and the capacitance component due to the capacitor 10 and the mounting portion of the capacitor 10 cannot be canceled out, and the second line conductor 4b. The characteristic impedance value of the capacitor 10 and its mounting portion fluctuates in a direction that decreases from the characteristic impedance of the remaining portion of the second line conductor 4b, and the high resistance portion 7 is likely to deviate from the desired termination characteristic. On the other hand, if it exceeds 250%, the range of the recess 12 is wide in the range other than the capacitor 10 and the capacitor 10 mounting portion of the second line conductor 4b, and the capacitance generated in the portion of the capacitor 10 and the capacitor 10 mounting portion. The capacity reduction effect of the recess 12 is stronger than the component, the inductive component is increased, the characteristic impedance value of the second line conductor 4b is increased, and the high resistance portion 7 is likely to deviate from the desired termination characteristic. .

なお、凹部12の長さ方向（第2の線路導体４ｂに沿う方向）はコンデンサ10の長さの120〜160％程度とし、幅方向（第2の線路導体４ｂと直角の方向）はコンデンサ10の幅の120〜160％程度とする範囲内で、その面積がコンデンサの平面視における面積の160〜250％となるように選択するのが好ましい。   The length direction of the recess 12 (the direction along the second line conductor 4b) is about 120 to 160% of the length of the capacitor 10, and the width direction (the direction perpendicular to the second line conductor 4b) is the capacitor 10. In the range of about 120 to 160% of the width of the capacitor, the area is preferably selected to be 160 to 250% of the area of the capacitor in plan view.

また、凹部12の深さが0.2ｍｍ未満であると、コンデンサ10と凹部12の底面までの距離が近くなり、コンデンサ10およびその実装部の容量成分を低減しきれず第２の線路導体４ｂの残部の特性インピーダンスから減少する方向になりやすくなり、1.5ｍｍを超えると、コンデンサ10と凹部12の底面までの距離が遠くなりすぎ、コンデンサ10およびその実装部の容量成分を低減しすぎて、第２の線路導体４ｂの残部の特性インピーダンスから増大する方向になりやすくなる。 If the depth of the concave portion 12 is less than 0.2 mm, the distance between the capacitor 10 and the bottom surface of the concave portion 12 becomes short, and the capacity component of the capacitor 10 and its mounting portion cannot be reduced, and the remaining portion of the second line conductor 4b. it tends in the direction to decrease the characteristic impedance, it exceeds 1.5 mm, the distance to the bottom surface of the capacitor 10 and the recess 12 is too far, too reduce the capacitance component of the capacitor 10 and its mounting portion, the This tends to increase from the characteristic impedance of the remaining portion of the second line conductor 4b.

凹部12の底面の形状は図６（ａ）に示すように平坦であるのが一般的であるが、凹部12の底面の各部の深さが上述の0.2〜1.5ｍｍの深さの範囲内で図６（ｂ）のように外周を凹ませた凹凸形状にする。 The shape of the bottom surface of the recess 12 is generally in the range of flat as shown in FIG. 6 (a), the depth of each portion of the bottom surface of the recess 12 is within the depth of 0.2 to 1.5 mm above to concavo-convex shape by recessing the outer circumference as shown in FIG. 6 (b).

図６（ｂ）に示すように、凹部12の底面を凹凸にし、凹部12の外周を凹ませ（凹部12の深さを深くし）、中央部を凸形状（凹部12の深さを浅くなるよう）にすることにより、コンデンサ10の実装部と基体１との間で容量成分が大きくなるのを抑制できる。これはコンデンサ10の実装部分で、コンデンサ10の端子材の厚みやコンデンサ10を実装する際に使用する半田のメニスカスが生じる分、線路幅が広くなって容量成分が大きくなるとともに、コンデンサ10の端子材や半田の厚みの分、上下方向にも線路導体の厚みが厚くなったように見え、この厚くなっているコンデンサ10の実装部の側面と基体１との間で電気力線が生じて容量成分が生じるためである。従って、凹部12の底面を図６（ｂ）に示すような形状にすることにより、コンデンサ10の実装部に対向する凹部12の底面の外周が凹んでいるため、コンデンサ10の実装部と凹部12との間の容量成分の低減が可能となる。 As shown in FIG. 6 (b), the irregularities of the bottom surface of the recess 12, Hekomase the outer periphery of the recess 12 (to the depth of the recess 12) shallower the depth of the convex shape (recess 12 a central portion By doing so, it is possible to suppress an increase in the capacitance component between the mounting portion of the capacitor 10 and the base 1. This is the part where the capacitor 10 is mounted, the thickness of the terminal material of the capacitor 10 and the meniscus of the solder used when mounting the capacitor 10 are generated, the line width becomes wider and the capacitance component increases, and the terminal of the capacitor 10 It appears that the thickness of the line conductor has increased in the vertical direction as much as the thickness of the material and solder, and electric lines of force are generated between the side surface of the mounting portion of the thick capacitor 10 and the base body 1 to generate capacitance. This is because components are produced. What slave, by the bottom surface of the recess 12 in the shape as shown in FIG. 6 (b), since the recessed outer peripheral of the bottom surface of the recess 12 facing the mounting portion of the capacitor 10, and the mounting portion of the capacitor 10 It is possible to reduce the capacitance component between the concave portion 12 and the concave portion 12.

また凹部12は基体１に切削加工などにより、一体に形成するのが好ましいが、図５のように基体１に凹部12となる貫通孔を形成し、その後、貫通孔の基体１の下面側の開口を封止部品13で塞ぎ、凹部12としても構わない。その際、封止部品13は、基体１と同じ材質の金属板で形成し、その周囲にＡｕ−Ｓｎ半田やＰｂ−Ｓｎ半田等の封着材を挟んで貫通孔に挿入し、しかる後、封着材を加熱して溶融させ、封止部品13が貫通孔内に半田等の封着材を介して嵌着接合され凹部12を形成する方法でも構わない。これにより、凹部深さ寸法が調整しやすくなるため、電気特性を確認しながら容量成分を低減させるように凹部深さを調整して凹部深さを決定することが出来る。   The recess 12 is preferably formed integrally with the base body 1 by cutting or the like. However, as shown in FIG. 5, a through-hole that becomes the recess 12 is formed in the base body 1 and then the through-hole on the lower surface side of the base body 1 is formed. The opening may be closed by the sealing component 13 to form the recess 12. At that time, the sealing component 13 is formed of a metal plate made of the same material as that of the base 1, and is inserted into a through hole with a sealing material such as Au-Sn solder or Pb-Sn solder around it, and then, Alternatively, the sealing material 13 may be heated and melted, and the sealing component 13 may be fitted and joined into the through hole via a sealing material such as solder to form the recess 12. Thereby, since the recess depth dimension can be easily adjusted, the recess depth can be determined by adjusting the recess depth so as to reduce the capacitance component while checking the electrical characteristics.

また、回路基板４の厚みは、第２の線路導体４ｂを伝送する高周波信号の波長の１／４より厚いと高次モードが発生し、第２の線路導体４ｂを伝送する高周波信号の反射係数が増大するので、第２の線路導体４ｂを伝送する高周波信号の波長の１／４より薄くするのが好ましい。回路基板４を１／４波長より薄くすると、回路基板４の上面に形成される第２の線路導体４ｂやコンデンサ10と基体１との距離が接近して、コンデンサ10の実装部とコンデンサ10との部分における容量成分がより大きくなる傾向を有するが、基体１に凹部12が形成されていることから、容量成分を抑制することができる。   Further, when the thickness of the circuit board 4 is thicker than 1/4 of the wavelength of the high-frequency signal transmitted through the second line conductor 4b, a higher-order mode occurs, and the reflection coefficient of the high-frequency signal transmitted through the second line conductor 4b. Therefore, it is preferable to make it thinner than ¼ of the wavelength of the high-frequency signal transmitted through the second line conductor 4b. When the circuit board 4 is made thinner than a quarter wavelength, the distance between the second line conductor 4b and the capacitor 10 formed on the upper surface of the circuit board 4 and the base body 1 approaches, and the mounting portion of the capacitor 10 and the capacitor 10 However, since the concave portion 12 is formed in the substrate 1, the capacitance component can be suppressed.

このように、本発明の半導体素子収納用パッケージによれば、コンデンサ10の実装部とコンデンサ10とが基体１との間で発生する容量成分を凹部12にて低減させることができる。その結果、10ＧＨｚ以上の高周波信号用の半導体素子収納用パッケージにおいても良好な高周波特性が実現できる。   Thus, according to the package for housing a semiconductor element of the present invention, the capacitance component generated between the mounting portion of the capacitor 10 and the capacitor 10 between the base 1 can be reduced by the recess 12. As a result, good high frequency characteristics can be realized even in a package for housing semiconductor elements for high frequency signals of 10 GHz or higher.

また、本発明の半導体装置は、上記本発明の半導体素子収納用パッケージと、載置部１ａに載置され、回路基板４の回路配線に電気的に接続された半導体素子５と、基体１の外周部に載置部１ａを囲むように接合された枠体２と、枠体２の上面に枠体２の内側を塞ぐように接合された蓋体３とを具備しており、このことから、回路基板の上側主面に形成される線路導体の特性インピーダンスが所望の値に近いものとなり、良好な電気特性を示す半導体装置とできる。   Further, the semiconductor device of the present invention includes the semiconductor element storage package of the present invention, the semiconductor element 5 mounted on the mounting portion 1 a and electrically connected to the circuit wiring of the circuit board 4, and the substrate 1. The frame body 2 joined so that the mounting part 1a may be enclosed in an outer peripheral part, and the cover body 3 joined so that the inner side of the frame body 2 might be plugged up on the upper surface of the frame body 2, From this, The characteristic impedance of the line conductor formed on the upper main surface of the circuit board becomes close to a desired value, and a semiconductor device exhibiting good electrical characteristics can be obtained.

本発明および比較用の半導体素子収納用パッケージの回路基板４，104を以下のように構成することとし、高周波３次元構造シミュレータ（アンソフト社製HFSS（High Frequency Structure Simulator））を用いて１ＧＨｚ〜15ＧＨｚの反射係数Ｓ11をシミュレーションにより評価した。   The circuit boards 4 and 104 of the present invention and the comparative semiconductor element storage package are configured as follows, and a high-frequency three-dimensional structure simulator (HFSS (High Frequency Structure Simulator manufactured by Ansoft)) is used from 1 GHz to The reflection coefficient S11 of 15 GHz was evaluated by simulation.

まず、回路基板４は、比誘電率が9.6のアルミナセラミックスからなる縦６ｍｍ×横2.05ｍｍ×厚さ１ｍｍの基板とし、その上側主面に、幅0.54ｍｍ×長さ5.8ｍｍ×厚さ0.002ｍｍの第２の線路導体４ｂを配置した。なお、第２の線路導体４ｂの高抵抗体部７に接続される終端から1.9ｍｍおよび3.1ｍｍのコンデンサ10が挿入接続される部位は、線路導体４ｂが切断されており、その切断された第２の線路導体４ｂの端の幅は1.55ｍｍ、そしてこれらの端から0.9ｍｍの長さ方向に沿って第２の線路導体４ｂの幅は1.55ｍｍから0.54ｍｍの範囲で漸次幅が変化するようにした。   First, the circuit board 4 is a substrate made of alumina ceramics having a relative dielectric constant of 9.6, length 6 mm × width 2.05 mm × thickness 1 mm, and its upper main surface has a width 0.54 mm × length 5.8 mm × thickness 0.002 mm. The second line conductor 4b was arranged. It should be noted that the line conductor 4b is cut at the portion where the 1.9 mm and 3.1 mm capacitors 10 are inserted and connected from the end connected to the high resistance portion 7 of the second line conductor 4b. The width of the end of the second line conductor 4b is 1.55 mm, and the width of the second line conductor 4b gradually changes in the range of 1.55 mm to 0.54 mm along the length direction of 0.9 mm from these ends. I made it.

次に、第２の線路導体４ｂにコンデンサ10として、幅1.25ｍｍ×長さ２ｍｍ×厚さ1.25ｍｍのチップコンデンサ10を第２の線路導体４ｂの上記切断部位に挿入接続されるように配置した。   Next, a chip capacitor 10 having a width of 1.25 mm, a length of 2 mm, and a thickness of 1.25 mm is disposed as a capacitor 10 on the second line conductor 4b so as to be inserted and connected to the cut portion of the second line conductor 4b. .

また、縦10ｍｍ×横５ｍｍ×厚さ５ｍｍの金属から成る基体１のチップコンデンサ10の直下となる部位に凹部12を配置した。凹部12の面積および深さは、表１に示す10通りとした。   Further, a recess 12 was disposed in a portion of the substrate 1 made of a metal having a length of 10 mm × width of 5 mm × thickness of 5 mm immediately below the chip capacitor 10. The area and depth of the recess 12 were 10 types shown in Table 1.

各試料における上記周波数範囲のうちで、最も悪い反射係数Ｓ11の値を表１に示す。

Figure 0004377768
Table 1 shows the worst value of the reflection coefficient S11 in the frequency range of each sample.
Figure 0004377768

表１より、凹部12が形成されていない比較用の試料No.１は反射係数Ｓ11が−10ｄＢ以上となり、本発明の半導体素子収納用パッケージにおいては、コンデンサ面積比欄に示される平面視における凹部12の面積がコンデンサ10およびその実装部の面積の160〜250％で、かつ、その深さが0.2〜1.5ｍｍの範囲である試料No.２，３，４，７，８，９については、反射係数Ｓ11が実際に半導体装置が正常に動作する−15ｄＢ以下と良好な特性が得られることが分かった。これに対し、試料No.５，６，10においては、反射係数Ｓ11が−15ｄＢを超えて大きいことが分かった。   From Table 1, the comparative sample No. 1 in which the recess 12 is not formed has a reflection coefficient S11 of −10 dB or more. In the semiconductor element storage package of the present invention, the recess in the plan view shown in the capacitor area ratio column. Sample Nos. 2, 3, 4, 7, 8, and 9 in which the area of 12 is 160 to 250% of the area of the capacitor 10 and its mounting portion and the depth is in the range of 0.2 to 1.5 mm, It has been found that the reflection coefficient S11 is as good as -15 dB or less at which the semiconductor device actually operates normally. On the other hand, in samples Nos. 5, 6, and 10, it was found that the reflection coefficient S11 exceeded -15 dB.

なお、本発明は、上述の実施の形態の一例に限定されるものではなく、本発明の要旨を逸脱しない範囲内であれば種々の変更は可能である。例えば、回路基板４は、第１の線路導体４ａを有する入力用の回路基板４と第２の線路導体４ｂを有する終端用の回路基板４とに二分されている形態について説明したが、これらが一体となった回路基板４としてもよい。   Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. For example, the circuit board 4 has been described as being divided into an input circuit board 4 having a first line conductor 4a and a termination circuit board 4 having a second line conductor 4b. The circuit board 4 may be integrated.

本発明の半導体素子収納用パッケージおよび半導体装置の実施の形態の一例を示す断面図である。It is sectional drawing which shows an example of embodiment of the package for semiconductor element accommodation of this invention, and a semiconductor device. 図１の半導体素子収納用パッケージおよび半導体装置の平面図である。FIG. 2 is a plan view of the semiconductor element storage package and the semiconductor device of FIG. 1. 従来の半導体素子収納用パッケージおよび半導体装置の例を示す断面図である。It is sectional drawing which shows the example of the conventional package for semiconductor element accommodation, and a semiconductor device. 図３の半導体素子収納用パッケージおよび半導体装置の平面図である。FIG. 4 is a plan view of the semiconductor element storage package and the semiconductor device of FIG. 3. 本発明の半導体素子収納用パッケージおよび半導体装置の実施の形態の他の例を示す断面図である。It is sectional drawing which shows the other example of embodiment of the semiconductor element accommodation package and semiconductor device of this invention. 凹部の断面形状の例を示す図である。It is a figure which shows the example of the cross-sectional shape of a recessed part.

符号の説明Explanation of symbols

１・・・・・・・基体
１ａ・・・・・・載置部
２・・・・・・・枠体
３・・・・・・・蓋体
４・・・・・・・回路基板
４ａ・・・・・・第１の線路導体
４ｂ・・・・・・第２の線路導体
５・・・・・・・半導体素子
６ａ，６ｂ・・・ボンディングワイヤ
７・・・・・・・高抵抗体部
８・・・・・・・同一面接地導体
９・・・・・・・面間接続導体
10・・・・・・・コンデンサ
11・・・・・・・ガラスビーズ
12・・・・・・・凹部
13・・・・・・・封止部品 DESCRIPTION OF SYMBOLS 1 ... Base | substrate 1a ..... Placement part 2 ..... Frame body 3 ..... Lid body 4 ..... Circuit board 4a ······· First line conductor 4b ··········· Second line conductor 5 ········· Semiconductor elements 6a and 6b ··· Bonding wires 7 ····· High Resistor section 8 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Ground conductor on the same plane 9 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Connector between planes
10 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Capacitor
11 .... Glass beads
12 ...
13 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Sealing parts

Claims (3)

上側主面に、半導体素子およびコンデンサが実装されている回路基板を載置するための載置部を有する基体を具備している半導体素子収納用パッケージにおいて、前記基体は、上側主面の前記コンデンサの直下の部位に平面視で前記コンデンサおよびその実装部を含む大きさの凹部が形成されており、該凹部の底面は、該底面の外周を凹ませて中央部を凸形状とした凹凸であることを特徴とした半導体素子収納用パッケージ。 In the semiconductor element storage package comprising a base having a mounting portion for mounting a circuit board on which the semiconductor element and the capacitor are mounted on the upper main surface, the base is the capacitor on the upper main surface A concave portion having a size including the capacitor and its mounting portion is formed in a plan view directly below the bottom surface of the concave portion, and the bottom surface of the concave portion is concave and convex with the outer periphery of the bottom surface being concave and the central portion being convex. A package for housing a semiconductor element. 前記凹部は、平面視における面積が前記コンデンサおよびその実装部の面積の１６０乃至２５０％であることを特徴とする請求項１記載の半導体素子収納用パッケージ。   2. The package for housing a semiconductor element according to claim 1, wherein an area of the concave portion in plan view is 160 to 250% of an area of the capacitor and its mounting portion. 請求項１記載の半導体素子収納用パッケージと、前記載置部に載置され、前記回路基板の回路配線に電気的に接続された前記半導体素子と、前記基体の外周部に前記載置部を囲むように接合された枠体と、前記枠体の上面に枠体の内側を塞ぐように取着された蓋体とを具備していることを特徴とする半導体装置。   The package for housing a semiconductor element according to claim 1, the semiconductor element placed on the placement part and electrically connected to the circuit wiring of the circuit board, and the placement part on the outer periphery of the base. A semiconductor device comprising: a frame body joined so as to surround; and a lid body attached to an upper surface of the frame body so as to close an inside of the frame body.
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