JP2003007901A - Package for storing semiconductor element, and semiconductor device - Google Patents
Package for storing semiconductor element, and semiconductor deviceInfo
- Publication number
- JP2003007901A JP2003007901A JP2001193744A JP2001193744A JP2003007901A JP 2003007901 A JP2003007901 A JP 2003007901A JP 2001193744 A JP2001193744 A JP 2001193744A JP 2001193744 A JP2001193744 A JP 2001193744A JP 2003007901 A JP2003007901 A JP 2003007901A
- Authority
- JP
- Japan
- Prior art keywords
- line conductor
- circuit board
- conductor layer
- semiconductor element
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Non-Reversible Transmitting Devices (AREA)
- Waveguides (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、高周波信号で作動
する半導体素子を収納するための半導体素子収納用パッ
ケージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element housing package for housing a semiconductor element that operates with a high frequency signal.
【０００２】[0002]
【従来の技術】従来、光通信分野で使用されたり、マイ
クロ波帯、ミリ波帯等の高周波信号を用いる各種半導体
素子を収納する半導体素子収納用パッケージ（以下、半
導体パッケージという）には、半導体素子を電気的に接
地するための導体パターンとしての線路導体が設けられ
ている。このような半導体パッケージを図３に断面図で
示す。同図において、２１は基体、２２は金属製の枠
体、２６は回路基板である。2. Description of the Related Art Conventionally, a semiconductor element housing package (hereinafter referred to as a semiconductor package) which is used in the field of optical communication or which houses various semiconductor elements using high frequency signals such as microwave band and millimeter wave band is a semiconductor. A line conductor is provided as a conductor pattern for electrically grounding the element. Such a semiconductor package is shown in cross section in FIG. In the figure, 21 is a base, 22 is a metal frame, and 26 is a circuit board.
【０００３】基体２１は鉄（Ｆｅ）−ニッケル（Ｎｉ）
−コバルト（Ｃｏ）合金や銅（Ｃｕ）−タングステン
（Ｗ）等の金属から成る略四角形状の板状体であり、そ
の上側主面には、ＩＣ，ＬＳＩ，半導体レーザ（Ｌ
Ｄ），フォトダイオード（ＰＤ）等の半導体素子２５と
回路基板２６−Ａ，２６−Ｂが載置固定される。回路基
板２６−Ａ，２６−Ｂの下面には、接地導体層２６ｃ−
Ａ，２６ｃ−Ｂが被着されており、銀（Ａｇ）ろう，Ａ
ｇ−銅（Ｃｕ）ろう等のろう材や半田によって接地導体
層２６ｃと載置部２１ａが強固に接着される。The base 21 is iron (Fe) -nickel (Ni).
-A substantially rectangular plate-like body made of a metal such as cobalt (Co) alloy or copper (Cu) -tungsten (W). The upper main surface thereof has an IC, an LSI, a semiconductor laser (L).
D), the semiconductor element 25 such as a photodiode (PD), and the circuit boards 26-A and 26-B are mounted and fixed. The ground conductor layer 26c- is formed on the lower surfaces of the circuit boards 26-A and 26-B.
A, 26c-B is deposited, and silver (Ag) wax, A
The ground conductor layer 26c and the mounting portion 21a are firmly adhered by a brazing material such as g-copper (Cu) brazing or solder.
【０００４】なお、半導体素子２５は、その電極が回路
基板２６−Ａ，２６−Ｂに被着されている第１の線路導
体２６ａと第２の線路導体２６ｂにそれぞれボンディン
グワイヤ２７ａ，２７ｂを介して電気的に接続されてい
る。The semiconductor element 25 has bonding electrodes 27a and 27b, respectively, on the first line conductor 26a and the second line conductor 26b whose electrodes are attached to the circuit boards 26-A and 26-B, respectively. Are electrically connected.
【０００５】基体２１の上側主面の外周部には載置部２
１ａを囲繞するようにして枠体２２が立設されており、
枠体２２は基体２１とともにその内側に半導体素子２５
を収容する空所を形成する。枠体２２は基体２１と同様
にＦｅ−Ｎｉ−Ｃｏ合金やＣｕ−Ｗの焼結材等から成
り、基体２１と一体成形される、または基体２１にＡｇ
ろう、Ａｇ−Ｃｕろう等のろう材を介してろう付けされ
る、またはシーム溶接法等の溶接法により接合されるこ
とによって基体２１の上側主面の外周部に立設される。The mounting portion 2 is provided on the outer peripheral portion of the upper main surface of the base 21.
A frame 22 is erected so as to surround 1a,
The frame body 22 is formed with the semiconductor element 25 inside the base body 21.
To form a void for housing The frame 22 is made of a sintered material such as a Fe—Ni—Co alloy or Cu—W like the base 21, and is integrally molded with the base 21, or the base 21 is made of Ag.
It is erected on the outer peripheral portion of the upper main surface of the base body 21 by being brazed through a brazing material such as brazing or Ag—Cu brazing or being joined by a welding method such as a seam welding method.
【０００６】枠体２２の側面には同軸コネクタ２３が嵌
着される貫通孔２２ａが形成されており、貫通孔２２ａ
内に同軸コネクタ２３を嵌め込むとともに半田等の封着
材を貫通孔２２ａ内の隙間に挿入し、しかる後、加熱し
て封着材を溶融させ、溶融した封着材を毛細管現象によ
り同軸コネクタ２３と貫通孔２２ａの内面との隙間に充
填させることによって、同軸コネクタ２３が貫通孔２２
ａ内に封着材を介して嵌着接合される。A through hole 22a into which the coaxial connector 23 is fitted is formed on the side surface of the frame body 22, and the through hole 22a is formed.
The coaxial connector 23 is fitted therein, and a sealing material such as solder is inserted into the gap in the through hole 22a. Thereafter, the sealing material is melted by heating, and the melted sealing material is caused by the capillary phenomenon by the coaxial connector. 23 and the inner surface of the through hole 22 a are filled with the coaxial connector 23 so that the through hole 22 is formed.
It is fitted and joined in a through a sealing material.
【０００７】同軸コネクタ２３は、中心軸部分に信号線
路としてＦｅ−Ｎｉ−Ｃｏ合金等の金属から成る棒状の
中心導体２３ａが固定されている。中心導体２３ａが半
田等から成る導電性接着材を介して回路基板２６−Ａの
第１の線路導体２６ａに電気的に接続される。この同軸
コネクタ２３には、外部電気回路（図示せず）に接続さ
れた同軸ケーブル（図示せず）が装着されることによっ
て、内部に収納された半導体素子２５が同軸コネクタ２
３の中心導体２３ａを介して外部電気回路に電気的に接
続されることとなる。In the coaxial connector 23, a rod-shaped central conductor 23a made of a metal such as Fe-Ni-Co alloy is fixed to the central axis portion as a signal line. The center conductor 23a is electrically connected to the first line conductor 26a of the circuit board 26-A via a conductive adhesive material such as solder. A coaxial cable (not shown) connected to an external electric circuit (not shown) is attached to the coaxial connector 23 so that the semiconductor element 25 housed inside is coaxially connected to the coaxial connector 2
It will be electrically connected to an external electric circuit through the central conductor 23a of No. 3.
【０００８】第２の線路導体２６ｂは、図４に要部拡大
平面図を示すように、回路基板２６−Ｂの第２の線路導
体２６ｂの延長部の端面に設けられた導体層２６ｄを介
して、接地導体層２６ｃ−Ｂに電気的に接続される。第
２の線路導体２６ｂには高抵抗部２８が設けられてい
る。この高抵抗部２８は、第２の線路導体２６ｂを流れ
て接地導体層２６ｃ−Ｂに接地される、高周波信号成分
を含む終端用信号を、電気エネルギーから熱エネルギー
に変換し、接地導体層２６ｃ−Ｂからの終端用信号の反
射によるノイズを抑制して、電気的に接地するものであ
る。The second line conductor 26b has a conductor layer 26d provided on the end surface of the extension of the second line conductor 26b of the circuit board 26-B, as shown in the enlarged plan view of the main portion of FIG. And is electrically connected to the ground conductor layer 26c-B. A high resistance portion 28 is provided on the second line conductor 26b. The high resistance portion 28 converts a termination signal including a high frequency signal component, which flows through the second line conductor 26b and is grounded to the ground conductor layer 26c-B, from electrical energy to thermal energy, and the ground conductor layer 26c. The noise due to the reflection of the termination signal from -B is suppressed and electrically grounded.
【０００９】最後に、基体２１、枠体２２から成る容器
内部に半導体素子２５を収容し、枠体２２の上面に蓋体
２４をろう付け法やシームウエルド法等の溶接法により
接合し、容器内部を気密に封止することによって製品と
しての半導体装置となる。Finally, the semiconductor element 25 is housed in a container consisting of the base body 21 and the frame body 22, and the lid body 24 is joined to the upper surface of the frame body 22 by a welding method such as a brazing method or a seam weld method. A semiconductor device as a product is obtained by hermetically sealing the inside.
【００１０】[0010]
【発明が解決しようとする課題】しかしながら、上記従
来の半導体パッケージにおいては、第２の線路導体２６
ｂと導体層２６ｄとの境界部および導体層２６ｄと接地
導体層２６ｃ−Ｂとの境界部で終端用信号が略直角に曲
がって伝送するため、終端用信号の伝送をスムーズにで
きないといった理由により、回路基板２６−Ｂに設けた
第２の線路導体２６ｂを伝送する終端用信号を確実に接
地させるのが困難であった。そのため、第２の線路導体
２６ｂを伝わる終端用信号の反射によるノイズが発生
し、半導体素子２５を正常に作動させることができない
という問題点を有していた。However, in the above conventional semiconductor package, the second line conductor 26 is used.
Because the termination signal is bent and transmitted at a substantially right angle at the boundary between the conductor layer 26d and the ground conductor layer 26c-B and the boundary between the conductor layer 26d and the ground conductor layer 26c-B, the termination signal cannot be transmitted smoothly. However, it is difficult to reliably ground the terminating signal transmitted through the second line conductor 26b provided on the circuit board 26-B. Therefore, there is a problem in that noise is generated due to the reflection of the termination signal transmitted through the second line conductor 26b, and the semiconductor element 25 cannot be operated normally.
【００１１】また、第２の線路導体２６ｂを伝わる終端
用信号の高周波化が進むと、第２の線路導体２６ｂに設
けられた高抵抗部２８において、終端用信号の電気エネ
ルギーを熱エネルギーに変換することを十分にできなく
なるとともに、接地導体層２６ｃ−Ｂは終端用信号を接
地させるには不十分な面積となっていた。即ち、高抵抗
部２８では終端用信号を確実に電気エネルギーから熱エ
ネルギーに変換することができず、また接地導体２６ｃ
−Ｂの面積が不十分であるため、第２の線路導体２６ｂ
を伝送する終端用信号を確実に接地できなくなる。その
ため、第２の線路導体２６ｂを伝わる終端用信号によっ
て接地導体層２６ｃ−Ｂからの反射によるノイズが発生
し、そのノイズが半導体素子２５に入り込んで誤作動を
発生させるという問題点を有していた。When the frequency of the termination signal transmitted through the second line conductor 26b is increased, the high resistance portion 28 provided in the second line conductor 26b converts the electrical energy of the termination signal into thermal energy. In addition to that, the ground conductor layer 26c-B has an insufficient area for grounding the termination signal. That is, the high resistance portion 28 cannot reliably convert the termination signal from electrical energy to thermal energy, and the ground conductor 26c
Since the area of −B is insufficient, the second line conductor 26b
It becomes impossible to reliably ground the terminating signal that transmits the signal. Therefore, there is a problem that the termination signal transmitted through the second line conductor 26b causes noise due to reflection from the ground conductor layer 26c-B, and the noise enters the semiconductor element 25 to cause malfunction. It was
【００１２】特に、上記問題点は、光通信分野に使用さ
れたりマイクロ波帯やミリ波帯等の高周波信号を用いる
各種半導体素子を組み込んだ半導体装置の高速情報処理
化が進み、第１の線路導体２６ａおよび第２の線路導体
２６ｂを介して半導体素子２５に入出力される信号がよ
り高周波領域になると、より顕著となっていた。Particularly, the above problem is caused by the progress of high-speed information processing of a semiconductor device used in the field of optical communication or incorporating various semiconductor elements using a high frequency signal of a microwave band, a millimeter wave band, etc. It became more prominent when the signal input to and output from the semiconductor element 25 via the conductor 26a and the second line conductor 26b was in a higher frequency region.
【００１３】従って、本発明は上記問題点に鑑み完成さ
れたものであり、その目的は、半導体素子の終端用電極
に終端用信号の高周波信号成分が反射して入り込んで半
導体素子が誤作動を起こすのを防ぐことにより、信頼性
の高いものとすることにある。Therefore, the present invention has been completed in view of the above problems, and an object of the present invention is to prevent a malfunction of a semiconductor element due to reflection of a high frequency signal component of a termination signal into a termination electrode of the semiconductor element. To prevent it from happening, to make it more reliable.
【００１４】[0014]
【課題を解決するための手段】本発明の半導体パッケー
ジは、上側主面に半導体素子を載置するための載置部を
有する基体と、前記上側主面の外周部に前記載置部を囲
繞するように接合され、内面に回路基板を載置するため
の棚部を有する枠体とを具備した半導体素子収納用パッ
ケージにおいて、前記回路基板は、その上面に、一端が
前記半導体素子に電気的に接続され他端が縁部に達して
おりかつ途中に高抵抗部を設けた接地用の線路導体が形
成されているとともに、前記線路導体を取り囲むように
形成されかつ前記線路導体の他端側に接続された同一面
接地導体層が設けられ、下面に接地導体層が形成されて
おり、さらに前記線路導体の他端から前記回路基板の端
面および前記接地導体層にかけて導体層が形成されてい
ることを特徴とする。A semiconductor package according to the present invention includes a base body having a mounting portion for mounting a semiconductor element on an upper main surface and an outer peripheral portion of the upper main surface surrounding the mounting portion. And a frame body having a shelf for mounting the circuit board on the inner surface thereof, the circuit board is electrically connected to the upper surface of the circuit board. Is connected to the other end of the line conductor, the other end of the line conductor is formed to surround the line conductor, and the other end of the line conductor is formed on the other end of the line conductor. And a ground conductor layer formed on the lower surface, and a conductor layer is formed from the other end of the line conductor to the end surface of the circuit board and the ground conductor layer. Characterized by .
【００１５】本発明の半導体パッケージによれば、線路
導体の他端側に接続された同一面接地導体層が回路基板
の上面に形成されていることから、線路導体の他端にお
いて線路導体を伝送する終端用信号を電気的に接地させ
るための接地導体層の面積を拡大できる。そのため、線
路導体から接地導体層に向けての終端用信号の伝送をス
ムーズに行なうことができ、他端における終端用信号の
反射を有効に減少させることができる。According to the semiconductor package of the present invention, since the same-plane grounding conductor layer connected to the other end of the line conductor is formed on the upper surface of the circuit board, the line conductor is transmitted at the other end of the line conductor. The area of the ground conductor layer for electrically grounding the terminating signal can be increased. Therefore, the termination signal can be smoothly transmitted from the line conductor to the ground conductor layer, and the reflection of the termination signal at the other end can be effectively reduced.
【００１６】また、線路導体に略平行かつ取り囲むよう
に同一面接地導体層が設けられていることから、線路導
体から同一面接地導体層に終端用信号の高周波信号成分
を空間を介して短絡させることができ、線路導体におい
て終端用信号を大幅に減衰させて確実に接地させること
ができる。即ち、線路導体を進行する終端用信号は、線
路導体の他端側に向かって同一面接地導体層に空間を介
して短絡されながら進行するため、他端側にいくにつれ
て大幅に減衰されることとなる。Further, since the same-plane grounding conductor layer is provided so as to be substantially parallel to and surround the line conductor, the high-frequency signal component of the termination signal is short-circuited from the line conductor to the same-plane grounding conductor layer through a space. It is possible to significantly attenuate the terminating signal in the line conductor and reliably ground it. That is, the terminating signal that travels along the line conductor travels toward the other end of the line conductor while being short-circuited to the ground conductor layer on the same plane through the space, and therefore is greatly attenuated toward the other end. Becomes
【００１７】さらに、同一面接地導体層において、好ま
しくは金属から成る枠体に向けて終端用信号を放射し易
くなり、線路導体に設けられた高抵抗部において接地し
きれない終端用信号を放射することによって終端用信号
をより確実に接地することができる。Further, in the ground conductor layer on the same plane, it is easy to radiate the termination signal toward the frame body preferably made of metal, and the termination signal which cannot be grounded is radiated in the high resistance portion provided in the line conductor. By doing so, the termination signal can be grounded more reliably.
【００１８】従って、本発明は、このような構成によ
り、線路導体を伝わる終端用信号の反射によるノイズが
発生することを防止し、半導体素子を正常に作動させ得
る。Therefore, according to the present invention, by such a structure, it is possible to prevent the generation of noise due to the reflection of the termination signal transmitted through the line conductor, and to operate the semiconductor element normally.
【００１９】また、本発明の半導体装置は、上記本発明
の半導体素子収納用パッケージと、前記棚部に設置され
た前記回路基板と、前記載置部に載置されるとともに前
記回路基板の線路導体の一端に電気的に接続された前記
半導体素子と、前記枠体の上面に接合された蓋体とを具
備したことを特徴とする。Further, a semiconductor device of the present invention includes the semiconductor element housing package of the present invention, the circuit board installed on the shelf portion, and the line of the circuit board mounted on the mounting portion. It is characterized by comprising the semiconductor element electrically connected to one end of a conductor, and a lid body joined to an upper surface of the frame body.
【００２０】本発明は、このような構成により、上記本
発明の半導体パッケージを用いた信頼性の高い半導体装
置を提供できる。With the above-described structure, the present invention can provide a highly reliable semiconductor device using the semiconductor package of the present invention.
【００２１】[0021]
【発明の実施の形態】本発明の半導体パッケージについ
て以下に詳細に説明する。図１は本発明の半導体パッケ
ージについて実施の形態の一例を示す断面図であり、１
は基体、２は枠体、６−Ａ，６−Ｂは回路基板である。BEST MODE FOR CARRYING OUT THE INVENTION The semiconductor package of the present invention will be described in detail below. FIG. 1 is a sectional view showing an example of an embodiment of a semiconductor package of the present invention.
Is a base, 2 is a frame, and 6-A and 6-B are circuit boards.
【００２２】本発明の基体１は、Ｆｅ−Ｎｉ−Ｃｏ合金
等の金属やＣｕ−Ｗの焼結材等から成る略四角形の板状
体であり、そのインゴットに圧延加工や打ち抜き加工等
の従来周知の金属加工法、または射出成形と切削加工等
を施すことによって、所定の形状に製作される。基体１
の上側主面の略中央部には、ＩＣ，ＬＳＩ，ＬＤ，ＰＤ
等の半導体素子５を載置するための載置部１ａが形成さ
れており、載置部１ａには半導体素子５が載置固定され
る。The substrate 1 of the present invention is a substantially rectangular plate-like body made of a metal such as an Fe-Ni-Co alloy or a Cu-W sintered material, and its ingot is conventionally subjected to rolling or punching. It is manufactured into a predetermined shape by a well-known metal working method, or injection molding and cutting. Base 1
IC, LSI, LD, PD in the approximately central part of the upper main surface of
A mounting portion 1a for mounting the semiconductor element 5 such as the above is formed, and the semiconductor element 5 is mounted and fixed on the mounting portion 1a.
【００２３】また、基体１の上側主面の外周部には載置
部１ａを囲繞するようにして枠体２が立設するように接
合されており、枠体２は基体１とともにその内側に半導
体素子５を収容する空所を形成する。この枠体２は、基
体１と同様にＦｅ−Ｎｉ−Ｃｏ合金やＣｕ−Ｗの焼結材
等から成り、基体１と一体成形される、または基体１に
Ａｇろう等のろう材を介してろう付けされる、またはシ
ーム溶接法等の溶接法により接合されることによって、
基体１の上側主面の外周部に立設される。Further, a frame body 2 is joined to the outer peripheral portion of the upper main surface of the base body 1 so as to stand upright so as to surround the mounting portion 1a. A void for accommodating the semiconductor element 5 is formed. The frame body 2 is made of a sintered material such as a Fe—Ni—Co alloy or Cu—W similar to the base body 1, and is integrally molded with the base body 1 or via a brazing material such as Ag brazing on the base body 1. By brazing or joining by welding methods such as seam welding,
It is erected on the outer peripheral portion of the upper main surface of the base 1.
【００２４】枠体２の内面には回路基板６−Ａ，６−Ｂ
を設置するための棚部２ｂ−Ａ，２ｂ−Ｂが設けられて
おり、棚部２ｂ−Ａ，２ｂ−Ｂは枠体２と一体成形され
るか、または、別体として作製した棚部２ｂ−Ａ，２ｂ
−Ｂの一端面をＡｇろう等のろう材を介して枠体２にろ
う付け、または溶接法により接合することにより枠体２
と一体化される。回路基板６−Ａ，６−Ｂの下面には接
地導体層６ｃ−Ａ，６ｃ−Ｂが被着形成されており、Ａ
ｇろう，Ａｇ−Ｃｕろう等のろう材やＡｕ−Ｓｎ半田や
Ｐｂ−Ｓｎ半田等の半田によって接地導体層６ｃ−Ａ，
６ｃ−Ｂと棚部２ｂ−Ａ，２ｂ−Ｂが強固に接着され
る。On the inner surface of the frame body 2, circuit boards 6-A and 6-B are provided.
Shelves 2b-A and 2b-B for installing the shelves 2b-A and 2b-B are formed integrally with the frame 2 or are separately manufactured. -A, 2b
The frame body 2 is formed by brazing one end surface of -B to the frame body 2 through a brazing material such as Ag brazing, or by joining by welding.
Is integrated with. Ground conductor layers 6c-A and 6c-B are adhered and formed on the lower surfaces of the circuit boards 6-A and 6-B.
A ground conductor layer 6c-A, which is made of a brazing material such as g solder or Ag-Cu solder, or a solder such as Au-Sn solder or Pb-Sn solder.
6c-B and the shelves 2b-A and 2b-B are firmly bonded.
【００２５】なお、枠体２はＦｅ−Ｎｉ−Ｃｏ合金やＣ
ｕ−Ｗの焼結材等の金属の他に、セラミックス等の誘電
体材料から成りかつその表面にメタライズ層等の導体層
が形成されているのが好ましい。この場合、後述するよ
うに、同一面接地導体層１６から枠体２に向けて放射さ
れた高周波信号成分を接地し易くなり、第２の線路導体
６ｂに設けられた高抵抗部８において接地しきれない終
端用信号を放射することによって終端用信号をより確実
に接地することができる。The frame 2 is made of Fe-Ni-Co alloy or C.
In addition to a metal such as a u-W sintered material, it is preferable that a dielectric material such as ceramics is formed and a conductor layer such as a metallized layer is formed on the surface thereof. In this case, as will be described later, it becomes easy to ground the high-frequency signal component radiated from the same-plane grounding conductor layer 16 toward the frame body 2, and it is grounded in the high resistance portion 8 provided in the second line conductor 6b. The terminating signal can be grounded more reliably by radiating the unterminating signal.
【００２６】半導体素子５は、その電極が回路基板６−
Ａ，６−Ｂの上面に被着形成されている第１の線路導体
６ａおよび接地用の第２の線路導体６ｂにそれぞれボン
ディングワイヤ７ａ，７ｂを介して電気的に接続され
る。The semiconductor element 5 has its electrodes on the circuit board 6-.
The first line conductor 6a and the second line conductor 6b for grounding, which are adhered and formed on the upper surfaces of A and 6-B, are electrically connected via bonding wires 7a and 7b, respectively.
【００２７】回路基板６−Ａ，６−Ｂは、例えばＡｌ2
Ｏ3セラミックスから成る場合、以下のようにして作製
される。まず、Ａｌ2Ｏ3，酸化珪素（ＳｉＯ2），酸化
カルシウム（ＣａＯ），酸化マグネシウム（ＭｇＯ）等
の原料粉末に適当な有機バインダや可塑剤，分散剤，溶
剤等を添加混合して泥漿状となす。これを従来周知のド
クターブレード法でシート状となすことによってセラミ
ックグリーンシートを得る。しかる後、このセラミック
グリーンシートに適当な打ち抜き加工を施す、または、
Ａｌ2Ｏ3，ＳｉＯ2，ＣａＯ，ＭｇＯ等の原料粉末を金
型に充填しプレス成型することによって、所定の形状に
成形する。そのセラミックグリーンシートの上面に第１
の線路導体６ａ、第２の線路導体６ｂおよび接地導体層
６ｃとなる金属ペーストを印刷塗布し、還元雰囲気中で
約１６００℃の温度で焼成することによって製作され
る。The circuit boards 6-A and 6-B are made of, for example, Al 2
When it is made of O 3 ceramics, it is manufactured as follows. First, a raw material powder of Al 2 O 3 , silicon oxide (SiO 2 ), calcium oxide (CaO), magnesium oxide (MgO), etc. is mixed with an appropriate organic binder, plasticizer, dispersant, solvent, etc. And eggplant A ceramic green sheet is obtained by forming this into a sheet by a conventionally known doctor blade method. After that, apply appropriate punching processing to this ceramic green sheet, or
A raw material powder such as Al 2 O 3 , SiO 2 , CaO, and MgO is filled in a mold and press-molded to form a predetermined shape. No. 1 on the top surface of the ceramic green sheet
Of the line conductor 6a, the second line conductor 6b, and the ground conductor layer 6c are printed and applied, and the paste is baked at a temperature of about 1600 ° C. in a reducing atmosphere.
【００２８】第１の線路導体６ａ、第２の線路導体６ｂ
および接地導体層６ｃとなる金属ペーストは、Ｗ，モリ
ブデン（Ｍｏ），マンガン（Ｍｎ）等の高融点金属粉末
に適当な有機バインダや溶剤を添加混合してペースト状
となしたものを従来周知のスクリーン印刷法を採用して
印刷することにより、セラミックグリーンシートまたは
セラミックスの成形体に印刷塗布される。The first line conductor 6a and the second line conductor 6b
As the metal paste to be the ground conductor layer 6c, a paste having a high melting point metal powder such as W, molybdenum (Mo), manganese (Mn), etc. added and mixed with an appropriate organic binder and a solvent to form a paste is well known. By printing using a screen printing method, it is applied by printing onto a ceramic green sheet or a ceramic molded body.
【００２９】なお、第１の線路導体６ａ、第２の線路導
体６ｂおよび接地導体層６ｃは薄膜形成法によって形成
されていても良く、その場合、第１の線路導体６ａ、第
２の線路導体６ｂおよび接地導体層６ｃは窒化タンタル
（Ｔａ2Ｎ），ニクロム（Ｎｉ−Ｃｒ合金），チタン
（Ｔｉ），パラジウム（Ｐｄ），白金（Ｐｔ），Ａｕ等
から形成され、セラミックグリーンシートを焼成した後
に形成される。The first line conductor 6a, the second line conductor 6b and the ground conductor layer 6c may be formed by a thin film forming method. In that case, the first line conductor 6a and the second line conductor 6a are formed. 6b and the ground conductor layer 6c are made of tantalum nitride (Ta 2 N), nichrome (Ni—Cr alloy), titanium (Ti), palladium (Pd), platinum (Pt), Au, etc., and fired a ceramic green sheet. It will be formed later.
【００３０】また、外部より半導体素子５に駆動信号等
を入力するものとして、例えば同軸コネクタ３が用いら
れ、以下のようにして枠体２に設置される。枠体２の側
面に同軸コネクタ３が嵌着される貫通孔２ａを形成し、
貫通孔２ａ内に同軸コネクタ３を嵌め込むとともにＡｕ
−Ｓｎ半田やＰｂ−Ｓｎ半田等の封着材を貫通孔２ａと
の隙間に挿入する。しかる後、加熱して封着材を溶融さ
せ、溶融した封着材は毛細管現象により同軸コネクタ３
と貫通孔２ａの内面との隙間に充填されることによっ
て、同軸コネクタ３が貫通孔２ａ内に半田等の封着材を
介して嵌着接合される。A coaxial connector 3 is used, for example, to input a drive signal and the like to the semiconductor element 5 from the outside, and is installed in the frame body 2 as follows. Forming a through hole 2a into which the coaxial connector 3 is fitted on the side surface of the frame body 2;
The coaxial connector 3 is fitted into the through hole 2a and the Au
A sealing material such as -Sn solder or Pb-Sn solder is inserted in the gap with the through hole 2a. Then, the sealing material is melted by heating, and the molten sealing material undergoes a capillary phenomenon to cause the coaxial connector 3
By filling the gap between the inner surface of the through hole 2a and the through hole 2a, the coaxial connector 3 is fitted and joined into the through hole 2a via a sealing material such as solder.
【００３１】同軸コネクタ３は、内部に収容する半導体
素子５を外部電気回路に接続された同軸ケーブルに電気
的に接続するものであり、Ｆｅ−Ｎｉ−Ｃｏ合金等の金
属から成る円筒形等の筒状の外周導体にガラス等の絶縁
体が充填され、中心軸にＦｅ−Ｎｉ−Ｃｏ合金等の金属
から成る中心導体３ａが固定されて成る。中心導体３ａ
が半田等から成る導電性接着材を介して回路基板６−Ａ
の第１の線路導体６ａに電気的に接続される。この同軸
コネクタ３に、同軸ケーブルが装着されることによっ
て、半導体パッケージの内部に収納された半導体素子５
が同軸コネクタ３の中心導体３ａを介して、外部電気回
路に電気的に接続されることとなる。The coaxial connector 3 electrically connects the semiconductor element 5 housed inside to a coaxial cable connected to an external electric circuit, and is of a cylindrical shape or the like made of a metal such as Fe-Ni-Co alloy. An insulating material such as glass is filled in a cylindrical outer peripheral conductor, and a central conductor 3a made of a metal such as Fe—Ni—Co alloy is fixed to the central axis. Center conductor 3a
Circuit board 6-A through a conductive adhesive material such as solder
Is electrically connected to the first line conductor 6a. When the coaxial cable is attached to the coaxial connector 3, the semiconductor element 5 housed inside the semiconductor package is mounted.
Is electrically connected to an external electric circuit via the central conductor 3a of the coaxial connector 3.
【００３２】そして、半導体素子５の電極と回路基板６
−Ａの上面に形成された第１の線路導体６ａとがボンデ
ィングワイヤ７ａにより電気的に接続され、第１の線路
導体６ａと中心導体３ａとが半田等の導電性接着材を介
して電気的に接続される。The electrodes of the semiconductor element 5 and the circuit board 6
-The first line conductor 6a formed on the upper surface of -A is electrically connected by the bonding wire 7a, and the first line conductor 6a and the center conductor 3a are electrically connected via a conductive adhesive such as solder. Connected to.
【００３３】また、回路基板６−Ｂの上面に形成された
第２の線路導体６ｂは、図２に示すように、一端が半導
体素子５に電気的に接続され、他端が回路基板６−Ｂの
上面の縁部に達しており、かつ途中に高抵抗部８が設け
られ、他端は回路基板６−Ｂの上面の略全周に線路導体
６ｂに略平行かつ取り囲むように設けられた同一面接地
導体層１６に接続されている。この場合、同一面接地導
体層１６は、回路基板６−Ｂの上面に線路導体６ｂを取
り囲むように設けられるが、好ましくは、回路基板６−
Ｂの上面の略全周に設けられるのがよく、同一面接地導
体層１６から高周波信号成分が枠体２に向けて放射され
易くなる。As shown in FIG. 2, one end of the second line conductor 6b formed on the upper surface of the circuit board 6-B is electrically connected to the semiconductor element 5 and the other end thereof is the circuit board 6-. The high resistance portion 8 is provided at the edge of the upper surface of B, and the high resistance portion 8 is provided in the middle, and the other end is provided substantially in the entire circumference of the upper surface of the circuit board 6-B so as to be substantially parallel to and surround the line conductor 6b. It is connected to the coplanar ground conductor layer 16. In this case, the same-plane ground conductor layer 16 is provided on the upper surface of the circuit board 6-B so as to surround the line conductor 6b, but preferably the circuit board 6-
It is preferable that it is provided substantially all around the upper surface of B so that the high-frequency signal component is easily radiated from the same-plane ground conductor layer 16 toward the frame body 2.
【００３４】第２の線路導体６ｂの途中に設けられた高
抵抗部８は、Ｔａ2Ｎ，Ｎｉ−Ｃｒ合金等の材料から成
り、回路基板６−Ｂに印刷塗布された後に焼成される
か、薄膜形成法により形成され、所望の抵抗値を有する
厚み、幅、形状となるように形成される。抵抗値を微小
調整するために、高抵抗部８の一部をレーザ加工によっ
て除去することもできる。The high resistance portion 8 provided in the middle of the second line conductor 6b is made of a material such as Ta 2 N, Ni--Cr alloy or the like, and is printed on the circuit board 6-B and then baked. It is formed by a thin film forming method and is formed so as to have a thickness, a width and a shape having a desired resistance value. In order to finely adjust the resistance value, a part of the high resistance portion 8 can be removed by laser processing.
【００３５】また、回路基板６−Ｂの端面で第２の線路
導体６ｂを他端側に延長した部位には導体層６ｄが設け
られ、第２の線路導体６ｂが導体層６ｄを介して接地導
体層６ｃ−Ｂに電気的に接続されている。Further, a conductor layer 6d is provided on the end surface of the circuit board 6-B where the second line conductor 6b is extended to the other end side, and the second line conductor 6b is grounded via the conductor layer 6d. It is electrically connected to the conductor layer 6c-B.
【００３６】接地導体層６ｃ−Ａ，６ｃ−Ｂは、Ａｇろ
う，Ａｇ−Ｃｕろう等のろう材やＡｕ−Ｓｎ半田やＰｂ
−Ｓｎ半田等の半田によって、枠体２に設けられた棚部
２ｂ−Ａ，２ｂ−Ｂに強固に接着され、回路基板６−
Ａ，６−Ｂがそれぞれ棚部２ｂ−Ａ，２ｂ−Ｂに設置固
定されている。The ground conductor layers 6c-A and 6c-B are made of a brazing material such as Ag brazing or Ag-Cu brazing, Au-Sn solder or Pb.
-Soldering such as Sn solder firmly adheres to the shelves 2b-A and 2b-B provided on the frame body 2 to form the circuit board 6-
A and 6-B are installed and fixed on the shelves 2b-A and 2b-B, respectively.
【００３７】本発明は、第２の線路導体６ｂの他端に同
一面接地導体層１６が接続するように形成されているこ
とから、従来に比べ第２の線路導体６ｂの他端において
第２の線路導体６ｂを伝送する終端用信号を接地させる
ための接地導体層６ｃ−Ｂの面積を拡大できる。そのた
め、第２の線路導体６ｂから接地導体層６ｃ−Ｂに向け
ての高周波信号の伝送をスムーズに行なうことができ、
第２の線路導体６ｂの他端における終端用信号の反射を
有効に減少させることができる。According to the present invention, since the same-plane ground conductor layer 16 is formed so as to be connected to the other end of the second line conductor 6b, the second end is formed at the other end of the second line conductor 6b as compared with the prior art. The area of the ground conductor layer 6c-B for grounding the termination signal transmitted through the line conductor 6b can be increased. Therefore, the high-frequency signal can be smoothly transmitted from the second line conductor 6b to the ground conductor layer 6c-B,
The reflection of the termination signal at the other end of the second line conductor 6b can be effectively reduced.
【００３８】また、第２の線路導体６ｂに略平行にかつ
取り囲むように同一面接地導体層１６が設けられている
ことから、第２の線路導体６ｂから同一面接地導体層１
６に終端用信号を空間を介して短絡させることができ、
第２の線路導体６ｂにおいて終端用信号を減衰させて確
実に接地させることができる。Since the coplanar grounding conductor layer 16 is provided so as to be substantially parallel to and surround the second line conductor 6b, the coplanar grounding conductor layer 1 is provided from the second line conductor 6b.
6, the signal for termination can be short-circuited through space,
In the second line conductor 6b, the termination signal can be attenuated and reliably grounded.
【００３９】さらに、同一面接地導体層１６において枠
体２に向けて高周波信号を放射し易くなり、第２の線路
導体６ｂに設けられた高抵抗部８において接地しきれな
い終端用信号を放射することによって終端用信号をより
確実に接地することができる。Further, it becomes easier to radiate a high frequency signal toward the frame 2 in the ground conductor layer 16 on the same plane, and a termination signal that cannot be grounded is radiated in the high resistance portion 8 provided in the second line conductor 6b. By doing so, the termination signal can be grounded more reliably.
【００４０】このようにして、第２の線路導体６ｂを伝
わる終端用信号をより確実に接地することができ、第２
の線路導体６ｂを伝わる終端用信号により生じる接地導
体層６ｃ−Ｂからの反射によるノイズが発生し、そのノ
イズが半導体素子５に入り込むのを防止し、半導体素子
５を正常に作動させ得る。In this way, the terminating signal transmitted through the second line conductor 6b can be grounded more reliably,
The noise due to the reflection from the ground conductor layer 6c-B generated by the terminating signal transmitted through the line conductor 6b is prevented from entering the semiconductor element 5, and the semiconductor element 5 can be normally operated.
【００４１】また、回路基板６−Ａ，６−Ｂは枠体２に
設けられた棚部２ｂ−Ａ，２ｂ−Ｂに設置されている。
基体１には半導体パッケージの製造過程において反りが
発生し、外部回路基板へねじ止めによって実装する際、
この反りが矯正される。従来、反りが矯正されることに
より、基体１上に設置された回路基板６−Ａ，６−Ｂに
歪が加わって回路基板６−Ａ，６−Ｂが破損し線路導体
６ａ，６ｂが断線してしまい半導体素子５が作動しなく
なる場合があったが、枠体２に設けられた棚部２ｂ−
Ａ，２ｂ−Ｂは、反りの矯正時に加わる歪の影響を受け
にくくなる。そのため、棚部２ｂ−Ａ，２ｂ−Ｂにそれ
ぞれ回路基板６−Ａ，６−Ｂを設置することにより、基
体１の反りの矯正時に加わる歪の影響をほとんど受けな
くなり、回路基板６−Ａ，６−Ｂの破損を防止し線路導
体６ａ，６ｂを伝送する高周波信号を無駄なく伝送でき
る。従って、半導体素子５を正常かつ安定に作動させる
ことができる。The circuit boards 6-A and 6-B are installed on the shelves 2b-A and 2b-B provided on the frame body 2.
The substrate 1 is warped during the manufacturing process of the semiconductor package, and when mounted on the external circuit board by screwing,
This warp is corrected. Conventionally, by correcting the warp, distortion is applied to the circuit boards 6-A and 6-B installed on the base 1, the circuit boards 6-A and 6-B are damaged, and the line conductors 6a and 6b are disconnected. However, the semiconductor element 5 may not operate, but the shelf 2b-provided on the frame 2
A and 2b-B are less likely to be affected by the strain applied when correcting the warp. Therefore, by installing the circuit boards 6-A and 6-B on the shelves 2b-A and 2b-B, respectively, the influence of the strain applied during the correction of the warp of the substrate 1 is hardly received, and the circuit boards 6-A and 6-A It is possible to prevent the damage of 6-B and to transmit the high frequency signal transmitted through the line conductors 6a and 6b without waste. Therefore, the semiconductor element 5 can be operated normally and stably.
【００４２】そして、上記本発明の半導体パッケージの
枠体２上面にＦｅ−Ｎｉ−Ｃｏ合金等の金属から成る蓋
体４を半田付けやシームウエルド法により接合すること
によって、製品としての半導体装置となる。蓋体４によ
り、容器内部に収納した半導体素子５を気密に収容し、
半導体素子５を長期にわたり正常かつ安定に作動させる
ことができる。この半導体装置は、基体１が外部電気回
路基板に固定実装され、同軸コネクタ３と外部電気回路
に接続された同軸ケーブルとを接続することにより、内
部に収納した半導体素子５が外部電気回路に電気的に接
続され、半導体素子５が高周波信号で作動することとな
る。Then, a lid 4 made of a metal such as Fe-Ni-Co alloy is joined to the upper surface of the frame 2 of the semiconductor package of the present invention by soldering or a seam weld method to obtain a semiconductor device as a product. Become. The lid 4 hermetically houses the semiconductor element 5 housed in the container,
The semiconductor element 5 can be operated normally and stably for a long period of time. In this semiconductor device, the base 1 is fixedly mounted on an external electric circuit board, and the coaxial connector 3 and the coaxial cable connected to the external electric circuit are connected to each other, so that the semiconductor element 5 housed inside is electrically connected to the external electric circuit. And the semiconductor element 5 operates with a high frequency signal.
【００４３】本発明における高周波信号の好ましい周波
数は５〜２０ＧＨｚ程度であり、この場合に高周波信号
の伝送特性を良好なものとすることができる。The preferred frequency of the high frequency signal in the present invention is about 5 to 20 GHz, and in this case, the transmission characteristics of the high frequency signal can be improved.
【００４４】[0044]
【実施例】以下に本発明の実施例について説明する。EXAMPLES Examples of the present invention will be described below.
【００４５】（実施例）本発明の実施例と従来例につい
て、線路導体の伝送特性を以下のように解析した。伝送
特性の解析は、図５（ａ），（ｂ）に示した２種類の解
析モデルについて行なった。この解析モデルは、図１ま
たは図３に示した構成をモデル化したものである。即
ち、図５（ａ）は本発明の実施例による回路基板６−Ｂ
の解析モデル（モデルＡ）の上面図、５（ｂ）は従来の
回路基板２６−Ｂの解析モデル（モデルＢ）の上面図で
ある。(Example) With respect to the example of the present invention and the conventional example, the transmission characteristics of the line conductor were analyzed as follows. The analysis of the transmission characteristics was performed on the two types of analysis models shown in FIGS. 5 (a) and 5 (b). This analytical model is a model of the configuration shown in FIG. 1 or 3. That is, FIG. 5A shows a circuit board 6-B according to an embodiment of the present invention.
5B is a top view of the analysis model (model B) of the conventional circuit board 26-B.
【００４６】各解析モデルＡ，Ｂにおいて、回路基板６
−Ｂ（２６−Ｂ）（厚さ１ｍｍ）はアルミナセラミック
ス（比誘電率εｒ＝９．４）からなり、回路基板６−Ｂ
（２６−Ｂ）の上面には高抵抗部８（２８）を５０Ωと
した第２の線路導体６ｂ（２６ｂ）を形成した。また、
ボンディングワイヤ７ｂ（２７ｂ）が接続される側と反
対側である、回路基板６−Ｂ（２６−Ｂ）の端面の第２
の線路導体６ｂ（２６ｂ）を延長した部位に、導体層６
ｄ（２６ｄ）を形成した。この導体層６ｄ（２６ｄ）を
介して、第２の線路導体６ｂ（２６ｂ）を回路基板６−
Ｂ（２６−Ｂ）の下面の接地導体層６ｃ−Ｂ（２６ｃ−
Ｂ）に電気的に接続した。In each analysis model A, B, the circuit board 6
-B (26-B) (thickness 1 mm) is made of alumina ceramics (relative permittivity εr = 9.4), and the circuit board 6-B
The second line conductor 6b (26b) having the high resistance portion 8 (28) of 50Ω was formed on the upper surface of (26-B). Also,
The second end surface of the circuit board 6-B (26-B), which is the side opposite to the side to which the bonding wire 7b (27b) is connected.
The conductor layer 6 is provided at a portion where the line conductor 6b (26b) of
d (26d) was formed. The second line conductor 6b (26b) is connected to the circuit board 6- via the conductor layer 6d (26d).
B (26-B) lower surface ground conductor layer 6c-B (26c-
It was electrically connected to B).
【００４７】各解析モデルＡ，Ｂでは、半導体素子５の
終端用電極の両脇に接地用電極が設けられているものに
ついてモデル化しているため、その接地用電極にボンデ
ィングワイヤを介して接続される接地電極層を、回路基
板６−Ｂ（２６−Ｂ）の上面の縁部で第２の線路導体６
ｂ（２６ｂ）の両側に形成した。その接地電極層は、回
路基板６−Ｂ（２６−Ｂ）の端面に設けられた配線導体
を介して接地導体層６ｃに電気的に接続されるようにし
た。In each of the analysis models A and B, since the grounding electrodes are provided on both sides of the terminating electrode of the semiconductor element 5, the semiconductor element 5 is connected to the grounding electrode via a bonding wire. The second ground line conductor 6 at the edge of the upper surface of the circuit board 6-B (26-B).
It was formed on both sides of b (26b). The ground electrode layer was electrically connected to the ground conductor layer 6c via a wiring conductor provided on the end surface of the circuit board 6-B (26-B).
【００４８】図５（ａ）において、回路基板６−Ｂの上
面に第２の線路導体６ｂを取り囲むようにして同一面接
地導体層１６を形成した。また、各モデルＡ，Ｂにおい
て、基体１（１１）の材質はＦｅ−Ｎｉ−Ｃｏ合金、枠
体２（２２）の材質はＦｅ−Ｎｉ−Ｃｏ合金、ボンディ
ングワイヤ７ｂ（２７ｂ）の材質はＡｕであり、それぞ
れ同様の材質から成るものとした。回路基板６−Ｂ（２
６−Ｂ）、第２の線路導体６ｂ（２６ｂ）および同一面
接地導体層１６の詳細な寸法は、それぞれ図５（ａ），
（ｂ）に示す通りとした（単位はｍｍ）。In FIG. 5A, the same-plane ground conductor layer 16 is formed on the upper surface of the circuit board 6-B so as to surround the second line conductor 6b. In each of the models A and B, the material of the base 1 (11) is Fe-Ni-Co alloy, the material of the frame 2 (22) is Fe-Ni-Co alloy, and the material of the bonding wire 7b (27b) is Au. And made of the same material. Circuit board 6-B (2
6-B), the second line conductor 6b (26b) and the same-plane ground conductor layer 16 have detailed dimensions as shown in FIG.
As shown in (b), the unit is mm.
【００４９】そして、各モデルＡ，Ｂについて、０〜２
０ＧＨｚの周波数帯域おける反射損失をシミュレーショ
ンによって求めた。図６は各モデルＡ，Ｂの反射損失の
グラフである。図６において、周波数が０〜２０ＧＨｚ
の大部分で、従来のモデルＢに比べ、本発明のモデルＡ
の反射損失が改善されていることがわかる。For each of the models A and B, 0 to 2
The reflection loss in the frequency band of 0 GHz was obtained by simulation. FIG. 6 is a graph of the reflection loss of each model A and B. In FIG. 6, the frequency is 0 to 20 GHz.
In most of the cases, compared to the conventional model B, the model A of the present invention
It can be seen that the reflection loss of is improved.
【００５０】図６の結果から、各モデルＡ，Ｂを構成す
る各部位は、それぞれ同様の材質から成っており、第２
の線路導体６ｂ（２６ｂ）部、接地導体層６ｃ−Ｂ（２
６ｃ−Ｂ）部、導体層６ｄ（２６ｄ）部および高抵抗部
８（２８）に起因する伝送損失は同じとみなせることか
ら、各モデルＡ，Ｂの伝送損失の違いは、同一面接地導
体層１６の有無に基づくものとみなせる。１２〜１５．
５ＧＨｚにおいて、モデルＢに比べ、モデルＡの反射損
失が大きくなっているが、これは第２の線路導体６ｂ
（２６ｂ）の長さによる共振の影響により、モデルＢの
反射損失が部分的に低減したものと考えられる。From the results shown in FIG. 6, the respective parts constituting the models A and B are made of the same material, and
Line conductor 6b (26b) portion, ground conductor layer 6c-B (2
6c-B) portion, the conductor layer 6d (26d) portion and the high resistance portion 8 (28) can be regarded as the same transmission loss. Therefore, the difference in the transmission loss between the models A and B is that the same plane ground conductor layer is used. It can be regarded as based on the presence or absence of 16. 12-15.
At 5 GHz, the reflection loss of the model A is larger than that of the model B, which is due to the second line conductor 6b.
It is considered that the reflection loss of the model B was partially reduced due to the influence of resonance due to the length of (26b).
【００５１】従って、本発明のモデルＡは、従来のモデ
ルＢに比べ、０〜２０ＧＨｚの周波数帯域の大部分で反
射特性に優れた良好な信号線路を構成することがわかっ
た。Therefore, it was found that the model A of the present invention constitutes a good signal line having excellent reflection characteristics in most of the frequency band of 0 to 20 GHz as compared with the conventional model B.
【００５２】これは、同一面接地導体層１６によって、
第２の線路導体６ｂの他端において第２の線路導体６ｂ
を伝送する終端用信号を接地させるための接地導体層６
ｃ−Ｂの面積を拡大できたため、第２の線路導体６ｂか
ら接地導体層６ｃ−Ｂに向けての終端用信号の伝送をス
ムーズに行なうことができ、第２の線路導体６ｂの他端
における終端用信号の反射が減少したためである。ま
た、第２の線路導体６ｂに略平行かつ取り囲むように同
一面接地導体層１６を設けたことで、第２の線路導体６
ｂから同一面接地導体層１６に終端用信号を空間を介し
て短絡させることができ、第２の線路導体６ｂにおいて
終端用信号を減衰させて確実に接地させたためである。
さらに、同一面接地導体層１６において枠体２に向けて
終端用信号を放射し易くなり、第２の線路導体６ｂの高
抵抗部８において接地しきれない終端用信号を放射し
て、終端用信号をより確実に接地したためである。This is due to the coplanar ground conductor layer 16.
At the other end of the second line conductor 6b, the second line conductor 6b
Conductor layer 6 for grounding the terminal signal for transmitting
Since the area of c-B can be expanded, the termination signal can be smoothly transmitted from the second line conductor 6b to the ground conductor layer 6c-B, and the other end of the second line conductor 6b can be provided. This is because the reflection of the termination signal is reduced. Further, since the same-plane ground conductor layer 16 is provided so as to be substantially parallel to and surround the second line conductor 6b, the second line conductor 6 is provided.
This is because the terminating signal can be short-circuited from b to the same-plane grounding conductor layer 16 through the space, and the terminating signal is attenuated in the second line conductor 6b to be surely grounded.
Furthermore, it becomes easier to radiate the terminating signal toward the frame 2 in the same-plane ground conductor layer 16, and the terminating signal that cannot be grounded is radiated in the high resistance portion 8 of the second line conductor 6b for terminating. This is because the signal was grounded more reliably.
【００５３】上述のように終端用信号を確実に接地する
ことができたため、終端用信号の反射特性が良好になっ
ていると考えられる。このような、終端用信号を確実に
接地することによる反射特性の向上は終端用信号の周波
数が高くなるほど重要である。Since the terminating signal could be reliably grounded as described above, it is considered that the reflection characteristics of the terminating signal are good. The improvement of the reflection characteristics by surely grounding the termination signal is more important as the frequency of the termination signal becomes higher.
【００５４】なお、本発明は上記実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲内であれば
種々の変更は可能である。The present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the present invention.
【００５５】[0055]
【発明の効果】本発明は、半導体パッケージ内に載置さ
れた回路基板は、その上面に、一端が半導体素子に電気
的に接続され他端が縁部に達しておりかつ途中に高抵抗
部を設けた接地用の線路導体が形成されているととも
に、線路導体を取り囲むように形成されかつ線路導体の
他端側に接続された同一面接地導体層が設けられ、下面
に接地導体層が形成されており、さらに線路導体の他端
から回路基板の端面および接地導体層にかけて導体層が
形成されていることにより、線路導体の他端において線
路導体を伝送する終端用信号を電気的に接地させるため
の接地導体層の面積を拡大できるため、線路導体から接
地導体に向けての終端用信号の伝送をスムーズに行なう
ことができ、線路導体の他端における終端用信号の反射
を有効に減少させることができる。According to the present invention, a circuit board mounted in a semiconductor package has, on its upper surface, one end electrically connected to a semiconductor element and the other end reaching an edge portion and a high resistance portion on the way. Is formed, and a ground conductor layer is formed so as to surround the line conductor and connected to the other end of the line conductor, and a ground conductor layer is formed on the lower surface. Further, since the conductor layer is formed from the other end of the line conductor to the end face of the circuit board and the ground conductor layer, the termination signal transmitted through the line conductor is electrically grounded at the other end of the line conductor. Since the area of the ground conductor layer can be increased, the signal for termination can be smoothly transmitted from the line conductor to the ground conductor, and the reflection of the signal for termination at the other end of the line conductor can be effectively reduced. Door can be.
【００５６】また、線路導体から同一面接地導体層に終
端用信号の高周波信号成分を空間および間隙を介して短
絡させることができ、線路導体において終端用信号を減
衰させて確実に接地させることができる。さらに、同一
面接地導体層において枠体に向けて高周波信号を放射し
易くなり、線路導体に設けられた高抵抗部において接地
しきれない終端用信号を放射することによってより確実
に接地することができる。Further, the high frequency signal component of the terminating signal can be short-circuited from the line conductor to the grounded conductor layer on the same plane through a space and a gap, and the terminating signal can be attenuated in the line conductor and reliably grounded. it can. Further, it becomes easier to radiate a high frequency signal toward the frame in the ground conductor layer on the same plane, and more reliable grounding can be achieved by radiating a termination signal that cannot be grounded in the high resistance portion provided in the line conductor. it can.
【００５７】従って、線路導体を伝わる終端用信号の反
射によるノイズが発生することを防止し、半導体素子を
正常に作動させることが可能になる。Therefore, it is possible to prevent the generation of noise due to the reflection of the termination signal transmitted through the line conductor, and to operate the semiconductor element normally.
【００５８】また、基体には半導体パッケージの製造過
程において反りが発生し、外部回路基板へねじ止めによ
って実装する際、この反りが矯正される。このため、従
来の基体上に載置固定された回路基板は反り矯正時に歪
が加わり破損する場合があったが、反りの矯正による歪
の影響が少ない枠体の棚部へ回路基板を設置することに
より、回路基板の破損を防止し、回路基板の線路導体で
高周波信号を伝送させることができるため、半導体素子
を正常に作動させることができる。Further, a warp occurs in the substrate during the manufacturing process of the semiconductor package, and this warp is corrected when the semiconductor substrate is mounted on the external circuit board by screwing. For this reason, the conventional circuit board mounted and fixed on the base body may be distorted due to distortion during the warp correction, but the circuit board is installed on the shelf of the frame body which is less affected by the distortion due to the warp correction. As a result, damage to the circuit board can be prevented and high-frequency signals can be transmitted by the line conductor of the circuit board, so that the semiconductor element can operate normally.
【００５９】本発明の半導体装置は、本発明の半導体素
子収納用パッケージと、棚部に設置された回路基板と、
載置部に載置されるとともに回路基板の線路導体の一端
に電気的に接続された半導体素子と、枠体の上面に接合
された蓋体とを具備したことにより、上記本発明の作用
効果を有する半導体パッケージを用いた信頼性の高い半
導体装置を提供できる。The semiconductor device of the present invention comprises a package for accommodating semiconductor elements of the present invention, a circuit board installed on a shelf,
Since the semiconductor element mounted on the mounting portion and electrically connected to one end of the line conductor of the circuit board and the lid body joined to the upper surface of the frame body are provided, the above-mentioned effects of the present invention It is possible to provide a highly reliable semiconductor device using the semiconductor package having the above.
【図１】本発明の半導体パッケージについて実施の形態
の例を示す断面図である。FIG. 1 is a cross-sectional view showing an example of an embodiment of a semiconductor package of the present invention.
【図２】本発明の半導体パッケージにおける回路基板の
要部拡大平面図である。FIG. 2 is an enlarged plan view of an essential part of a circuit board in the semiconductor package of the present invention.
【図３】従来の半導体パッケージの断面図である。FIG. 3 is a cross-sectional view of a conventional semiconductor package.
【図４】従来の半導体パッケージにおける回路基板の要
部拡大平面図である。FIG. 4 is an enlarged plan view of an essential part of a circuit board in a conventional semiconductor package.
【図５】（ａ）は本発明の半導体パッケージの回路基板
について実施の形態の例を示す解析モデルＡの平面図で
あり、（ｂ）は従来例の回路基板を示す解析モデルＢの
平面図である。5A is a plan view of an analysis model A showing an example of an embodiment of a circuit board of a semiconductor package of the present invention, and FIG. 5B is a plan view of an analysis model B showing a circuit board of a conventional example. Is.
【図６】図５の解析モデルＡ，Ｂの反射損失の解析結果
を示すグラフである。FIG. 6 is a graph showing the analysis result of the reflection loss of the analytical models A and B of FIG.
１：基体 １ａ：載置部 ２：枠体 ２ｂ：棚部 ４：蓋体 ５：半導体素子 ６：回路基板 ６ｂ：第２の線路導体 ６ｃ：接地導体層 ６ｄ：導体層 ８：高抵抗部 １６：同一面接地導体層 1: Base 1a: Placement part 2: Frame body 2b: Shelf 4: Lid 5: Semiconductor element 6: Circuit board 6b: Second line conductor 6c: Ground conductor layer 6d: conductor layer 8: High resistance part 16: Same-plane ground conductor layer
Claims (2)
載置部を有する基体と、前記上側主面の外周部に前記載
置部を囲繞するように接合され、内面に回路基板を設置
するための棚部を有する枠体とを具備した半導体素子収
納用パッケージにおいて、前記回路基板は、その上面
に、一端が前記半導体素子に電気的に接続され他端が縁
部に達しておりかつ途中に高抵抗部を設けた接地用の線
路導体が形成されているとともに、前記線路導体を取り
囲むように形成されかつ前記線路導体の他端側に接続さ
れた同一面接地導体層が設けられ、下面に接地導体層が
形成されており、さらに前記線路導体の他端から前記回
路基板の端面および前記接地導体層にかけて導体層が形
成されていることを特徴とする半導体素子収納用パッケ
ージ。1. A base body having a mounting portion for mounting a semiconductor element on an upper main surface, and an outer peripheral portion of the upper main surface are joined to surround the mounting portion, and a circuit board is provided on an inner surface. In a package for housing a semiconductor element, which includes a frame body having a shelf for installing, the circuit board has an upper surface, one end electrically connected to the semiconductor element and the other end reaching an edge. In addition, a line conductor for grounding having a high resistance portion is formed on the way, and a same-plane grounding conductor layer formed so as to surround the line conductor and connected to the other end side of the line conductor is provided. A package for storing semiconductor elements, wherein a ground conductor layer is formed on a lower surface, and a conductor layer is further formed from the other end of the line conductor to the end surface of the circuit board and the ground conductor layer.
ージと、前記棚部に設置された前記回路基板と、前記載
置部に載置されるとともに前記回路基板の線路導体の一
端に電気的に接続された前記半導体素子と、前記枠体の
上面に接合された蓋体とを具備したことを特徴とする半
導体装置。2. The package for accommodating a semiconductor element according to claim 1, the circuit board installed on the shelf portion, the electrical circuit mounted on the mounting portion and electrically connected to one end of a line conductor of the circuit board. A semiconductor device, comprising: the semiconductor element connected to the above; and a lid body joined to the upper surface of the frame body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001193744A JP3652278B2 (en) | 2001-06-26 | 2001-06-26 | Semiconductor element storage package and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001193744A JP3652278B2 (en) | 2001-06-26 | 2001-06-26 | Semiconductor element storage package and semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| JP2003007901A true JP2003007901A (en) | 2003-01-10 |
| JP3652278B2 JP3652278B2 (en) | 2005-05-25 |
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|---|---|---|---|
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002319645A (en) * | 2001-04-20 | 2002-10-31 | Kyocera Corp | Package for housing semiconductor element and semiconductor device |
| JP2002319644A (en) * | 2001-04-20 | 2002-10-31 | Kyocera Corp | Package for housing semiconductor element and semiconductor device |
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2001
- 2001-06-26 JP JP2001193744A patent/JP3652278B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002319645A (en) * | 2001-04-20 | 2002-10-31 | Kyocera Corp | Package for housing semiconductor element and semiconductor device |
| JP2002319644A (en) * | 2001-04-20 | 2002-10-31 | Kyocera Corp | Package for housing semiconductor element and semiconductor device |
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| Publication number | Publication date |
|---|---|
| JP3652278B2 (en) | 2005-05-25 |
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