JP2006128323A - Semiconductor device and storing package thereof - Google Patents

Semiconductor device and storing package thereof Download PDF

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Publication number
JP2006128323A
JP2006128323A JP2004313023A JP2004313023A JP2006128323A JP 2006128323 A JP2006128323 A JP 2006128323A JP 2004313023 A JP2004313023 A JP 2004313023A JP 2004313023 A JP2004313023 A JP 2004313023A JP 2006128323 A JP2006128323 A JP 2006128323A
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conductor
semiconductor element
circuit board
groove
line conductor
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Michinobu Iino
道信 飯野
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

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  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storing package for a semiconductor device and a semiconductor device having good transmission characteristics capable of preventing high frequency signal radiation by strengthening the grounding conductor of a circuit board. <P>SOLUTION: The storing package for a semiconductor device is provided with a base substrate 1 which has the placing part 1a of a semiconductor device 8, a frame 2 wherein a penetration hole 2a is formed in the side while comprising the insulator made to intervene between a perimeter conductor 3c and a central conductor, a coaxial connector 3 attached to the penetration hole 2a, and a circuit board wherein it is connected to the inside of the frame 2 of the upper surface of the base substrate 1 and a line conductor 6a is formed to which the end of the central conductor is connected electrically in the upper surface. The circuit board comprises a metal substrate 4 in the upper surface of which a groove is formed, and an insulating substrate wherein the line conductor 6a is formed in the upper surface along the groove while being attached to the groove. A notch is provided in the side of the groove in which it is located in the both sides of the connection part of the central conductor and the line conductor. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体素子収納用パッケージおよびそれを用いた半導体装置に関し、特に、高周波信号で作動する半導体素子を収納するための半導体素子収納用パッケージおよび半導体装置に関する。   The present invention relates to a semiconductor element storage package and a semiconductor device using the same, and more particularly to a semiconductor element storage package and a semiconductor device for storing a semiconductor element that operates with a high-frequency signal.

従来の光通信や無線通信分野に用いられる高周波用の各種半導体素子を収納する半導体素子収納用パッケージの断面図を図６に、その平面図を図７に、同軸コネクタと線路導体との接続部周辺の要部拡大断面図を図８に、その平面図を図９に、同軸コネクタの要部拡大断面図を図10に示す。これらの図において、101は基体、102は金属製の枠体、110は蓋体、Ｓ’は回路基板である。   FIG. 6 is a cross-sectional view of a package for housing semiconductor elements for housing various high-frequency semiconductor elements used in the conventional optical communication and wireless communication fields, FIG. 7 is a plan view thereof, and a connection portion between a coaxial connector and a line conductor. FIG. 8 is an enlarged cross-sectional view of the main part of the periphery, FIG. 9 is a plan view thereof, and FIG. 10 is an enlarged cross-sectional view of the main part of the coaxial connector. In these figures, 101 is a base, 102 is a metal frame, 110 is a lid, and S 'is a circuit board.

基体101は鉄（Ｆｅ）−ニッケル（Ｎｉ）−コバルト（Ｃｏ）合金や銅（Ｃｕ）−タングステン（Ｗ）等の金属から成る四角形状の板状体であり、その上側主面の載置部101ａには、ＩＣ，ＬＳＩ，半導体レーザ（ＬＤ），フォトダイオード（ＰＤ）等の半導体素子108を載置する酸化アルミニウム質焼結体（Ａｌ２Ｏ３）や窒化アルミニウム質焼結体（ＡｌＮ）などのセラミックスから成るサブマウント回路基板105が搭載固定されている。サブマウント回路基板105は載置部101ａにＡｇろう，Ａｇ−Ｃｕろう等のろう材や半田、樹脂接着剤によって接着固定される。また半導体素子108は、サブマウント回路基板105に、Ａｇろう，Ａｇ―Ｃｕろう等のろう材や半田、樹脂接着剤によって接着固定される。 The base 101 is a rectangular plate-like body made of a metal such as iron (Fe) -nickel (Ni) -cobalt (Co) alloy or copper (Cu) -tungsten (W), and a mounting portion on the upper main surface thereof. 101a includes an aluminum oxide sintered body (Al 2 O 3 ) and an aluminum nitride sintered body (AlN) on which a semiconductor element 108 such as an IC, LSI, semiconductor laser (LD), photodiode (PD), etc. is placed. A submount circuit board 105 made of ceramics is mounted and fixed. The submount circuit board 105 is bonded and fixed to the mounting portion 101a with a brazing material such as Ag brazing or Ag-Cu brazing, solder, or a resin adhesive. The semiconductor element 108 is bonded and fixed to the submount circuit board 105 with a brazing material such as Ag brazing or Ag—Cu brazing, solder, or a resin adhesive.

また、基体101の上側主面には回路基板Ｓ’が搭載されている。回路基板Ｓ’はＦｅ−Ｎｉ−Ｃｏ合金やＣｕ−Ｗ等の金属から成る金属基板104と絶縁基板106とから成る。金属基板104の上面には溝が形成されており、この溝に、上面に線路導体106ａが形成された絶縁基板106が嵌め込まれている。そして、絶縁基板106の下面に形成された接地導体106ｃおよび上面に形成された同一面接地導体106ｂが金属基板104と電気的に接続されることにより、金属基板104で接地電位をより安定化することができる。   A circuit board S ′ is mounted on the upper main surface of the base 101. The circuit board S 'includes a metal substrate 104 made of a metal such as an Fe-Ni-Co alloy or Cu-W, and an insulating substrate 106. A groove is formed on the upper surface of the metal substrate 104, and an insulating substrate 106 having a line conductor 106a formed on the upper surface is fitted into the groove. Then, the grounding conductor 106c formed on the lower surface of the insulating substrate 106 and the same-surface grounding conductor 106b formed on the upper surface are electrically connected to the metal substrate 104, thereby further stabilizing the ground potential at the metal substrate 104. be able to.

このような金属基板104は基体101や枠体102と一体形状もしくは、基体101や枠体102に、銀（Ａｇ）ろう，Ａｇ−銅（Ｃｕ）ろう等のろう材や半田、樹脂接着剤によって接着固定される。また、絶縁基板106も金属基板104へ同様に接着固定される。   Such a metal substrate 104 is integrally formed with the base body 101 and the frame body 102, or the base body 101 and the frame body 102 are made of brazing material such as silver (Ag) brazing, Ag-copper (Cu) brazing, solder, or resin adhesive. Bonded and fixed. The insulating substrate 106 is also bonded and fixed to the metal substrate 104 in the same manner.

そして、半導体素子108の電極は、絶縁基板106に被着されている線路導体106ａおよびその両側の同一面接地導体106ｂにそれぞれボンディングワイヤ107を介して電気的に接続されている。   The electrodes of the semiconductor element 108 are electrically connected to the line conductor 106a attached to the insulating substrate 106 and the same-surface ground conductor 106b on both sides thereof via bonding wires 107, respectively.

さらに、同一面接地導体106ｂは、絶縁基板106の裏面に被着されている接地導体106ｃと回路基板106内に形成されたスルーホール導体（図示せず）により電気的に接続されており、このように同一面接地導体106ｂをスルーホール導体（図示せず）を介して接地導体106ｃに接続することにより、回路基板Ｓ’は、高周波信号を伝送する線路導体106ａを接地用（グラウンド）導体となっている同一面接地導体106ｂ、接地導体106ｃが取り囲んだ形状のグラウンド付きコープレナー線路となっている。   Further, the same-surface ground conductor 106b is electrically connected to the ground conductor 106c attached to the back surface of the insulating substrate 106 by a through-hole conductor (not shown) formed in the circuit board 106. Thus, by connecting the ground conductor 106b on the same plane to the ground conductor 106c via a through-hole conductor (not shown), the circuit board S ′ can replace the line conductor 106a that transmits a high-frequency signal with the ground (ground) conductor. A grounded coplanar line surrounded by the same grounded conductor 106b and the grounded conductor 106c is formed.

このようなグラウンド付きコープレナー線路は高周波信号を伝送する線路導体106ａを接地導体が囲むような形状のため、高周波信号の放射が少なく、良好な伝送特性を示す。また半導体素子108に形成された配線構造も高周波信号を伝送する線路導体の両脇に同一面接地導体が形成されたグラウンド付きコープレナー線路であることが多いため、回路基板Ｓ’と半導体素子108の高周波伝播モードを同一のもの（グラウンド付きコープレナー線路）とすることで伝送損失を小さくしている。   Such a grounded coplanar line has a shape in which the ground conductor surrounds the line conductor 106a for transmitting a high-frequency signal, so that it emits less high-frequency signals and exhibits good transmission characteristics. Also, since the wiring structure formed in the semiconductor element 108 is often a grounded coplanar line in which ground conductors on the same plane are formed on both sides of a line conductor that transmits a high-frequency signal, the circuit board S ′ and the semiconductor element 108 are also formed. The transmission loss is reduced by using the same high-frequency propagation mode (coplanar line with ground).


基体101の上側主面の外周部には載置部101ａを囲むようにして枠体102が接合されており、枠体102の内側に半導体素子108を収容する空所を形成する。枠体102は、基体101と同様にＦｅ−Ｎｉ−Ｃｏ合金やＣｕ−Ｗの焼結材等から成り、基体101と一体成形されるか、基体101にＡｇろう，Ａｇ−Ｃｕろう等のろう材を介してろう付けされるか、またはシーム溶接法等の溶接法により接合されることによって、基体101の上側主面の外周部に設けられる。
A frame body 102 is joined to the outer peripheral portion of the upper main surface of the base body 101 so as to surround the mounting portion 101a, and a space for accommodating the semiconductor element 108 is formed inside the frame body 102. The frame 102 is made of an Fe—Ni—Co alloy, a Cu—W sintered material, or the like, similar to the base 101, and is integrally formed with the base 101, or is brazed to the base 101 such as Ag solder, Ag—Cu solder, or the like. It is provided on the outer peripheral portion of the upper main surface of the base 101 by being brazed through a material or joined by a welding method such as a seam welding method.

枠体102の側面には中心導体103ａ，誘電体103ｂ，外部導体103ｃが同心円状に配置された同軸構造の同軸コネクタ103が嵌着される貫通孔102ａが形成されており、貫通孔102ａ内に同軸コネクタ103を嵌め込むとともに半田等の封着材を貫通孔102ａ内の隙間に挿入し、しかる後、加熱して封着材を溶融させ、溶融した封着材を毛細管現象により同軸コネクタ103と貫通孔102ａの内壁との隙間に充填させることによって、同軸コネクタ103が貫通孔102ａ内に封着材を介して嵌着接合される。   A through hole 102a into which a coaxial connector 103 having a coaxial structure in which a central conductor 103a, a dielectric 103b, and an outer conductor 103c are concentrically arranged is fitted is formed on a side surface of the frame 102, and the through hole 102a is formed in the through hole 102a. The coaxial connector 103 is fitted and a sealing material such as solder is inserted into the gap in the through hole 102a, and then heated to melt the sealing material, and the molten sealing material is connected to the coaxial connector 103 by capillary action. By filling the gap with the inner wall of the through hole 102a, the coaxial connector 103 is fitted and joined into the through hole 102a via a sealing material.

同軸コネクタ103は、図10に示すように、Ｆｅ−Ｎｉ−Ｃｏ合金等の金属から成る外部導体103ｃ内にホウケイ酸ガラスなどから成る誘電体103ｂを介してＦｅ−Ｎｉ−Ｃｏ合金から成る信号線路としての中心導体103ａが挿通され、誘電体103ｂを加熱し、溶融することにより中心導体103ａが外部導体103ｃに固定されている。   As shown in FIG. 10, the coaxial connector 103 is a signal line made of Fe—Ni—Co alloy via a dielectric 103b made of borosilicate glass in an outer conductor 103c made of metal such as Fe—Ni—Co alloy. The central conductor 103a is fixed to the external conductor 103c by inserting and melting the dielectric 103b and melting the dielectric 103b.

中心導体103ａの一端は、半田等から成る導電性接着材を介して高周波用の回路基板Ｓ’の線路導体106ａに電気的に接続される。そして、中心導体103ａの他端に、外部電気回路（図示せず）に接続された同軸ケーブル（図示せず）の中心導体が装着されることによって内部に収納された半導体素子108が同軸コネクタ103の中心導体103ａを介して外部電気回路に電気的に接続されることとなる。   One end of the center conductor 103a is electrically connected to the line conductor 106a of the circuit board S 'for high frequency via a conductive adhesive made of solder or the like. The other end of the center conductor 103a is fitted with a center conductor of a coaxial cable (not shown) connected to an external electric circuit (not shown), so that the semiconductor element 108 housed therein is connected to the coaxial connector 103. It is electrically connected to an external electric circuit through the central conductor 103a.

最後に、枠体102の内側の載置部101ａに半導体素子108をサブマウント回路基板105を介して載置し、枠体102の上面に蓋体110をろう付け法やシームウエルド法等の溶接法により接合し、半導体素子収納用パッケージ内を気密に封止することによって製品としての半導体装置となる。
特開２００２−３１９６４５号公報 Finally, the semiconductor element 108 is mounted on the mounting portion 101a inside the frame body 102 via the submount circuit board 105, and the lid body 110 is welded to the upper surface of the frame body 102 by a brazing method, a seam weld method, or the like. The semiconductor device as a product is obtained by bonding by the method and hermetically sealing the inside of the semiconductor element storage package.
JP 2002-319645 A

しかしながら、従来の回路基板106を使用した半導体素子収納用パッケージにおいては、高周波用途になるにつれ、同一面接地導体106ｂと接地導体106ｃとを導通させているスルーホール導体同士の隙間から高周波信号が放射しやすくなり、良好な高周波特性を満たさず、半導体素子108が誤動作するという問題が生じてきた。   However, in a package for housing a semiconductor element using a conventional circuit board 106, a high-frequency signal is radiated from a gap between through-hole conductors that conduct the same-surface ground conductor 106b and the ground conductor 106c as it becomes a high-frequency application. As a result, there is a problem that the semiconductor element 108 malfunctions without satisfying good high frequency characteristics.

また、同軸コネクタ103の中心導体103ａと回路基板Ｓ’の線路導体106ａとの接続部における伝送損失が大きくなるという問題も生じてきた。   In addition, there has been a problem that transmission loss at the connection portion between the central conductor 103a of the coaxial connector 103 and the line conductor 106a of the circuit board S 'increases.

本発明は上記問題点に鑑み完成されたものであり、その目的は、回路基板Ｓ’の接地導体の強化により高周波信号が放射するのを防ぐことが可能で、かつ良好な伝送特性を有する半導体素子収納用パッケージおよび半導体装置を提供することにある。   The present invention has been completed in view of the above problems, and an object of the present invention is to provide a semiconductor that can prevent high-frequency signals from being radiated by reinforcing the grounding conductor of the circuit board S ′ and has good transmission characteristics. An object is to provide an element storage package and a semiconductor device.

本発明の半導体素子収納用パッケージは、上側主面の半導体素子の載置部を有する基体と、該基体の上側主面に前記載置部を取り囲むように接合され、側部に貫通孔が形成された枠体と、筒状の外周導体およびその中心軸に設置された中心導体ならびにそれらの間に介在させた絶縁体から成るとともに前記貫通孔に嵌着された同軸コネクタと、前記基体の上面の前記枠体の内側に接合され、上面に前記中心導体の端部が電気的に接続された線路導体が形成されている回路基板とを具備した半導体素子収納用パッケージにおいて、前記回路基板は、上面に溝が形成された金属基板と、該溝に嵌着されるとともに上面に前記溝に沿って前記線路導体が形成された絶縁基板とから成り、前記中心導体と前記線路導体との接続部の両側に位置する前記溝の側面に切り欠き部を設けたことを特徴とするものである。   The semiconductor element storage package of the present invention is bonded to a base body having a semiconductor element mounting portion on the upper main surface, and is joined to the upper main surface of the base body so as to surround the mounting portion, and a through hole is formed in the side portion. A frame-shaped frame body, a cylindrical outer peripheral conductor, a central conductor installed on the central axis thereof, an insulator interposed therebetween, and a coaxial connector fitted into the through-hole, and an upper surface of the base body A circuit board that is joined to the inside of the frame body and has a circuit board on which an end portion of the central conductor is electrically connected is formed on the upper surface. A metal substrate having a groove formed on the upper surface, and an insulating substrate fitted in the groove and having the line conductor formed along the groove on the upper surface, the connecting portion between the central conductor and the line conductor Located on both sides of the In which characterized in that a notch portion of the side surface.

また、本発明の半導体素子収納用パッケージにおいて、好ましくは、前記切り欠き部が前記回路基板の前記同軸コネクタ側端部よりも内側に位置していることを特徴とするものである。   Moreover, in the package for housing a semiconductor element of the present invention, it is preferable that the notch portion is located on the inner side of the end portion on the coaxial connector side of the circuit board.

また、本発明の半導体素子収納用パッケージにおいて、好ましくは、前記切り欠き部の内面が平面視して円弧状であることを特徴とするものである。   In the package for housing a semiconductor element of the present invention, it is preferable that the inner surface of the notch is arcuate in plan view.

本発明の半導体装置は、上記本発明の半導体素子収納用パッケージと、前記載置部に載置された半導体素子と、前記枠体の上面に前記半導体素子を覆うように取着された蓋体とを具備していることを特徴とするものである。   The semiconductor device according to the present invention includes a package for housing a semiconductor element according to the present invention, a semiconductor element placed on the mounting portion, and a lid attached to an upper surface of the frame so as to cover the semiconductor element. It is characterized by comprising.

本発明の半導体素子収納用パッケージによれば、回路基板は、上面に溝が形成された金属基板と、溝に嵌着されるとともに上面に溝に沿って線路導体が形成された絶縁基板とから成り、同軸コネクタの中心導体と線路導体との接続部の両側に位置する溝の側面に切り欠き部を設けたことから、従来のような一定間隔のスルーホール導体を用いた場合と異なり、線路導体の両側から下側にかけて連続するとともに厚い接地層（グラウンド）を形成することができ、接地層が強化され、高周波信号の放射を少なくすることができる結果、10ＧＨｚ以上の高周波においても回路基板における高周波信号の放射が少なく、良好な伝送特性が実現でき、半導体素子を正常に作動させることができる。   According to the package for housing a semiconductor element of the present invention, the circuit board includes: a metal substrate having a groove formed on the upper surface; and an insulating substrate fitted in the groove and having a line conductor formed on the upper surface along the groove. Unlike the case of using a through-hole conductor with a constant interval unlike the conventional case, because the notch is provided on the side surface of the groove located on both sides of the connection portion between the central conductor of the coaxial connector and the line conductor, the line A continuous and thick ground layer (ground) can be formed from both sides to the lower side of the conductor, and the ground layer can be strengthened to reduce radiation of high-frequency signals. As a result, even at high frequencies of 10 GHz or higher, High-frequency signal radiation is low, good transmission characteristics can be realized, and semiconductor elements can be operated normally.

また、同軸コネクタの中心導体と線路導体との接続部の両側に位置する溝の側面に切り欠き部を設けることにより、中心導体と線路導体との接合部にて発生する容量成分を低減し、接合部における急激な特性インピーダンスの変化を少なくすることが可能となる。   In addition, by providing a notch on the side surface of the groove located on both sides of the connection between the central conductor and the line conductor of the coaxial connector, the capacitance component generated at the joint between the central conductor and the line conductor is reduced. It is possible to reduce a sudden change in characteristic impedance at the junction.

また、本発明の半導体素子収納用パッケージによれば、切り欠き部が回路基板の同軸コネクタ側端部よりも内側に位置していることから、中心導体と線路導体との接合部よりも同軸コネクタ側の回路基板の端部で金属基板の溝の開口縁を線路導体に近づけ、この端部付近の中心導体に対して金属基板によって接地電位の強化を行ない、線路導体と同じような電磁界雰囲気を形成することができる。よって、中心導体と線路導体との接合部において生じる、中心導体の同軸構造の伝播モードから線路導体のマイクロストリップ構造の伝播モードへの急激な変化、または線路導体の伝播モードから中心導体の伝播モードへの急激な変化をこの端部で緩和して、伝送損失が生じるのを有効に防止できる。   Further, according to the package for housing a semiconductor element of the present invention, since the notch portion is located on the inner side of the coaxial connector side end portion of the circuit board, the coaxial connector rather than the joint portion between the center conductor and the line conductor. At the edge of the circuit board on the side, the opening edge of the groove of the metal board is brought close to the line conductor, and the ground potential is strengthened by the metal board to the central conductor near this edge, and the electromagnetic field atmosphere is similar to that of the line conductor Can be formed. Therefore, a sudden change from the propagation mode of the coaxial structure of the center conductor to the propagation mode of the microstrip structure of the line conductor, or the propagation mode of the center conductor to the propagation mode of the center conductor, which occurs at the joint between the center conductor and the line conductor. It is possible to effectively prevent a transmission loss from occurring by relieving a sudden change in the distance at this end.

また、本発明の半導体素子収納用パッケージによれば、切り欠き部の内面が平面視して円弧状であることから、中心導体の伝播モードと線路導体の伝播モード間の急激な伝播モードの変化をより緩やかにすることができ、伝送特性をより有効に向上できる。   Further, according to the semiconductor element storage package of the present invention, since the inner surface of the notch is arcuate in plan view, a sudden change in the propagation mode between the propagation mode of the center conductor and the propagation mode of the line conductor is achieved. Can be made more gradual, and transmission characteristics can be improved more effectively.

また、本発明の半導体装置によれば、上記本発明の半導体素子収納用パッケージと、載置部に載置された半導体素子と、枠体の上面に半導体素子を覆うように取着された蓋体とを具備していることから、回路基板における高周波信号の放射が少なく、良好な電気特性を示す半導体装置となる。   According to the semiconductor device of the present invention, the semiconductor element storage package of the present invention, the semiconductor element mounted on the mounting portion, and the lid attached to the upper surface of the frame so as to cover the semiconductor element Therefore, a semiconductor device having good electrical characteristics can be obtained with less emission of high-frequency signals from the circuit board.

本発明の半導体素子収納用パッケージについて以下に詳細に説明する。図１は本発明の半導体素子収納用パッケージの実施の形態の一例を示す断面図であり、図２はその平面図である。また、図３は図１，２の半導体素子収納用パッケージの同軸コネクタと線路導体との接続部周辺の要部拡大断面図であり、図４はその平面図である。さらに、図５は図１，２の半導体素子収納用パッケージの同軸コネクタの断面図である。これらの図において、１は基体、２は枠体、10は蓋体、Ｓは回路基板を示す。   The semiconductor element storage package of the present invention will be described in detail below. FIG. 1 is a sectional view showing an example of an embodiment of a package for housing a semiconductor element of the present invention, and FIG. 2 is a plan view thereof. 3 is an enlarged cross-sectional view of the main part around the connection portion between the coaxial connector and the line conductor of the semiconductor element housing package of FIGS. 1 and 2, and FIG. 4 is a plan view thereof. FIG. 5 is a cross-sectional view of the coaxial connector of the semiconductor element storage package of FIGS. In these drawings, 1 is a base, 2 is a frame, 10 is a lid, and S is a circuit board.

そして、本発明の半導体素子収納用パッケージは、基体１の上側主面に載置部１ａを有し、この載置部１ａに直接あるいはサブマウント基板５を介して半導体素子８が載置される。また、基体１の上側主面には回路基板Ｓが載置されている。   The semiconductor element storage package of the present invention has a mounting portion 1 a on the upper main surface of the base 1, and the semiconductor element 8 is mounted on the mounting portion 1 a directly or via the submount substrate 5. . A circuit board S is placed on the upper main surface of the base 1.

基体１は、Ｆｅ−Ｎｉ−Ｃｏ合金等の金属やＣｕ−Ｗの焼結材等の金属から成り、四角板状体のものである。基体１は、Ｆｅ−Ｎｉ−Ｃｏ合金等やＣｕ−Ｗの焼結材等のインゴットに圧延加工や打ち抜き加工等の従来周知の金属加工法、または切削加工等を施すことによって、所定の形状に製作される。   The substrate 1 is made of a metal such as an Fe—Ni—Co alloy or a metal such as a sintered material of Cu—W, and has a rectangular plate shape. The base body 1 is formed into a predetermined shape by subjecting an ingot such as a Fe—Ni—Co alloy or the like or a sintered material of Cu—W to a conventionally known metal processing method such as rolling or punching or cutting. Produced.

基体１の上側主面のほぼ中央部の載置部１ａには、半導体素子８を搭載したサブマウント回路基板５が、例えばＡｇろう，Ａｇ−Ｃｕろう等のろう材やＡｕ−Ｓｎ半田，Ｐｂ−Ｓｎ半田等の半田、樹脂系接着剤を介して接着固定される。あるいは、載置部１ａに半導体素子８が、例えばＡｇろう，Ａｇ−Ｃｕろう等のろう材やＡｕ−Ｓｎ半田，Ｐｂ−Ｓｎ半田等の半田、樹脂系接着剤を介して直接接着固定される。   A submount circuit board 5 on which a semiconductor element 8 is mounted is mounted on a mounting portion 1a at a substantially central portion of the upper main surface of the substrate 1, for example, a brazing material such as Ag brazing or Ag-Cu brazing, Au-Sn solder, Pb, etc. -It is bonded and fixed via a solder such as Sn solder or a resin adhesive. Alternatively, the semiconductor element 8 is directly bonded and fixed to the mounting portion 1a via, for example, a brazing material such as Ag brazing or Ag—Cu brazing, solder such as Au—Sn solder or Pb—Sn solder, or a resin adhesive. .

さらに、基体１の上側主面には回路基板Ｓが例えばＡｇろう，Ａｇ−Ｃｕろう等のろう材やＡｕ−Ｓｎ半田，Ｐｂ−Ｓｎ半田等の半田、樹脂系接着剤を介して接着固定されている。回路基板Ｓは金属基板４と絶縁基板６とから成る。金属基板４は上面に溝が形成されており、この溝に、上面に線路導体６ａが形成された絶縁基板６が嵌め込まれている。そして、絶縁基板６の下面に形成された接地導体６ｃが金属基板４と電気的に接続されることにより、金属基板４で接地電位をより安定化することができる。   Further, the circuit board S is bonded and fixed to the upper main surface of the base 1 through a brazing material such as Ag brazing, Ag-Cu brazing, solder such as Au-Sn solder, Pb-Sn solder, or a resin adhesive. ing. The circuit board S includes a metal substrate 4 and an insulating substrate 6. A groove is formed on the upper surface of the metal substrate 4, and an insulating substrate 6 having a line conductor 6 a formed on the upper surface is fitted in the groove. The ground conductor 6 c formed on the lower surface of the insulating substrate 6 is electrically connected to the metal substrate 4, whereby the ground potential can be further stabilized by the metal substrate 4.

半導体素子８の電極は、絶縁基板６の上面に被着形成されている線路導体６ａおよび金属基板４にそれぞれボンディングワイヤ７を介して電気的に接続される。   The electrodes of the semiconductor element 8 are electrically connected to the line conductor 6 a and the metal substrate 4 formed on the upper surface of the insulating substrate 6 via bonding wires 7.

サブマウント回路基板５や絶縁基板６は、例えばアルミナ（Ａｌ２Ｏ３）質セラミックスや窒化アルミニウム（ＡｌＮ）質セラミックスから成り、アルミナ質セラミックスから成る場合、以下のようにして作製される。 The submount circuit board 5 and the insulating substrate 6 are made of, for example, alumina (Al 2 O 3 ) ceramics or aluminum nitride (AlN) ceramics.

まず、アルミナ（Ａｌ２Ｏ３），酸化珪素（ＳｉＯ２），酸化カルシウム（ＣａＯ），酸化マグネシウム（ＭｇＯ）等の原料粉末に適当な有機バインダや可塑剤，分散剤，溶剤等を添加混合して泥漿状となす。これを従来周知のドクターブレード法等でシート状となすことによってセラミックグリーンシートを得、これを切断加工したものを積層するか、または、Ａｌ２Ｏ３，ＳｉＯ２，ＣａＯ，ＭｇＯ等の原料粉末に適当な可塑剤や分散剤，溶剤等を添加混合して金型に充填し、プレス成型することによって、所定形状のセラミック成形体を得る。しかる後、このセラミック成形体に適当な打ち抜き加工を施して得た四角平板状等の板体の上面に線路導体６ａ、および下面に接地導体６ｃとなる金属ペーストを印刷塗布し、還元雰囲気中で約1600℃の温度で焼成することによって製作される。 First, an appropriate organic binder, plasticizer, dispersant, solvent, etc. are added to and mixed with raw material powders such as alumina (Al 2 O 3 ), silicon oxide (SiO 2 ), calcium oxide (CaO), and magnesium oxide (MgO). To make a mud. A ceramic green sheet is obtained by making this into a sheet by a conventionally known doctor blade method or the like, and the cut green powder is laminated, or raw material powder such as Al 2 O 3 , SiO 2 , CaO, MgO An appropriate plasticizer, dispersant, solvent, etc. are added to and mixed into a mold and press-molded to obtain a ceramic molded body having a predetermined shape. Thereafter, a metal paste to be the line conductor 6a and the ground conductor 6c is printed on the upper surface of a square plate-like plate body obtained by performing an appropriate punching process on the ceramic molded body, and in a reducing atmosphere. Manufactured by firing at a temperature of about 1600 ° C.

このような線路導体６ａ，接地導体６ｃとなる金属ペーストはタングステン（Ｗ），モリブデン（Ｍｏ），マンガン（Ｍｎ）等の高融点金属粉末に適当な有機バインダや添加剤，溶剤等を添加混合してペースト状となしたものから成る。   The metal paste used as the line conductor 6a and the ground conductor 6c is obtained by adding and mixing an appropriate organic binder, additive, solvent, etc. with a high melting point metal powder such as tungsten (W), molybdenum (Mo), manganese (Mn). Made of paste.

なお、線路導体６ａ，接地導体６ｃは薄膜形成法によって形成されていても良く、その場合、線路導体６ａ，接地導体６ｃは、窒化タンタル（Ｔａ２Ｎ），ニクロム（Ｎｉ−Ｃｒ）合金，チタン（Ｔｉ），パラジウム（Ｐｄ），白金（Ｐｔ），金（Ａｕ）等から形成され、セラミックグリーンシートを焼成した後に従来周知の真空蒸着成膜法等によって形成される。 The line conductor 6a and the ground conductor 6c may be formed by a thin film forming method. In this case, the line conductor 6a and the ground conductor 6c are tantalum nitride (Ta 2 N), nichrome (Ni—Cr) alloy, titanium. It is made of (Ti), palladium (Pd), platinum (Pt), gold (Au) or the like, and is formed by a conventionally known vacuum deposition method or the like after firing the ceramic green sheet.

また、基体１の上側主面の外周部には載置部１ａを囲むようにして枠体２が接合されており、枠体２は、その内側に半導体素子８を収容する空所を形成する。この枠体２は、基体１と同様にＦｅ−Ｎｉ−Ｃｏ合金やＣｕ−Ｗの焼結材等から成り、基体１と一体成形されるか、または基体１にＡｇろう等のろう材を介してろう付けされるか、またはシーム溶接法等の溶接法により接合されることによって、基体１の上側主面の外周部に設けられる。   Further, a frame body 2 is joined to the outer peripheral portion of the upper main surface of the base body 1 so as to surround the mounting portion 1a, and the frame body 2 forms a space for accommodating the semiconductor element 8 inside thereof. The frame 2 is made of a Fe—Ni—Co alloy, a Cu—W sintered material, or the like in the same manner as the base 1 and is formed integrally with the base 1 or via a brazing material such as Ag brazing. It is provided on the outer peripheral portion of the upper main surface of the base 1 by being brazed or joined by a welding method such as a seam welding method.

なお、枠体２は上記のような金属の他にセラミックス等の誘電体材料から成っていてもよく、その表面や内部にメタライズ層等の導体層が形成されていてもよい。   The frame body 2 may be made of a dielectric material such as ceramics in addition to the metal as described above, and a conductor layer such as a metallized layer may be formed on the surface or inside thereof.

また、外部より半導体素子８に駆動信号等を入力させる入出力端子としての同軸コネクタ３が設けられる。このような同軸コネクタ３は、中心導体３ａ，誘電体３ｂ，外部導体３ｃが同心円状に配置された同軸構造から成り、この同軸コネクタ３を枠体２に形成された貫通孔２ａに嵌め込むとともにＡｕ−Ｓｎ半田やＰｂ−Ｓｎ半田等の封着材を貫通孔２ａとの隙間に挿入し、しかる後、封着材を加熱して溶融させ、溶融した封着材を毛細管現象により同軸コネクタ３と貫通孔２ａの内壁との隙間に充填することによって、同軸コネクタ３が貫通孔２ａ内に半田等の封着材を介して嵌着接合される。   A coaxial connector 3 is provided as an input / output terminal for inputting a drive signal or the like to the semiconductor element 8 from the outside. Such a coaxial connector 3 has a coaxial structure in which a center conductor 3a, a dielectric 3b, and an outer conductor 3c are arranged concentrically, and the coaxial connector 3 is fitted into a through hole 2a formed in the frame body 2. A sealing material such as Au-Sn solder or Pb-Sn solder is inserted into the gap between the through holes 2a, and then the sealing material is heated and melted. The melted sealing material is connected to the coaxial connector 3 by capillary action. By filling the gap between the through hole 2a and the inner wall of the through hole 2a, the coaxial connector 3 is fitted and joined into the through hole 2a via a sealing material such as solder.

同軸コネクタ３は、Ｆｅ−Ｎｉ−Ｃｏ合金等の金属から成る円筒形等の筒状の外周導体３ｃの内側にガラス等の絶縁体３ｂが充填され、さらに、中心軸にＦｅ−Ｎｉ−Ｃｏ合金等の金属から成る中心導体３ａが固定される。そして、この中心導体３ａは、その先端部が半田等から成る導電性接着材９を介して回路基板Ｓの線路導体６ａに電気的に接続される。この中心導体３ａおよび筒状の外周導体３ｃに同軸ケーブルが装着されることによって、半導体素子収納用パッケージの内部に収納された半導体素子８が中心導体３ａを介して外部電気回路に電気的に接続されることとなる。   In the coaxial connector 3, an insulator 3b such as glass is filled inside a cylindrical outer conductor 3c made of a metal such as an Fe—Ni—Co alloy, and the central axis is further Fe—Ni—Co alloy. A central conductor 3a made of metal such as is fixed. The center conductor 3a is electrically connected to the line conductor 6a of the circuit board S via a conductive adhesive 9 whose tip is made of solder or the like. By attaching a coaxial cable to the center conductor 3a and the cylindrical outer conductor 3c, the semiconductor element 8 housed in the semiconductor element housing package is electrically connected to an external electric circuit via the center conductor 3a. Will be.

そして、本発明の半導体素子収納用パッケージにおける金属基板４においては、線路導体６ａと同軸コネクタ３の中心導体３ａとが接続される箇所の側面に切り欠き部４ａを設けている。これにより、従来のような一定間隔のスルーホール導体を用いた場合と異なり、線路導体６ａの両側から下側にかけて連続するとともに厚い接地層（グラウンド）を形成することができ、接地層が強化され、高周波信号の放射を少なくすることができる結果、10ＧＨｚ以上の高周波においても回路基板Ｓにおける高周波信号の放射が少なく、良好な伝送特性が実現でき、半導体素子８を正常に作動させることができる。   And in the metal substrate 4 in the package for housing semiconductor elements of the present invention, a notch 4a is provided on the side surface of the location where the line conductor 6a and the central conductor 3a of the coaxial connector 3 are connected. This makes it possible to form a thick ground layer (ground) that is continuous from both sides to the lower side of the line conductor 6a, unlike the conventional case where through-hole conductors with a constant interval are used, and the ground layer is strengthened. As a result, the radiation of the high-frequency signal can be reduced. As a result, the radiation of the high-frequency signal on the circuit board S is small even at a high frequency of 10 GHz or higher, and good transmission characteristics can be realized.

また、同軸コネクタ３の中心導体３ａと線路導体６ａとの接続部の両側に位置する溝の側面に切り欠き部４ａを設けることにより、中心導体３ａと線路導体６ａとの接合部にて発生する容量成分を低減し、接合部における急激な特性インピーダンスの変化を少なくすることが可能となる。   Further, by providing a notch 4a on the side surface of the groove located on both sides of the connecting portion between the central conductor 3a and the line conductor 6a of the coaxial connector 3, it is generated at the junction between the central conductor 3a and the line conductor 6a. Capacitance components can be reduced, and sudden changes in characteristic impedance at the junction can be reduced.

なお、絶縁基板６の上面が位置している平面内において、線路導体６ａと切り欠き部４ａの内面との間隔は、同一平面内における切り欠き部４ａ以外の部位での線路導体６ａと金属基板４の溝の側面との間隔の1.7〜10倍であるのがよい。1.7倍未満であると、中心導体３ａと線路導体６ａとの接続部での急激な特性インピーダンスの変化を少なくする効果が小さくなりやすい。また、10倍を超えると、中心導体３ａと線路導体６ａとの接続部での接地電位の強化ができず、伝送特性が低下しやすくなる。   Note that, in the plane where the upper surface of the insulating substrate 6 is located, the distance between the line conductor 6a and the inner surface of the notch 4a is such that the line conductor 6a and the metal substrate at a portion other than the notch 4a in the same plane. It should be 1.7 to 10 times the distance from the side surface of the groove 4. If it is less than 1.7 times, the effect of reducing a sudden change in characteristic impedance at the connecting portion between the center conductor 3a and the line conductor 6a tends to be small. On the other hand, if it exceeds ten times, the ground potential at the connecting portion between the center conductor 3a and the line conductor 6a cannot be strengthened, and the transmission characteristics are likely to deteriorate.

また、切り欠き部４ａは金属基板４の溝の上端から下端にかけて形成されていてもよく、上面から溝の中央部まででもよい。さらに切り欠き部４ａの深さ（溝の側面に直交する方向の深さ）は下側に行くにともなって浅くなっていてもよい。   Further, the notch 4a may be formed from the upper end to the lower end of the groove of the metal substrate 4, or from the upper surface to the center of the groove. Further, the depth of the notch 4a (depth in the direction orthogonal to the side surface of the groove) may become shallower as it goes downward.

好ましくは、切り欠き部４ａが回路基板Ｓの同軸コネクタ３側の端部よりも内側に位置しているのがよい。これにより、中心導体３ａと線路導体６ａとの接合部よりも同軸コネクタ３側の回路基板Ｓの端部で金属基板４の溝の開口縁を線路導体６ａに近づけ、この端部付近の中心導体３ａに対して金属基板４によって接地電位の強化を行ない、線路導体６ａと同じような電磁界雰囲気を形成することができる。よって、中心導体３ａと線路導体６ａとの接合部において生じる、中心導体３ａの同軸構造の伝播モードから線路導体６ａのマイクロストリップ構造の伝播モードへの急激な変化、または線路導体６ａの伝播モードから中心導体３ａの伝播モードへの急激な変化をこの端部で緩和して、伝送損失が生じるのを有効に防止できる。   Preferably, the cutout portion 4a is located inside the end portion of the circuit board S on the coaxial connector 3 side. As a result, the opening edge of the groove of the metal substrate 4 is brought closer to the line conductor 6a at the end of the circuit board S closer to the coaxial connector 3 than the joint between the center conductor 3a and the line conductor 6a. The ground potential is enhanced by the metal substrate 4 with respect to 3a, and an electromagnetic field atmosphere similar to the line conductor 6a can be formed. Therefore, from the sudden change from the propagation mode of the coaxial structure of the center conductor 3a to the propagation mode of the microstrip structure of the line conductor 6a, which occurs at the junction between the center conductor 3a and the line conductor 6a, or from the propagation mode of the line conductor 6a. A sudden change to the propagation mode of the center conductor 3a can be mitigated at this end portion, and transmission loss can be effectively prevented.

このように切り欠き部４ａが回路基板Ｓの同軸コネクタ３側の端部よりも内側に位置している場合、切り欠き部４ａと回路基板Ｓの同軸コネクタ３側の端部との距離は0.4〜４ｍｍであるのがよい。0.4ｍｍ未満であると、回路基板Ｓの同軸コネクタ３側の端部付近の中心導体３ａに対して金属基板４によって接地電位の強化を行ない、線路導体６ａと同じような電磁界雰囲気を形成しにくくなる。また、４ｍｍを超えると中心導体３ａの露出部が長くなり、この露出部から放射損失が生じやすくなる。   Thus, when the notch 4a is located inside the end on the coaxial connector 3 side of the circuit board S, the distance between the notch 4a and the end on the coaxial connector 3 side of the circuit board S is 0.4. It should be ~ 4 mm. If it is less than 0.4 mm, the ground potential is reinforced by the metal substrate 4 with respect to the central conductor 3a near the end of the circuit board S on the coaxial connector 3 side, and an electromagnetic field atmosphere similar to the line conductor 6a is formed. It becomes difficult. On the other hand, if it exceeds 4 mm, the exposed portion of the center conductor 3a becomes long, and radiation loss is likely to occur from this exposed portion.

また、好ましくは、切り欠き部４ａの内面が平面視して円弧状であるのがよい。これにより、中心導体３ａの伝播モードと線路導体６ａの伝播モード間の急激な伝播モードの変化をより緩やかにすることができ、伝送特性をより有効に向上できる。   Preferably, the inner surface of the cutout 4a is arcuate in plan view. Thereby, the rapid change of the propagation mode between the propagation mode of the center conductor 3a and the propagation mode of the line conductor 6a can be made more gradual, and the transmission characteristics can be improved more effectively.

そして、上記本発明の半導体素子収納用パッケージの載置部１ａに半導体素子８を載置し、枠体２の上面に半導体素子８を覆うように蓋体10を取着して、半導体素子８を気密に封止することにより本発明の半導体装置となる。これにより、伝送特性に優れる上記本発明の半導体素子収納用パッケージを用いたことから、回路基板Ｓにおける高周波信号の放射が少なく、良好な電気特性を示す半導体装置となる。   Then, the semiconductor element 8 is mounted on the mounting portion 1a of the semiconductor element storage package of the present invention, and the lid body 10 is attached to the upper surface of the frame 2 so as to cover the semiconductor element 8. Is hermetically sealed to provide a semiconductor device of the present invention. As a result, since the semiconductor element housing package of the present invention having excellent transmission characteristics is used, a semiconductor device exhibiting good electrical characteristics with less emission of high-frequency signals in the circuit board S is obtained.

本発明の半導体素子収納用パッケージの回路基板Ｓを以下のように構成し、高周波３次元構造シミュレータ（アンソフト社製HFSS（High Frequency Structure Simulator））を用いて１ＧＨｚ〜15ＧＨｚの反射係数Ｓ11をシミュレーションにより評価した。   The circuit board S of the semiconductor element storage package of the present invention is configured as follows, and a reflection coefficient S11 of 1 GHz to 15 GHz is simulated using a high-frequency three-dimensional structure simulator (HFSS (High Frequency Structure Simulator manufactured by Ansoft)). It was evaluated by.

まず、絶縁基板６は、比誘電率が9.6のアルミナセラミックスからなる縦２ｍｍ×横0.98ｍｍ×厚さ0.5ｍｍの基板とし、その上側主面中央部に、幅0.38ｍｍ×長さ２ｍｍ×厚さ0.002ｍｍの線路導体６aを、絶縁基板６の裏面には絶縁基板６と同一の面積である縦２ｍｍ×横0.98ｍｍ×厚さ0.002ｍｍの接地導体６ｃを配置した。   First, the insulating substrate 6 is a substrate made of alumina ceramics having a relative dielectric constant of 9.6, which is 2 mm long × 0.98 mm wide × 0.5 mm thick, and has a width 0.38 mm × length 2 mm × thickness at the center of the upper main surface thereof. A line conductor 6a of 0.002 mm was disposed on the back surface of the insulating substrate 6 and a grounding conductor 6c having the same area as the insulating substrate 6 and a length of 2 mm × width of 0.98 mm × thickness of 0.002 mm.

次に上面に絶縁基板６嵌め込むための絶縁基板６と同じ大きさの溝を形成した、縦3.7ｍｍ×横５ｍｍ×厚さ５ｍｍの金属基板４を用意した。そして、この溝の端から切り欠き部４ａの半径と同じ長さ分、離れた部位を中心として、溝の上端から下端にかけて０ｍｍから２ｍｍの範囲の種々の半径の半円形の切り欠き部４ａを溝の両側面に形成した（試料１〜６とした）。   Next, a metal substrate 4 having a length of 3.7 mm × width 5 mm × thickness 5 mm, in which a groove having the same size as that of the insulating substrate 6 for fitting the insulating substrate 6 on the upper surface was prepared. Then, semicircular cutout portions 4a having various radii in the range of 0 mm to 2 mm from the upper end to the lower end of the groove with the same length as the radius of the cutout portion 4a from the end of the groove as the center. It formed in the both sides | surfaces of a groove | channel (it was set as the samples 1-6).

次に、比較用の回路基板Ｓ’を以下のようにして作製した。まず、絶縁基板106は比誘電率が9.6のアルミナセラミックスからなる縦２ｍｍ×横1.98ｍｍ×厚さ0.5ｍｍの基板を用い、その上側主面中央部に、幅0.38ｍｍ×長さ２ｍｍ×厚さ0.002ｍｍの線路導体106ａを配置するとともに、絶縁基板106の上側主面の線路導体106ａの両側に、絶縁基板106の上側主面の側部に沿ってそれぞれ縦２ｍｍ×横0.5ｍｍ×厚さ0.002ｍｍの同一面接地導体106ｂを設置し、絶縁基板106の裏面には絶縁基板106と同一の面積である縦２ｍｍ×横1.98ｍｍ×厚さ0.002ｍｍの接地導体106ｃを配置した。さらに線路導体106ａの両側に同一面接地導体106ｂと接地導体106ｃとを導通する直径が0.20ｍｍスルーホール導体を複数、互いの間隔が（スルーホール導体同士の隙間）が0.4ｍｍとなるように線路導体106ａに沿って形成した（試料７とした）。   Next, a circuit board S ′ for comparison was produced as follows. First, the insulating substrate 106 is made of alumina ceramics having a relative dielectric constant of 9.6 and is 2 mm long × 1.98 mm wide × 0.5 mm thick, with a width of 0.38 mm × length of 2 mm × thickness at the center of the upper main surface. A 0.002 mm line conductor 106a is arranged, and on both sides of the line conductor 106a on the upper main surface of the insulating substrate 106, along each side of the upper main surface of the insulating substrate 106, the length is 2 mm × width 0.5 mm × thickness 0.002. A ground conductor 106b of 2 mm in length, 1.98 mm in width, and 0.002 mm in thickness having the same area as that of the insulating substrate 106 is disposed on the back surface of the insulating substrate 106. Further, the line conductor 106a is provided with a plurality of through-hole conductors having a diameter of 0.20 mm for conducting the same-surface ground conductor 106b and the ground conductor 106c on both sides of the line conductor 106a, and the distance between them (the gap between the through-hole conductors) is 0.4 mm. It was formed along the conductor 106a (referred to as Sample 7).

各試料における上記周波数範囲のうちで、最も悪い反射係数Ｓ11の値を表１に示す。

Figure 2006128323
Table 1 shows the worst value of the reflection coefficient S11 in the frequency range of each sample.
Figure 2006128323

表１より、切り欠き部４ａの直径が０の比較用の試料No.１は反射係数Ｓ11が−10ｄＢ以上となったものの、本発明の半導体素子収納用パッケージである試料No.２，３，４，５,６については、反射係数Ｓ11が実際に半導体装置が正常に動作する−15ｄＢ以下と良好な特性が得られることが分かった。   From Table 1, although the sample No. 1 for comparison in which the diameter of the notch 4a is 0 has a reflection coefficient S11 of -10 dB or more, sample Nos. 2, 3, which are semiconductor device storage packages of the present invention. As for 4, 5, and 6, it was found that the reflection coefficient S11 is as good as −15 dB or less at which the semiconductor device actually operates normally.

また、表１より、比較例の半導体素子収納用パッケージである試料７については反射係数Ｓ11が−10ｄＢ以上となり、半導体装置が正常に動作する−15ｄＢ以下と満たすことができないことが分かった。   Further, from Table 1, it was found that the reflection coefficient S11 of the sample 7, which is a package for housing a semiconductor element of the comparative example, was -10 dB or more, and it was not possible to satisfy -15 dB or less at which the semiconductor device operates normally.

なお、本発明は、上述の実施の形態の一例に限定されるものではなく、本発明の要旨を逸脱しない範囲内であれば種々の変更は可能である。   Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention.

本発明の半導体素子収納用パッケージおよび半導体装置の実施の形態の一例を示す断面図である。It is sectional drawing which shows an example of embodiment of the package for semiconductor element accommodation of this invention, and a semiconductor device. 図１の半導体素子収納用パッケージおよび半導体装置の平面図である。FIG. 2 is a plan view of the semiconductor element storage package and the semiconductor device of FIG. 1. 図１の半導体素子収納用パッケージにおける同軸コネクタと線路導体との接続部周辺の要部拡大断面図である。FIG. 2 is an enlarged cross-sectional view of a main part around a connection part between a coaxial connector and a line conductor in the semiconductor element storage package of FIG. 1. 図１の半導体素子収納用パッケージにおける同軸コネクタと線路導体との接続部周辺の要部拡大平面図である。FIG. 2 is an enlarged plan view of a main part around a connection part between a coaxial connector and a line conductor in the semiconductor element storage package of FIG. 1. 図１の半導体素子収納用パッケージにおける同軸コネクタの拡大断面図である。It is an expanded sectional view of the coaxial connector in the package for semiconductor element accommodation of FIG. 従来の半導体素子収納用パッケージおよび半導体装置の断面図である。It is sectional drawing of the conventional package for semiconductor element accommodation, and a semiconductor device. 図６の半導体素子収納用パッケージおよび半導体装置の平面図である。FIG. 7 is a plan view of the semiconductor element storage package and the semiconductor device of FIG. 6. 図６の半導体素子収納用パッケージにおける同軸コネクタと線路導体との接続部周辺の要部拡大断面図である。FIG. 7 is an enlarged cross-sectional view of a main part around a connection portion between a coaxial connector and a line conductor in the semiconductor element storage package of FIG. 6. 図６の半導体素子収納用パッケージにおける同軸コネクタと線路導体との接続部周辺の要部拡大平面図である。FIG. 7 is an enlarged plan view of a main part around a connection part between a coaxial connector and a line conductor in the semiconductor element storage package of FIG. 6. 図６の半導体素子収納用パッケージにおける同軸コネクタの拡大断面図である。FIG. 7 is an enlarged cross-sectional view of a coaxial connector in the semiconductor element storage package of FIG. 6.

符号の説明Explanation of symbols

１・・・・・・・基体
１ａ・・・・・・載置部
２・・・・・・・枠体
２ａ・・・・・・貫通孔
３・・・・・・・同軸コネクタ
３ａ・・・・・・中心導体
３ｂ・・・・・・絶縁体
３ｃ・・・・・・外周導体
４・・・・・・・金属基板
４ａ・・・・・・切り欠き部
６・・・・・・・絶縁基板
６ａ・・・・・・線路導体
８・・・・・・・半導体素子
10・・・・・・・蓋体
Ｓ・・・・・・・回路基板 DESCRIPTION OF SYMBOLS 1 ... Base body 1a .. Placement part 2 ..... Frame body 2a ..... Through hole 3 ...... Coaxial connector 3a ..・ ・ ・ ・ ・ Center conductor 3b ・ ・ ・ ・ ・ ・ Insulator 3c ・ ・ ・ ・ ・ ・ Outer peripheral conductor 4 ・ ・ ・ ・ ・ ・ Metal substrate 4a ・ ・ ・ Notch 6 ・ ・ ・ ・... Insulating substrate 6a ... Line conductors 8 ... Semiconductor elements
10 .... Lid S ... Circuit board

Claims (4)

上側主面の半導体素子の載置部を有する基体と、該基体の上側主面に前記載置部を取り囲むように接合され、側部に貫通孔が形成された枠体と、筒状の外周導体およびその中心軸に設置された中心導体ならびにそれらの間に介在させた絶縁体から成るとともに前記貫通孔に嵌着された同軸コネクタと、前記基体の上面の前記枠体の内側に接合され、上面に前記中心導体の端部が電気的に接続された線路導体が形成されている回路基板とを具備した半導体素子収納用パッケージにおいて、前記回路基板は、上面に溝が形成された金属基板と、該溝に嵌着されるとともに上面に前記溝に沿って前記線路導体が形成された絶縁基板とから成り、前記中心導体と前記線路導体との接続部の両側に位置する前記溝の側面に切り欠き部を設けたことを特徴とする半導体素子収納用パッケージ。 A base body having a semiconductor element mounting portion on the upper main surface, a frame body joined to the upper main surface of the base body so as to surround the mounting portion, and a through hole formed in the side portion, and a cylindrical outer periphery A coaxial connector composed of a conductor and a central conductor installed on the central axis thereof and an insulator interposed therebetween and fitted in the through hole, and joined to the inside of the frame on the upper surface of the base body, And a circuit board on which a line conductor having an end connected to the center conductor is formed on the upper surface. The circuit board includes a metal substrate having a groove formed on the upper surface. And an insulating substrate that is fitted in the groove and has the line conductor formed on the upper surface along the groove, on the side surface of the groove located on both sides of the connection portion between the center conductor and the line conductor. Features a notch Semiconductor device package for housing to be. 前記切り欠き部が前記回路基板の前記同軸コネクタ側端部よりも内側に位置していることを特徴とする請求項１記載の半導体素子収納用パッケージ。 2. The package for housing a semiconductor element according to claim 1, wherein the notch is located inside an end of the circuit board on the coaxial connector side. 前記切り欠き部の内面が平面視して円弧状であることを特徴とする請求項１または請求項２記載の半導体素子収納用パッケージ。 3. The package for housing a semiconductor element according to claim 1, wherein an inner surface of the notch is arcuate in plan view. 請求項１乃至請求項３のいずれかに記載の半導体素子収納用パッケージと、前記載置部に載置された半導体素子と、前記枠体の上面に前記半導体素子を覆うように取着された蓋体とを具備していることを特徴とする半導体装置。 A package for housing a semiconductor element according to any one of claims 1 to 3, a semiconductor element placed on the mounting portion, and an upper surface of the frame attached so as to cover the semiconductor element. A semiconductor device comprising a lid.
JP2004313023A 2004-10-27 2004-10-27 Semiconductor device and storing package thereof Pending JP2006128323A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010147187A (en) * 2008-12-17 2010-07-01 Shinko Electric Ind Co Ltd Package for semiconductor element storage, semiconductor device, and manufacturing method thereof
JP2012227219A (en) * 2011-04-15 2012-11-15 Kyocera Corp Package for housing electronic component, and electronic device
JP2012244002A (en) * 2011-05-20 2012-12-10 Kyocera Corp Package for housing electronic component and electronic device
JP2014232796A (en) * 2013-05-29 2014-12-11 京セラ株式会社 Package for storing optical semiconductor element and packaging structure including the package

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010147187A (en) * 2008-12-17 2010-07-01 Shinko Electric Ind Co Ltd Package for semiconductor element storage, semiconductor device, and manufacturing method thereof
JP2012227219A (en) * 2011-04-15 2012-11-15 Kyocera Corp Package for housing electronic component, and electronic device
JP2012244002A (en) * 2011-05-20 2012-12-10 Kyocera Corp Package for housing electronic component and electronic device
JP2014232796A (en) * 2013-05-29 2014-12-11 京セラ株式会社 Package for storing optical semiconductor element and packaging structure including the package

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