JP4335263B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4335263B2 JP4335263B2 JP2007028494A JP2007028494A JP4335263B2 JP 4335263 B2 JP4335263 B2 JP 4335263B2 JP 2007028494 A JP2007028494 A JP 2007028494A JP 2007028494 A JP2007028494 A JP 2007028494A JP 4335263 B2 JP4335263 B2 JP 4335263B2
- Authority
- JP
- Japan
- Prior art keywords
- resin layer
- molded resin
- semiconductor chip
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 167
- 238000004519 manufacturing process Methods 0.000 title description 12
- 239000010410 layer Substances 0.000 claims description 155
- 229920005989 resin Polymers 0.000 claims description 153
- 239000011347 resin Substances 0.000 claims description 153
- 239000000758 substrate Substances 0.000 claims description 55
- 238000000465 moulding Methods 0.000 claims description 46
- 238000000034 method Methods 0.000 claims description 42
- 239000012790 adhesive layer Substances 0.000 claims description 31
- 238000001816 cooling Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 14
- 239000000853 adhesive Substances 0.000 description 44
- 230000001070 adhesive effect Effects 0.000 description 43
- 229920001187 thermosetting polymer Polymers 0.000 description 21
- 229910000679 solder Inorganic materials 0.000 description 14
- 239000003990 capacitor Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 238000007789 sealing Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000011253 protective coating Substances 0.000 description 1
- 239000012779 reinforcing material Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
図1(A)は、実施形態1に係る半導体装置10の概略構成を示す斜視図である。図1(B)は、図1(A)のA−A’線上の断面構造を示す断面図である。半導体装置10は、基板20と、表面をフェイスダウンした状態で基板20にフリップチップ実装された半導体チップ30と、半導体チップ30が実装された基板20の同一面上に、半導体チップ30と離間し、半導体チップ30の周囲に設けられた成型樹脂層40と、半導体チップ30の裏面とTIM層80を介し、成型樹脂層40の上面と接着層82を介して接合されたリッド90とを備える。
図3は、実施形態1の半導体装置の製造方法の概略を示すフロー図である。まず、多層配線構造を有する基板を形成し(S10)、この基板の上に半導体チップを実装する(S20)。続いて、半導体チップと離間した周囲に成型樹脂層を形成する(S30)。次に半導体チップ裏面とTIM層を介し、成型樹脂層の上面と接着層を介してリッドを接着する(S40)。最後にハンダボール、キャパシタなどを基板の裏面に実装する(S50)。
図4は、実施形態1の半導体装置10の半導体チップ30の実装方法を示す工程断面図である。
図5および図6は、実施形態1の半導体装置10の成型樹脂層の形成方法を示す工程図である。
図7は、実施形態1の半導体装置10のリッド接着方法を示す工程図である。
図8(A)は、実施形態2に係る半導体装置11の断面構造を示している。また、実施形態2に係る半導体装置11の説明において、実施形態1に係る半導体装置10と同様な構成については適宜省略し、実施形態1に係る半導体装置10と異なる構成について説明する。
図8(B)は、実施形態3に係る半導体装置12の断面構造を示している。また、実施形態3に係る半導体装置12の説明において、実施形態2に係る半導体装置11と同様な構成については適宜省略し、実施形態2に係る半導体装置11と異なる構成について説明する。
Claims (6)
- 基板と、
表面をフェイスダウンした状態で前記基板に実装された半導体チップと、
前記半導体チップが実装された前記基板の同一面上に、前記半導体チップと離間し、前記半導体チップの周囲に設けられた成型樹脂層と、
前記半導体チップの熱を放熱するための冷却部材と、
前記冷却部材と前記成型樹脂層の上面を接着する接着層と、
前記半導体チップの裏面と前記冷却部材を熱的に接続する熱インターフェース材料層と、
を備え、
前記成型樹脂層の上面に凹部が設けられていることを特徴とする半導体装置。 - 前記成型樹脂層の上面は、前記半導体チップの裏面よりも上方に位置することを特徴とする請求項1に記載の半導体装置。
- 前記成型樹脂層の上面と同一平面における前記凹部の開口部の面積は、前記成型樹脂層の上面の面積よりも大きいことを特徴とする請求項1または2に記載の半導体装置。
- 前記接着層が、前記凹部内に設けられていることを特徴とする請求項1から3のいずれか1項に記載の半導体装置。
- 前記成型樹脂層の上面に前記凹部と前記成型樹脂層の側面を連通する流出路が設けられており、
前記流出路の底部が、前記凹部の底部よりも上方に位置することを特徴とする請求項1から4のいずれか1項に記載の半導体装置。 - 配線パターンが設けられた基板に表面をフェイスダウンした半導体チップをフリップチップ実装する工程と、
前記半導体チップが実装された前記基板の同一面上に、前記半導体チップと離間し、前記半導体チップの周囲に位置する成型樹脂層を成型するための工程と、
前記成型樹脂層の上面に接着層を形成する工程と、
前記半導体チップの裏面に熱インターフェース材料層を形成する工程と、
前記半導体チップの熱を放熱するための冷却部材を、前記成型樹脂層に対して前記接着層を介して接着するとともに前記熱インターフェース材料層と熱的に接続する工程と、
を備え、
前記成型樹脂層を成型するための工程において、前記成型樹脂層の上面に凹部を設けることを特徴とする半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007028494A JP4335263B2 (ja) | 2007-02-07 | 2007-02-07 | 半導体装置および半導体装置の製造方法 |
US11/968,840 US20080185712A1 (en) | 2007-02-07 | 2008-01-03 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007028494A JP4335263B2 (ja) | 2007-02-07 | 2007-02-07 | 半導体装置および半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008192996A JP2008192996A (ja) | 2008-08-21 |
JP4335263B2 true JP4335263B2 (ja) | 2009-09-30 |
Family
ID=39675453
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007028494A Active JP4335263B2 (ja) | 2007-02-07 | 2007-02-07 | 半導体装置および半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20080185712A1 (ja) |
JP (1) | JP4335263B2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8384223B2 (en) * | 2008-06-30 | 2013-02-26 | Intel Corporation | Backside mold process for ultra thin substrate and package on package assembly |
WO2012165647A1 (en) * | 2011-06-01 | 2012-12-06 | Canon Kabushiki Kaisha | Semiconductor device |
US10020236B2 (en) | 2014-03-14 | 2018-07-10 | Taiwan Semiconductar Manufacturing Campany | Dam for three-dimensional integrated circuit |
WO2018023887A1 (zh) * | 2016-08-01 | 2018-02-08 | 宁波舜宇光电信息有限公司 | 摄像模组及其模塑电路板组件和模塑感光组件和制造方法 |
WO2019066989A1 (en) * | 2017-09-30 | 2019-04-04 | Intel Corporation | INTEGRATED SUBSTRATE AMOUNTS AND HEAT DIFFUSER CUSTOMIZATION FOR ENHANCED PACKAGING THERMOMECHANICS |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4929965A (en) * | 1987-09-02 | 1990-05-29 | Alps Electric Co. | Optical writing head |
JPH0671061B2 (ja) * | 1989-05-22 | 1994-09-07 | 株式会社東芝 | 樹脂封止型半導体装置 |
DE19638667C2 (de) * | 1996-09-20 | 2001-05-17 | Osram Opto Semiconductors Gmbh | Mischfarbiges Licht abstrahlendes Halbleiterbauelement mit Lumineszenzkonversionselement |
JP2002270638A (ja) * | 2001-03-06 | 2002-09-20 | Nec Corp | 半導体装置および樹脂封止方法および樹脂封止装置 |
US6509696B2 (en) * | 2001-03-22 | 2003-01-21 | Koninklijke Philips Electronics N.V. | Method and system for driving a capacitively coupled fluorescent lamp |
TW521410B (en) * | 2001-11-15 | 2003-02-21 | Siliconware Precision Industries Co Ltd | Semiconductor package article |
US8174114B2 (en) * | 2005-12-15 | 2012-05-08 | Taiwan Semiconductor Manufacturing Go. Ltd. | Semiconductor package structure with constraint stiffener for cleaning and underfilling efficiency |
-
2007
- 2007-02-07 JP JP2007028494A patent/JP4335263B2/ja active Active
-
2008
- 2008-01-03 US US11/968,840 patent/US20080185712A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
JP2008192996A (ja) | 2008-08-21 |
US20080185712A1 (en) | 2008-08-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4589269B2 (ja) | 半導体装置およびその製造方法 | |
JP4155999B2 (ja) | 半導体装置および半導体装置の製造方法 | |
TWI379388B (ja) | ||
TWI415235B (zh) | Semiconductor device and manufacturing method thereof | |
JP3679786B2 (ja) | 半導体装置の製造方法 | |
KR100908759B1 (ko) | 범프레스 적층식 상호 연결 층을 갖는 초소형 전자 패키지 | |
US9040361B2 (en) | Chip scale package with electronic component received in encapsulant, and fabrication method thereof | |
JP5271886B2 (ja) | 半導体装置およびその製造方法 | |
TW201411788A (zh) | 集成電路封裝件及其裝配方法 | |
JP4335263B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP4963879B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP2014107554A (ja) | 積層型半導体パッケージ | |
TW200423342A (en) | Chip package structure and process for fabricating the same | |
JP3628991B2 (ja) | 半導体装置及びその製造方法 | |
JP2004260051A (ja) | 半導体装置の製造方法および半導体装置 | |
JPH0917827A (ja) | 半導体装置 | |
JP5958136B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
TWI750082B (zh) | 半導體覆晶封裝結構及方法 | |
JP7473156B2 (ja) | 半導体パッケージ | |
JP4344752B2 (ja) | 半導体装置の製造方法 | |
TW201725668A (zh) | 封裝基板及其製作方法 | |
JP2004172647A (ja) | 半導体装置 | |
JP2003078067A (ja) | スリム型フィリップチップ半導体装置のパッケージング方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090105 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090113 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090303 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090324 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090511 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090616 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090624 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120703 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4335263 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120703 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130703 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |