JP4155999B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- H01L23/427—Cooling by change of state, e.g. use of heat pipes
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
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- H01L2924/19041—Component type being a capacitor
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
図1(A)は、実施形態1に係る半導体装置10の概略構成を示す斜視図である。図1(B)は、図1(A)のA−A'線上の断面構造を示す断面図である。半導体装置10は、基板20と、表面をフェイスダウンした状態で基板20にフリップチップ実装された半導体チップ30と、半導体チップ30の周囲を封止する封止樹脂層40と、封止樹脂層40上にTIM層80を介して接合されたヒートシンク90とを備える。本実施形態の半導体装置10は、基板20の裏面に複数のハンダボール50がアレイ状に配設されたBGA(Ball Grid Array)型の半導体パッケージ構造を有する。
図3は、実施形態1の半導体装置の製造方法の概略を示すフロー図である。まず、多層配線構造を有する基板を形成し(S10)、この基板の上に半導体チップを実装する(S20)。続いて、半導体チップを封止樹脂で封止する(S30)。次に半導体チップ裏面に密閉空間95および冷媒98からなる冷却部を形成する(S40)。最後にハンダボール、キャパシタなどを基板の裏面に実装する(S50)。
図4は、実施形態1の半導体装置10の半導体チップ30の実装方法を示す工程断面図である。
図5および図6は、実施形態1の半導体装置10の封止樹脂層40の形成方法を示す工程図である。
図7は実施形態1の半導体装置10の冷却部の形成方法を示す工程図である。
図8は、実施形態2に係る半導体装置11の断面構造を示している。また、実施形態2に係る半導体装置11の説明において、実施形態1に係る半導体装置10と同様な構成については適宜省略し、実施形態1に係る半導体装置10と異なる構成について説明する。
Claims (9)
- 基板と
前記基板に表面をフェイスダウンした状態で実装された半導体チップと、
前記半導体チップを封止する封止樹脂層と、
前記封止樹脂層の上面に接合した冷却部材と、
前記封止樹脂層から露出した前記半導体チップの裏面と前記冷却部材の下面との間に形成された密閉空間に封入された冷媒と、
を備えたことを特徴とする半導体装置であり、
前記冷媒の一部は、前記半導体装置の動作時に前記半導体チップの裏面の発熱によって加熱され前記密閉空間内で気化することを特徴とする半導体装置。 - 前記封止樹脂層の上面に、前記封止樹脂層と前記冷却部材とを接合する熱インターフェース材料層を備えることを特徴とする請求項1に記載の半導体装置。
- 前記密閉空間には前記冷媒として水が封入されていることを特徴とする請求項1または2に記載の半導体装置。
- 非動作時の前記密閉空間の内圧は大気圧より小さいことを特徴とする請求項1または2に記載の半導体装置。
- 前記密閉空間の内壁に含まれる前記半導体チップの裏面および前記冷却部材の下面の少なくとも一方は表面に凹凸が形成されるように改質されていることを特徴とする請求項1から3のいずれか一項に記載の半導体装置。
- 前記密閉空間の内壁に含まれる前記半導体チップの裏面および前記冷却部材の下面の少なくとも一方はポーラスめっき処理されていることを特徴とする請求項1から3のいずれか一項に記載の半導体装置。
- 前記半導体チップの裏面は前記封止樹脂層の最上面より下位に位置し、前記封止樹脂層の上面の少なくとも一部は前記半導体チップの裏面に向けた傾斜を有することを特徴とする請求項1から6のいずれか一項に記載の半導体装置。
- 半導体装置の製造方法であって、
配線パターンが設けられた基板に表面をフェイスダウンした半導体チップをフリップチップ実装する工程と、
前記半導体チップの裏面を露出させた状態で前記半導体チップを封止する封止樹脂層を形成する工程と、
前記封止樹脂層の上面に接着材料層を形成する工程と、
前記接着材料層の上面に冷却部材を搭載して接合する工程と、
前記冷却部材に設けられ、前記半導体チップの裏面と前記冷却部材の下面との間に形成された空間に連通する注入穴より冷媒を注入する工程と、
前記注入穴を封止材料で塞ぎ、前記冷媒の一部が前記半導体装置の動作時に前記半導体チップの裏面の発熱によって加熱され気化する密閉空間を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記接着材料層を形成する工程より前に、前記半導体チップの裏面および前記冷却部材の下面の少なくとも一部の表面に凹凸が形成されるよう改質処理を施すステップをさらに含むことを特徴とする請求項8に記載の半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2006155232A JP4155999B2 (ja) | 2006-06-02 | 2006-06-02 | 半導体装置および半導体装置の製造方法 |
US11/751,694 US7679184B2 (en) | 2006-06-02 | 2007-05-22 | Semiconductor device having high cooling efficiency and method for manufacturing the same |
CNB2007101081063A CN100517662C (zh) | 2006-06-02 | 2007-05-30 | 半导体装置及半导体装置的制造方法 |
TW096119771A TWI346998B (en) | 2006-06-02 | 2007-06-01 | Semiconductor device having high cooling efficiency and method for manufacturing the same |
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JP2006155232A JP4155999B2 (ja) | 2006-06-02 | 2006-06-02 | 半導体装置および半導体装置の製造方法 |
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JP4155999B2 true JP4155999B2 (ja) | 2008-09-24 |
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JP (1) | JP4155999B2 (ja) |
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TW (1) | TWI346998B (ja) |
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KR100704919B1 (ko) * | 2005-10-14 | 2007-04-09 | 삼성전기주식회사 | 코어층이 없는 기판 및 그 제조 방법 |
JP2010103244A (ja) * | 2008-10-22 | 2010-05-06 | Sony Corp | 半導体装置及びその製造方法 |
NL2002240C2 (nl) * | 2008-11-21 | 2010-05-25 | Fico Bv | Inrichting en werkwijze voor het tenminste gedeeltelijk omhullen van een gesloten vlakke drager met elektronische componenten. |
JP5617548B2 (ja) * | 2010-11-11 | 2014-11-05 | ソニー株式会社 | 半導体装置の製造方法 |
US8937380B1 (en) * | 2013-08-30 | 2015-01-20 | Infineon Technologies Austria Ag | Die edge protection for pressure sensor packages |
JP6398399B2 (ja) * | 2013-09-06 | 2018-10-03 | 富士電機株式会社 | 半導体装置およびその製造方法 |
US9831190B2 (en) | 2014-01-09 | 2017-11-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device package with warpage control structure |
JP2015170625A (ja) * | 2014-03-05 | 2015-09-28 | 株式会社東芝 | 半導体パッケージ |
DE102014118080B4 (de) * | 2014-12-08 | 2020-10-15 | Infineon Technologies Ag | Elektronisches Modul mit einem Wärmespreizer und Verfahren zur Herstellung davon |
JP6413935B2 (ja) * | 2015-06-05 | 2018-10-31 | 株式会社デンソー | 半導体装置およびその製造方法 |
US11152274B2 (en) * | 2017-09-11 | 2021-10-19 | Advanced Semiconductor Engineering, Inc. | Multi-moldings fan-out package and process |
JP7095978B2 (ja) * | 2017-11-16 | 2022-07-05 | 日東電工株式会社 | 半導体プロセスシートおよび半導体パッケージ製造方法 |
CN110010565B (zh) * | 2018-12-25 | 2020-08-28 | 浙江集迈科微电子有限公司 | 一种射频微***中大功率组件的双层相变散热器制作方法 |
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KR20220163648A (ko) * | 2021-06-03 | 2022-12-12 | 삼성전자주식회사 | 반도체 패키지 |
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US6117797A (en) * | 1998-09-03 | 2000-09-12 | Micron Technology, Inc. | Attachment method for heat sinks and devices involving removal of misplaced encapsulant |
JP3677429B2 (ja) | 2000-03-09 | 2005-08-03 | Necエレクトロニクス株式会社 | フリップチップ型半導体装置の製造方法 |
US6535388B1 (en) * | 2001-10-04 | 2003-03-18 | Intel Corporation | Wirebonded microelectronic packages including heat dissipation devices for heat removal from active surfaces thereof |
KR100447867B1 (ko) * | 2001-10-05 | 2004-09-08 | 삼성전자주식회사 | 반도체 패키지 |
KR100446290B1 (ko) * | 2001-11-03 | 2004-09-01 | 삼성전자주식회사 | 댐을 포함하는 반도체 패키지 및 그 제조방법 |
US20040212080A1 (en) * | 2003-04-22 | 2004-10-28 | Kai-Chi Chen | [chip package structure and process for fabricating the same] |
TWI228806B (en) * | 2003-05-16 | 2005-03-01 | Advanced Semiconductor Eng | Flip chip package |
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