TW200423342A - Chip package structure and process for fabricating the same - Google Patents
Chip package structure and process for fabricating the same Download PDFInfo
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- TW200423342A TW200423342A TW092129524A TW92129524A TW200423342A TW 200423342 A TW200423342 A TW 200423342A TW 092129524 A TW092129524 A TW 092129524A TW 92129524 A TW92129524 A TW 92129524A TW 200423342 A TW200423342 A TW 200423342A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Abstract
Description
200423342 五、發明說明（1) 【發明所屬之技術領域】 本發明是有關於一種晶片封裝結構（c h i p p a c k a g e s t r u c t u r e )及其製程，且特別是有關於一種具有極佳散熱 性之晶片封裝結構及其製程。 【先前技術】 在高度情報化社會的今日，可攜式電子裝置 (Portable electric device)的市場不斷地急速擴張著。 晶片封裝技術亦需配合電子裝置的數位化、網路化、區域 連接化以及使用人性化的趨勢發展。為達成上述的要求， 必須強化電子元件的高速處理化、多功能化、積集 (I n t e g r a t i ο η )化、小型輕量化及低價化等多方面的要 求，於是晶片封裝技術也跟著朝向微型化、高密度化發 展。其中，覆晶接合（Flip Chip bonding， F/C bonding) 技術由於係以凸塊（B u m p )與載板（C a r r i e r )接合，較習知 導線連結（W i r e b ο n d i n g )法大幅縮短了配線長度，有助晶 片與載板間訊號傳遞速度的提昇，因此已漸成為高密度封 裝的主流。但伴隨高密度封裝技術而來的重要課題，即是 如何解決具有高積集度之晶片封裝結構的散熱問題。 第1圖繪示為習知採導線連結式的晶片封裝結構之剖 面圖。請參照第1圖，晶片2 0具有一主動表面2 2 ，且主動 表面2 2上更配置有多個焊墊（圖未示）。晶片2 0係以主動表 面22朝上而配置於載板30上。載板30之表面上配置有多個 接點（圖未示）。多條導線2 4之兩端係分別連接於晶片2 0之 焊墊以及載板3 0之接點，以電性連接於晶片2 0與載板3 0。200423342 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a chip packaging structure (c h i p p a c k a g e s t r u c t u r e) and its manufacturing process, and in particular to a chip packaging structure and its manufacturing process having excellent heat dissipation properties. [Previous Technology] In today's highly informative society, the market for portable electric devices continues to expand rapidly. Chip packaging technology also needs to cooperate with the trend of digitalization, networking, regional connection, and user-friendly use of electronic devices. In order to meet the above-mentioned requirements, it is necessary to strengthen the various requirements of high-speed processing, multifunctionalization, integration (integrati ο η), miniaturization, and low cost of electronic components. Therefore, chip packaging technology is also moving towards micro High-density development. Among them, because Flip Chip bonding (F / C bonding) technology uses bumps and Carriers to bond, it greatly shortens the wiring compared to the conventional wire bonding method. Length, which helps to improve the signal transmission speed between the chip and the carrier, has gradually become the mainstream of high-density packaging. However, an important issue that comes with high-density packaging technology is how to solve the heat dissipation problem of a chip packaging structure with a high degree of accumulation. FIG. 1 is a cross-sectional view of a conventional chip packaging structure using a wire connection type. Referring to FIG. 1, the chip 20 has an active surface 2 2, and a plurality of solder pads (not shown) are further disposed on the active surface 22. The wafer 20 is arranged on the carrier plate 30 with the active surface 22 facing upward. A plurality of contacts (not shown) are arranged on the surface of the carrier plate 30. The two ends of the plurality of wires 24 are respectively connected to the pads of the chip 20 and the contacts of the carrier board 30, and are electrically connected to the chip 20 and the carrier board 30.
11843twf .ptcl 第8頁 200423342 五、發明說明（2) 而且，載板3 0遠離晶片2 0之表面更配置有多個陣列排列之 焊球（Solder bal 1 ) 32，亦即晶片封裝結構1 0係採用球格 陣歹丨J 封裝（Ball Grid Array packaging， B G A p a c k a g i n g )，以使晶片封裝結構後續能與印刷電路板 (Printed circuit board， PCB)(圖未示）電性連接。另 外，一封裝材料層3 4係配置於載板3 0上，且覆蓋晶片2 0與 導線2 4以提供保護。但是，此晶片封裝結構1 0存在散熱性 不佳之缺點。 第2圖繪示為習知採覆晶接合技術的晶片封裝結構之 剖面圖。請參照第2圖，晶片5 0具有一主動表面5 2，且主 動表面52上更配置有多個焊塾（圖未示）。載板60之表面上 配置有多個接點（圖未示）。多個凸塊5 4係配置於主動表面 5 2上之焊墊上，且凸塊5 4係藉由晶片5 0之焊墊以及載板6 0 之接點而電性連接於晶片5 0與載板6 0之間。其中，載板6 0 遠離晶片5 0之表面更配置有多個陣列排列之焊球6 2。 為了保護晶片5 0使其免於受到濕氣的破壞，同時保護 連接晶片5 0與載板6 0的凸塊5 4，使其免於受到剪切應力 (S h e a r f 〇 r c e )破壞，因此更形成一封裝材料層6 5於晶片 5 0與載板6 0之間。習知形成封裝材料層6 5之方式係利用毛 細現象5將黏度較低的液恶封裝材料填入晶片5 0與載板6 0 之間的覆晶接合間隙，之後再將封裝材料硬化。 承上所述，晶片封裝結構4 0較第1圖所示之習知導線 連結式的晶片封裝結構1 0具有更佳電氣性能，且厚度亦符 合晶片封裝結構的薄型化趨勢。但是，封裝材料填入覆晶11843twf .ptcl Page 8 200423342 V. Description of the invention (2) Moreover, the surface of the carrier plate 30 far from the wafer 20 is further provided with a plurality of arrayed solder balls (Solder bal 1) 32, that is, the chip packaging structure 1 0 A ball grid array (JGA) package (BGA packaging) is used to enable the chip packaging structure to be electrically connected to a printed circuit board (PCB) (not shown) in the future. In addition, a packaging material layer 34 is disposed on the carrier board 30 and covers the chip 20 and the wires 24 to provide protection. However, this chip package structure 10 has the disadvantage of poor heat dissipation. FIG. 2 is a cross-sectional view of a chip package structure using a conventional flip-chip bonding technology. Referring to FIG. 2, the wafer 50 has an active surface 52, and a plurality of solder pads (not shown) are further disposed on the active surface 52. A plurality of contacts (not shown) are arranged on the surface of the carrier plate 60. The plurality of bumps 54 are arranged on the pads on the active surface 52, and the bumps 54 are electrically connected to the wafer 50 and the carrier by the pads of the wafer 50 and the contacts of the carrier 60. Board between 60. Wherein, a plurality of solder balls 62 arranged in an array are arranged on a surface of the carrier board 60 far from the wafer 50. In order to protect the wafer 50 from being damaged by moisture, and to protect the bumps 5 4 connecting the wafer 50 and the carrier board 60 from being damaged by shear stress (S hearf 〇 rce), A packaging material layer 65 is formed between the wafer 50 and the carrier board 60. The conventional way to form the packaging material layer 65 is to use the capillary phenomenon 5 to fill the low-viscosity liquid-emission packaging material into the flip-chip bonding gap between the wafer 50 and the carrier board 60, and then harden the packaging material. As mentioned above, the chip package structure 40 has better electrical performance than the conventional wire-connected chip package structure 10 shown in FIG. 1, and the thickness also conforms to the thinning trend of the chip package structure. However, the encapsulation material is filled in
11843twf.ptd 第9頁 200423342 五、發明說明（3) 接合間隙所需之時間較長，不符合產業界對產能的要求。 而且，由於封裝材料係藉助自然的毛細現象填入覆晶接合 間隙，因此晶片5 0與載板6 0之間凸塊5 4的數目、排列方式 與覆晶接合間隙的大小，都會影響封裝材料的流動性，導 致封裝材料填入不完全而形成空洞，進而影響封裝信賴度 (R e 1 i a b i 1 i t y )。此外，由於晶片5 0係直接暴露於外界， 因此在標記（M a r k i n g )晶片特性於晶片5 0表面時，或是在 猎由真空吸附晶片5 0以移動晶片封裝結構4 0時，都很容易 造成晶片5 0的破壞。 第3圖繪示為習知採熱增強型球格陣列封裝（Thermal Enhanced Ball Grid Array packaging， TEBGA p a c k a g i n g )的晶片封裝結構之剖面圖。請參照第3圖，晶 片80具有一主動表面82，且主動表面82上更配置有多個焊 墊（圖未示）。一散熱片8 5係配置於晶片8 0之背面以及載板 9 0之背面上，且散熱片8 5與晶片8 0之間係以一導熱性黏著 層87黏著。載板90之正面上配置有多個接點（圖未示）。多 條導線84之兩端係分別連接於晶片80與載板90之間，且導 線8 4係藉由晶片8 0之焊墊以及載板9 0之接點而電性連接於 晶片8 0與載板9 0之間。其中，載板9 0之正面更配置有多個 陣列排列之焊球92，焊球92係藉由連接接點之導線84而與 晶片8 0電性連接。此外，晶片封裝結構7 0更包括一封裝材 料層9 5，覆蓋晶片8 0、導線8 4與載板9 0上之接點，以提供 這些元件適當地保護。 承上所述，晶片封裝結構7 0雖然具有較佳之散熱性，11843twf.ptd Page 9 200423342 V. Description of the invention (3) The time required for the joint gap is longer, which does not meet the industry's requirements for production capacity. In addition, since the packaging material fills the flip-chip bonding gap by means of natural capillary phenomena, the number of bumps 5 4 between the wafer 50 and the carrier board 60, the arrangement and the size of the flip-chip bonding gap will affect the packaging material. The fluidity of the package leads to incomplete filling of the packaging material and formation of voids, which in turn affects the reliability of the package (R e 1 iabi 1 ity). In addition, since the wafer 50 is directly exposed to the outside world, it is easy to mark (Mark) the characteristics of the wafer on the surface of the wafer 50, or to hunt the wafer 50 by vacuum adsorption to move the wafer packaging structure 40. Causes damage to the wafer 50. FIG. 3 is a cross-sectional view of a chip package structure of a conventional Thermal Enhanced Ball Grid Array Packaging (TEBGA p a c k a g i n g). Referring to FIG. 3, the wafer 80 has an active surface 82, and a plurality of solder pads (not shown) are further disposed on the active surface 82. A heat sink 8 5 is disposed on the back of the chip 80 and the back of the carrier board 90, and a heat conductive adhesive layer 87 is adhered between the heat sink 85 and the chip 80. A plurality of contacts (not shown) are arranged on the front surface of the carrier plate 90. The two ends of the plurality of wires 84 are respectively connected between the chip 80 and the carrier board 90, and the wires 84 are electrically connected to the chip 80 and the pad 80 through the pads of the chip 80 and the contacts of the carrier board 90. Carrier board between 90. Among them, the front surface of the carrier board 90 is further provided with a plurality of solder balls 92 arranged in an array, and the solder balls 92 are electrically connected to the chip 80 through the lead wires 84 connected to the contacts. In addition, the chip packaging structure 70 further includes a packaging material layer 95 covering the contacts on the chip 80, the wires 84, and the carrier board 90 to provide proper protection of these components. As mentioned above, although the chip package structure 70 has better heat dissipation,
11843twf.ptd 第10頁 200423342 五、發明說明（4) 但是卻需要較大面積，因此無法符合高密度接腳（H i gh dens i ty I /0)之趨勢。而且，晶片封裝結構70之組裝亦非 常多雜，相對產能表現則不盡理想。 【發明内容】 因此，本發明的目的就是在提供一晶片封裝結構及其 製程，適於在晶片封裝結構中採用具有極佳電氣性能之覆 晶接合技術接合晶片，同時提供晶片封裝結構極佳之散熱 性。. 基於上述目的，本發明提出一種晶片封裝結構，主要 係由一載板、一晶片、一散熱片與一封裝材料層所構成。 其中，晶片具有一主動表面，主動表面上配置有多個凸 塊。晶片係以主動表面朝向載板而覆晶接合於載板上，且 電性連接至載板。散熱片係配置於晶片上，且散熱片之面 積係大於晶片之面積。封裝材料層係填充於晶片與載板之 間以及載板上，且封裝材料層係由單一封裝材料所形成。 其中，散熱片遠離晶片之表面至少係部份暴露於外界。 此外，封裝材料層位於晶片與載板之間的部份具有一 厚度，封裝材料層之最大材料粒徑例如係小於上述厚度之 0 . 5倍。本實施例之晶片封裝結構例如更包括一導熱性黏 著層（Heat conducting adhesive layer)。導熱性黏著層 例如係配置於晶片與散熱片之間。 基於上述目的，本發明再提出一種晶片封裝結構，主 要係由一載板、一晶片組、一散熱片與一封裝材料層所構 成。其中，晶片組係配置於載板上並與載板電性連接。晶11843twf.ptd Page 10 200423342 V. Description of the invention (4) However, it requires a large area, so it cannot meet the trend of high density pins (H i gh dens i ty I / 0). Moreover, the assembly of the chip package structure 70 is also very complicated, and the relative productivity performance is not satisfactory. [Summary of the Invention] Therefore, an object of the present invention is to provide a chip packaging structure and a manufacturing process thereof, which are suitable for bonding chips in a chip packaging structure by using a flip-chip bonding technology with excellent electrical performance, and at the same time provide a chip packaging structure with excellent Heat dissipation. Based on the above objectives, the present invention provides a chip packaging structure, which is mainly composed of a carrier board, a chip, a heat sink, and a packaging material layer. The wafer has an active surface, and a plurality of bumps are arranged on the active surface. The chip is bonded to the carrier with the active surface facing the carrier and is electrically connected to the carrier. The heat sink is arranged on the wafer, and the area of the heat sink is larger than the area of the wafer. The packaging material layer is filled between the wafer and the carrier board and the carrier board, and the packaging material layer is formed of a single packaging material. The surface of the heat sink away from the chip is at least partially exposed to the outside world. In addition, the portion of the packaging material layer between the wafer and the carrier board has a thickness, and the maximum material particle diameter of the packaging material layer is, for example, less than 0.5 times the thickness described above. The chip packaging structure of this embodiment further includes, for example, a heat conducting adhesive layer. The thermally conductive adhesive layer is, for example, disposed between the wafer and the heat sink. Based on the above objectives, the present invention further proposes a chip packaging structure, which is mainly composed of a carrier board, a chip set, a heat sink and a packaging material layer. The chip set is disposed on the carrier board and is electrically connected to the carrier board. crystal
11843twf.ptd 第11頁 200423342 五、發日月說明（5) 片組主要係由多個晶片所構成，且其中至少有一晶片係覆 晶接合於載板或其他晶片上，並且維持一覆晶接合間隙。 散熱片係配置於晶片組上，且散熱片之面積係大於晶片組 之面積。封裝材料層係填充於覆晶接合間隙内以及載板 上，且封裝材料層係由單一封裝材料所形成。其中，散熱 片遠離晶片組之表面至少係部份暴露於外界。 此外，封裝材料層位於覆晶接合間隙内的部份具有一 厚度，封裝材料層之最大材料粒徑例如係小於上述厚度之 0 . 5倍。本實施例之晶片封裝結構例如更包括一導熱性黏 著層。導熱性黏著層例如係配置於晶片組最上方之晶片與 散熱片之間。 另外，本實施例之晶片組主要例如係由一第一晶片與 一第二晶片所構成。其中，第一晶片具有一第一主動表 面，且第一晶片係以第一主動表面背向載板而配置於載板 上。第二晶片具有一第二主動表面，第二主動表面上配置 有多數個凸塊。第二晶片係以第二主動表面朝向第一晶片 而覆晶接合於第一晶片上，並電性連接至第一晶片。而凸 塊係維持覆晶接合間隙。 此外，晶片組例如更包括多條導線。其中，每條導線 之兩端例如係分別電性連接第一晶片與載板。 此外，本實施例之晶片組亦可主要由一第一晶片、一 第二晶片與一第三晶片所構成。其中，第一晶片具有一第 一主動表面，第一主動表面上配置有多個第一凸塊。第一 晶片係以第一主動表面朝向載板而覆晶接合於載板上，並11843twf.ptd Page 11 200423342 Fifth, the description of the sun and the moon (5) The chip set is mainly composed of multiple wafers, and at least one of the wafers is flip-chip bonded to a carrier board or other wafers, and a flip-chip bonding is maintained gap. The heat sink is arranged on the chipset, and the area of the heat sink is larger than the area of the chipset. The packaging material layer is filled in the flip-chip bonding gap and on the carrier board, and the packaging material layer is formed of a single packaging material. The surface of the heat sink away from the chipset is at least partially exposed to the outside world. In addition, a portion of the packaging material layer located in the flip-chip bonding gap has a thickness, and the maximum material particle diameter of the packaging material layer is, for example, less than 0.5 times the thickness described above. The chip packaging structure of this embodiment further includes, for example, a thermally conductive adhesive layer. The thermally conductive adhesive layer is, for example, disposed between the uppermost wafer of the chipset and the heat sink. In addition, the wafer set of this embodiment is mainly composed of a first wafer and a second wafer, for example. The first chip has a first active surface, and the first chip is disposed on the carrier board with the first active surface facing away from the carrier board. The second wafer has a second active surface, and a plurality of bumps are disposed on the second active surface. The second chip is flip-chip bonded to the first chip with the second active surface facing the first chip, and is electrically connected to the first chip. The bumps maintain the flip-chip bonding gap. In addition, the chipset further includes a plurality of wires, for example. The two ends of each wire are electrically connected to the first chip and the carrier board, respectively. In addition, the chip set of this embodiment may be mainly composed of a first chip, a second chip, and a third chip. The first wafer has a first active surface, and a plurality of first bumps are disposed on the first active surface. The first chip is flip-chip bonded to the carrier board with the first active surface facing the carrier board, and
11843twf.ptd 第12頁 200423342 五、發明說明（6) . 電性連接至載板。第二晶片具有一第二主動表面，且第二 晶片係以第二主動表面背向第一晶片而配置於第一晶片 上。第三晶片具有一第三主動表面，第三主動表面上配置 有多個第二凸塊。第三晶片係以第三主動表面朝向第二晶 片而覆晶接合於第二晶片上，並電性連接至第二晶片。而 第一凸塊與第二凸塊係維持覆晶接合間隙。 此外，晶片組例如更包括多條導線。其中，每條導線 之兩端例如係分別電性連接第二晶片與載板。 在上述晶片封裝結構之兩種實施例中，封裝材料層之 材質例如係樹脂。散熱片之材質例如係金屬。晶片封裝結 構例如更包括多個陣列排列之焊球與至少一被動元件。其 中，焊球例如係配置於載板未配置晶片之表面。被動元件 例如係配置於載板上且與載板電性連接。載板例如係一封 裝基材或一導線架。 基於上述目的，本發明另提出一種晶片封裝製程，主 要包括下列步驟：（a )提供一載板與多個晶片，每個晶片 分別具有一主動表面，至少一主動表面上配置有多個凸 塊。（b)使晶片與載板電性連接。（c)藉由一導熱性黏著層 將一散熱片黏著於晶片之背面上。（d )覆蓋至少一緩衝耐 熱膠片於散熱片之部分表面上。（e )形成一封裝材料層於 載板上’並使封裝材料層填充於晶片與載板之間。 其中，形成封裝材料層的方法例如係一減壓移轉注模 成形法。形成封裝材料層後例如更包括對載板進行切割， 以形成多個晶片封裝結構。而且，進行減壓移轉注模成形 11843twf.ptd 第13頁 200423342 五、發明說明（7) ' 法之壓力例如係保持在2〇毫米—汞柱(·_ —Hg 〇r T〇rr)以 下，溫度例如至少較凸塊之熔點低攝氏丨〇度。封裝材料層 位於晶片與載板之間的部份具有一厚度，而封裝材料之最 大粒控例如係小於此厚度之二分之一。 每上所述γ根據本發明所提出之晶片封裝結構，由於 ^片上配置了較晶片具有更大面積之散熱片，因此可提供 问搶度接腳之晶片封裝結構極佳的散熱途徑，進而提高晶 片封裝結構之運算速度與可靠度。而且，根據本發明所提 出之晶^封裝製程亦具有高產能之優點。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下。 【實施方式】 第4 A〜4 I圖繪示為根據本發明所提出之第一較佳實施 例的各種晶片封裝結構之剖面圖。請參照第4 A〜4丨圖，晶 片封裝結構1 0 0主要係由一載板；[8 〇、一晶片i 5 〇、一散熱 片1 4 0與一封裝材料層1 7 0所構成。其中，載板1 8 〇例如係 有機基板、陶瓷基板、可撓性基板等封裝基材，亦或是例 如覆晶式四方扁平封裝（Flip Chip Quad Flat Non-leaded packaging， F/C QFN packaging)等封裝製程 所使用之導線架（L e a d f r a m e )。載板1 8 0之上下表面例如 具有多個接點（圖未示）。 晶片150具有一主動表面152，且晶片150係以主動表 面1 5 2朝向載板1 8 0而覆晶接合於載板1 8 0之上表面上。晶11843twf.ptd Page 12 200423342 V. Description of the invention (6). Electrically connected to the carrier board. The second wafer has a second active surface, and the second wafer is disposed on the first wafer with the second active surface facing away from the first wafer. The third wafer has a third active surface, and a plurality of second bumps are disposed on the third active surface. The third wafer is flip-chip bonded to the second wafer with the third active surface facing the second wafer, and is electrically connected to the second wafer. The first bump and the second bump maintain a flip-chip bonding gap. In addition, the chipset further includes a plurality of wires, for example. The two ends of each wire are electrically connected to the second chip and the carrier board, respectively. In the above two embodiments of the chip packaging structure, the material of the packaging material layer is, for example, a resin. The material of the heat sink is, for example, metal. The chip package structure further includes, for example, a plurality of arrayed solder balls and at least one passive element. Among them, the solder balls are arranged on the surface of the carrier plate where no wafer is arranged, for example. The passive element is, for example, disposed on the carrier board and electrically connected to the carrier board. The carrier board is, for example, a mounting substrate or a lead frame. Based on the above purpose, the present invention further provides a chip packaging process, which mainly includes the following steps: (a) providing a carrier board and a plurality of wafers, each of which has an active surface, and at least one active surface is provided with a plurality of bumps . (B) electrically connecting the chip to the carrier. (C) A heat sink is adhered to the back of the chip by a thermally conductive adhesive layer. (D) covering at least one buffered heat-resistant film on a part of the surface of the heat sink. (E) Forming a packaging material layer on the carrier board 'and filling the packaging material layer between the wafer and the carrier board. Among them, the method of forming the packaging material layer is, for example, a reduced-pressure transfer injection molding method. Forming the packaging material layer further includes, for example, cutting the carrier board to form a plurality of chip packaging structures. In addition, pressure reduction transfer injection molding 11843twf.ptd page 13 200423342 V. Description of the invention (7) The pressure of the method is, for example, kept below 20 mm-Hg (· _ Hg 〇r T〇rr), The temperature is, for example, at least 0 ° C lower than the melting point of the bump. The portion of the packaging material layer between the wafer and the carrier board has a thickness, and the maximum particle size of the packaging material is, for example, less than one-half of this thickness. Each of the above mentioned chip packaging structures according to the present invention, since a larger heat sink than the chip is arranged on the chip, can provide an excellent heat dissipation path for the chip package structure of pin rush pins, thereby improving Operation speed and reliability of chip package structure. Moreover, the crystalline packaging process provided by the present invention also has the advantage of high throughput. In order to make the above and other objects, features, and advantages of the present invention more comprehensible ', preferred embodiments are described below in detail with reference to the accompanying drawings, as follows. [Embodiment] FIGS. 4A to 4I are cross-sectional views of various chip packaging structures according to the first preferred embodiment of the present invention. Please refer to FIGS. 4A to 4 丨, the chip package structure 100 is mainly composed of a carrier board; [80, a chip i50, a heat sink 140, and a packaging material layer 170. Among them, the carrier board 180 is, for example, an packaging substrate such as an organic substrate, a ceramic substrate, or a flexible substrate, or it may be, for example, a Flip Chip Quad Flat Non-leaded packaging (F / C QFN packaging). Lead frame used in packaging process. The upper and lower surfaces of the carrier plate 180 have, for example, a plurality of contacts (not shown). The chip 150 has an active surface 152, and the chip 150 is bonded to the upper surface of the carrier plate 180 with the active surface 15 2 facing the carrier plate 180. crystal
11843twf.ptd 第14頁 200423342 五、發明說明（8) 片150之主動表面上例如配置有多個焊墊（圖未示），多個 凸塊1 6 0係配置於晶片1 5 0之主動表面1 5 2上之焊墊上。晶 片1 5 0係藉由焊墊上之凸塊1 6 0而電性連接至載板1 8 0。亦 即，本實施例之晶片封裝結構1 0 0中至少包括了 一晶片 1 5 0，且此晶片1 5 0係採用覆晶接合技術接合於載板1 8 0之 上表面上。然而，除了此晶片1 5 0之外，本實施例亦可在 封裝結構1 0 0中的載板1 8 0上設置其他晶片或其他元件 (Component )，如電阻、電容等被動元件。 散熱片1 4 0係配置於晶片1 5 0上，且散熱片1 4 0之面積 係大於晶片1 5 0之面積，因此具有更佳之散熱效率。而 且，散熱片1 4 0並不侷限於一體成形，亦可由多個獨立之 散熱片所構成，此種設計有利於大面積之晶片封裝結構的 靈活運用。 此外，封裝材料層1 7 0係填充於晶片1 5 0與載板1 8 0之 間，且覆蓋載板1 8 0上。而且，封裝材料層1 7 0係由單一封 裝材料所形成。封裝材料層1 7 0之材質例如係樹脂。 散熱片1 4 0之材質例如係金屬。在本發明中，面積較 晶片1 5 0大之金屬材質的散熱片140 ’主要是為了使晶片 1 5 0所產生的熱量能大範圍的擴散，因此以導熱性佳者最 好。一般例如係使用銅板、铭板、鐵板、鎳板或其表面鑛 金者。此外，散熱片1 4 0須能承受形成進行封裝製程時的 壓力，因此最好具備不易彎曲的強度。雖然依金屬種類而 不同，但散熱片1 4 0例如係以0. 1〜0. 6毫米之間的厚度者 為佳。另外，為了增加封裝材料層1 7 0與散熱片之1 4 0界面11843twf.ptd Page 14 200423342 V. Description of the invention (8) For example, a plurality of solder pads (not shown) are arranged on the active surface of the sheet 150. A plurality of bumps 160 are arranged on the active surface of the chip 150. 1 5 2 on the pad. The wafer 150 is electrically connected to the carrier board 180 through the bump 160 on the solder pad. That is, the wafer package structure 100 of this embodiment includes at least one wafer 150, and the wafer 150 is bonded to the upper surface of the carrier board 180 using a flip-chip bonding technology. However, in addition to the chip 150, in this embodiment, other chips or other components (such as resistors, capacitors, and other passive components) may be provided on the carrier board 180 in the package structure 100. The heat sink 140 is disposed on the chip 150, and the area of the heat sink 140 is larger than the area of the chip 150, so it has better heat dissipation efficiency. In addition, the heat sink 140 is not limited to being integrally formed, and may also be composed of multiple independent heat sinks. This design facilitates the flexible use of a large-area chip package structure. In addition, the packaging material layer 170 is filled between the wafer 150 and the carrier board 180 and covers the carrier board 180. Further, the packaging material layer 170 is formed of a single packaging material. The material of the packaging material layer 170 is, for example, a resin. The material of the heat sink 1 40 is, for example, metal. In the present invention, the heat sink 140 'made of a metal material having a larger area than the wafer 150 is mainly used to diffuse the heat generated by the wafer 150 in a wide range, so the one with the best thermal conductivity is preferred. Generally, for example, a copper plate, a name plate, an iron plate, a nickel plate, or a surface gold is used. In addition, the heat sink 140 must be able to withstand the pressure when forming the packaging process, so it is desirable to have a strength that is not easily bent. Although it varies depending on the type of metal, the heat sink 1 40 is, for example, one having a thickness between 0.1 to 0.6 mm. In addition, in order to increase the interface between the packaging material layer 170 and the heat sink 1 40
11843twf.ptd 第15頁 200423342 五、發明說明（9) 的緊密度，除在散熱片140之表面例如進行鍍金處理外， 亦可在散熱片1 4 0之表面例如進行表面化學處理或表面粗 化等物理處理。 此外，為使散熱片1 4 0與晶片1 5 0之間具有適當接著， 例如更配置有一導熱性黏著層1 4 5於散熱片1 4 0與晶片1 5 0 之間（如第4 A圖之放大部分所示）。導熱性黏著層1 4 5 —般 多使用矽膠、銀膏、錫膏等導熱性佳之材質。 另外，晶片封裝結構1 0 0例如更包括多個陣列排列之 焊球1 9 0。其中，焊球1 9 0例如係配置於載板1 8 0下表面之 接點上。焊球1 9 0係提供晶片封裝結構1 0 0之後例如與印刷 電路板電性連接之用途。 在第4 A〜4 I圖所示之晶片封裝結構1 0 0中，第4 A〜 4 E、4 Η〜4 I圖之晶片封裝結構1 0 0係以單一晶片1 5 0為例， 而第4 F〜4 G圖之晶片封裝結構1 0 0則以兩個晶片1 5 0為例， 當然晶片1 5 0之數量不侷限於此，其數量亦可更多。第 4 C、4 D、4 G與4 I圖之晶片封裝結構1 0 0其封裝材料層1 7 0係 覆蓋散熱片1 4 0上表面之周緣，而其餘晶片封裝結構1 0 0之 散熱片1 4 0的上表面係完全暴露於外界。第4 D與4 Ε圖之晶 片封裝結構1 0 0其散熱片1 4 0之周緣係經加工變形。第4Η與 4 I圖之晶片封裝結構1 0 0更包括至少一被動元件1 9 5，被動 元件1 9 5例如係配置於載板1 8 0之上表面上，且與載板1 8 0 電性連接。以上各類晶片封裝結構1 0 0皆屬本發明之第一 較佳實施例之變形，唯仍不脫本發明所欲保護之範圍。 第5圖與第6圖繪示為根據本發明所提出之第二較佳實11843twf.ptd Page 15 200423342 V. The compactness of the invention (9), in addition to the surface of the heat sink 140 such as gold plating, the surface of the heat sink 140 can also be chemically treated or roughened. And other physical processing. In addition, for proper bonding between the heat sink 1 40 and the chip 150, for example, a thermally conductive adhesive layer 14 5 is further disposed between the heat sink 1 40 and the chip 1 50 (as shown in FIG. 4A). As shown in the enlarged section). Thermally conductive adhesive layer 1 4 5-Generally use silicone, silver paste, solder paste and other materials with good thermal conductivity. In addition, the chip package structure 100 includes, for example, a plurality of arrayed solder balls 190. Among them, the solder ball 190 is, for example, disposed on a contact on the lower surface of the carrier plate 180. The solder ball 190 is used for the purpose of electrically connecting the chip package structure 100 to the printed circuit board, for example. In the wafer package structure 100 shown in Figs. 4A to 4I, the wafer package structure 100 shown in Figs. 4A to 4E, 4Η to 4I uses a single wafer 150 as an example, and For the wafer package structure 100 in the 4th to 4th G diagrams, two wafers 150 are taken as an example. Of course, the number of wafers 150 is not limited to this, and the number may also be larger. 4C, 4D, 4G, and 4I of the chip package structure 100, its packaging material layer 170 is covering the periphery of the upper surface of the heat sink 1 40, and the remaining chip package structure 100 heat sink The upper surface of 140 is completely exposed to the outside world. The peripheral edge of the heat sink 1 140 of the wafer package structure 100 of Figs. 4D and 4E is processed and deformed. The chip package structure 1 0 in Figures 4 and 4 I further includes at least one passive component 195. The passive component 195 is, for example, disposed on the upper surface of the carrier plate 1 0 0 and electrically connected to the carrier plate 1 8 0. Sexual connection. The above-mentioned various types of chip packaging structures 100 are all modifications of the first preferred embodiment of the present invention, but still do not depart from the scope of the present invention. 5 and 6 show the second preferred embodiment according to the present invention.
11843twf.ptd 第16頁 200423342 五、發明說明（ίο) 施例的晶片封裝結構之剖面圖。在根據本發明所提出之第 二較佳實施例的晶片封裝結構中，主要係更增加多個晶 片，其餘與第一較佳實施例相同之處在此不再贅述。請共 同參照第5圖與第6圖，晶片封裝結構2 0 0主要係由一載板 2 8 0、一晶片組2 5 0、一散熱片2 4 0與一封裝材料層2 7 0所構 成。其中，晶片組2 5 0主要係由多個晶片所構成，且其中 至少有一晶片係以覆晶接合技術接合於載板2 8 0或其他晶 片上。因此，晶片組2 5 0内至少存在一覆晶接合間隙2 5 6 ， 覆晶接合間隙2 5 6係由採用覆晶接合之晶片上的凸塊所形 成的。散熱片2 4 0係配置於晶片組2 5 0上。封裝材料層2 7 0 係充滿於覆晶接合間隙2 5 6内，且覆蓋載板2 8 0上。封裝材 料層2 7 0係由單一封裝材料所形成。其中，散熱片2 4 0遠離 晶片組2 5 0之表面至少係部份暴露於外界。 此外，封裝材料層2 7 0位於覆晶接合間隙2 5 6内的部份 具有一厚度，封裝材料層2 7 0之最大材料粒徑例如係小於 上述厚度之0. 5倍。本實施例之晶片封裝結構2 0 0例如更包 括一導熱性黏著層2 4 5。導熱性黏著層2 4 5例如係配置於晶 片組2 5 0最上方之晶片與散熱片24 0之間。導熱性黏著層 2 4 5 —般多使用矽膠、銀膏、錫膏等導熱性佳之材質。 請參照第5圖，本較佳實施例之晶片組2 5 0主要例如係 由一第一晶片250a與一第二晶片250b所構成。其中，各元 件之配置關係如下所述。第一晶片2 5 0 a具有一第一主動表 面252a，且第一晶片250a係以第一主動表面252b朝上而配 置於載板2 8 0上。第二晶片25 0b係具有一第二主動表面11843twf.ptd Page 16 200423342 V. Sectional view of the chip package structure of the embodiment of the invention (ίο). In the chip package structure according to the second preferred embodiment of the present invention, a plurality of wafers are mainly added, and the rest is the same as the first preferred embodiment and will not be repeated here. Please refer to FIG. 5 and FIG. 6 together. The chip package structure 2 0 is mainly composed of a carrier board 2 80, a chip set 2 50, a heat sink 2 4 0, and a packaging material layer 2 7 0. . Among them, the chipset 250 is mainly composed of multiple wafers, and at least one of the wafers is bonded to the carrier board 2800 or other wafers by flip-chip bonding technology. Therefore, at least one flip-chip bonding gap 2 5 6 exists in the wafer group 250, and the flip-chip bonding gap 2 56 is formed by bumps on a wafer using flip-chip bonding. The heat sink 2 40 is disposed on the chipset 250. The encapsulating material layer 2 7 0 is filled in the flip-chip bonding gap 2 5 6 and covers the carrier plate 2 8 0. The packaging material layer 270 is formed of a single packaging material. Among them, the surface of the heat sink 24 0 away from the chipset 250 is at least partially exposed to the outside world. In addition, the portion of the packaging material layer 2 70 located within the flip-chip bonding gap 2 56 has a thickness, and the maximum material particle diameter of the packaging material layer 2 70 is, for example, less than 0.5 times the thickness described above. The chip package structure 200 of this embodiment further includes, for example, a thermally conductive adhesive layer 2 4 5. The thermally conductive adhesive layer 2 4 5 is, for example, disposed between the uppermost wafer of the wafer group 250 and the heat sink 240. Thermally conductive adhesive layer 2 4 5 —Silicon, silver paste, solder paste and other materials with good thermal conductivity are generally used. Referring to FIG. 5, the chip set 250 of the preferred embodiment is mainly composed of a first wafer 250a and a second wafer 250b, for example. Among them, the arrangement relationship of each element is as follows. The first wafer 250a has a first active surface 252a, and the first wafer 250a is disposed on the carrier plate 280 with the first active surface 252b facing upward. The second wafer 250b has a second active surface
11843twf.ptd 第17頁 200423342 五、發明說明（11) 252b，第二主動表面25 2b上配置有多數個凸塊260。第二 晶片2 5 0 b係以第二主動表面2 5 2 b朝向第一晶片2 5 0 a而覆晶 接合於第一晶片250a上，並電性連接至第一晶片250a。而 凸塊2 6 0係維持覆晶接合間隙2 5 6。 此外，晶片組250例如更包括多條導線2 5 4b。載板2 80 之表面上例如配置有多個接點（圖未示），第一晶片2 5 0 a之 第一主動表面252a以及第二晶片250b之第二主動表面252b 上例如配置有多個焊墊（圖未示）。第二晶片2 5 0 b之凸塊 2 6 0即維持覆晶接合間隙2 5 6於第一晶片2 5 0 a與第二晶片 2 5 0 b之間。換言之，第二晶片2 5 0 b係以覆晶接合技術接合 於第一晶片250a之第一主動表面252a上。每條導線254b之 兩端例如係分別電性連接第一晶片2 5 0 a之焊墊與載板2 8 0 之接點。 請參照第6圖，本較佳實施例之晶片組2 5 0例如係由一 第一晶片2 5 0 a 、一第二晶片2 5 0 b與一第三晶片2 5 0 c所構 成。晶片組2 5 0例如更包括多條導線2 5 4 b。其中，各元件 之配置關係如下所述。第一晶片2 5 0a係配置於載板2 8 0 上，且第一晶片250a具有一第一主動表面252a，第一主動 表面252a上配置有多個第一凸塊260a。第一晶片250a係以 弟一主動表面252a朝向載板280而覆晶接合於載板280上’ 並電性連接至載板280。第二晶片250b具有一第二主動表 面252b，第二主動表面252b係背向第一晶片250a。而且， 多條導線2 5 4b係連接於第二晶片2 5 0b之第二主動表面25 2 b 上的焊墊，以及載板2 8 0的接點之間，以電性連接第二晶11843twf.ptd Page 17 200423342 V. Description of the Invention (11) 252b, the second active surface 25 2b is provided with a plurality of bumps 260. The second wafer 2 50 b is flip-chip bonded to the first wafer 250 a with the second active surface 2 5 2 b facing the first wafer 250 a, and is electrically connected to the first wafer 250a. The bump 2 6 0 maintains the flip-chip bonding gap 2 5 6. In addition, the chip set 250 further includes a plurality of wires 2 5 4b, for example. For example, a plurality of contacts (not shown) are arranged on the surface of the carrier plate 2 80. For example, a plurality of first active surfaces 252a of the first chip 250a and a second active surface 252b of the second chip 250b are disposed. Pad (not shown). The bump 2 60 of the second wafer 2 5 0 b maintains the flip-chip bonding gap 2 5 6 between the first wafer 2 50 a and the second wafer 2 5 0 b. In other words, the second wafer 250b is bonded to the first active surface 252a of the first wafer 250a by a flip-chip bonding technique. The two ends of each wire 254b are, for example, electrically connected to the contacts of the soldering pad of the first chip 250a and the carrier 2800 respectively. Referring to FIG. 6, the chipset 250 of the preferred embodiment is composed of, for example, a first wafer 250a, a second wafer 250b, and a third wafer 250c. The chipset 2 5 0 further includes, for example, a plurality of wires 2 5 4 b. Among them, the arrangement relationship of each element is as follows. The first wafer 250a is disposed on the carrier board 280, and the first wafer 250a has a first active surface 252a, and a plurality of first bumps 260a are disposed on the first active surface 252a. The first chip 250a is bonded to the carrier plate 280 with the first active surface 252a facing the carrier plate 280 'and is electrically connected to the carrier plate 280. The second wafer 250b has a second active surface 252b, and the second active surface 252b faces away from the first wafer 250a. In addition, the plurality of wires 2 5 4b are connected to the pads on the second active surface 25 2 b of the second chip 2 50 b and the contacts of the carrier board 2 0 0 to electrically connect the second crystal.
11843twf.ptd 第18頁 200423342 五、發明說明（12) 片250b與載板280。第三晶片250c具有一第三主動表面 252c ，第三主動表面25 2c上配置有多個第二凸塊260b。第 三晶片250c係以第三主動表面252c朝向第二晶片250b而覆 晶接合於第二晶片2 5 0 b上，並電性連接至第二晶片2 5 0 b。 而第一凸塊2 6 0 a與第二凸塊2 6 0 b係維持覆晶接合間隙 2 5 6。換言之，第三晶片2 5 0 c係以覆晶接合技術接合於第 二晶片2 5 0 b之第二主動表面2 5 2 b，第一晶片2 5 0 a係以覆晶 接合技術接合於載板2 5 0 b之表面。 在本發明所提出之第二較佳實施例中，與第一較佳實 施例相較主要係增加晶片之數量，同時不限定所有晶片皆 採用覆晶接合技術與載板接合。本發明之最主要特徵仍在 於晶片封裝結構中至少包括一晶片，且此晶片係採用覆晶 接合技術與載板或是其他晶片接合。而且，晶片上方更配 置有一散熱板。載板上以及覆晶接合間隙内皆具有封裝材 料層，封裝材料層係以相同封裝材料一次形成。散熱片退 離晶片之表面至少係部份暴露於外界。只要符合上述主要 特徵之任何實施樣態，皆應屬於本發明所欲保護之範圍。 以下將介紹本發明所提出之較佳實施例的晶片封裝製 程，並且詳細介紹其實施方式。晶片封裝製程主要包括下 列步驟：（a )提供一載板與多個晶片，每個晶片分別具有 一主動表面，至少一主動表面上配置有多個凸塊。（b)使 晶片與載板電性連接。（d )藉由一導熱性黏著層將一散熱 片黏著於晶片之背面上。（e)覆蓋至少一緩衝耐熱膠片於 散熱片之部分表面上。（f )形成一封裝材料層於載板上，11843twf.ptd Page 18 200423342 V. Description of the invention (12) Piece 250b and carrier plate 280. The third wafer 250c has a third active surface 252c, and a plurality of second bumps 260b are disposed on the third active surface 252c. The third wafer 250c is flip-chip bonded to the second wafer 250b with the third active surface 252c facing the second wafer 250b, and is electrically connected to the second wafer 250b. The first bump 2 6 0 a and the second bump 2 6 0 b maintain a flip-chip bonding gap 2 5 6. In other words, the third wafer 2 5 0 c is bonded to the second active surface 2 5 2 b of the second wafer 2 5 0 b by the flip-chip bonding technique, and the first wafer 2 5 0 a is bonded to the carrier by the flip-chip bonding technique. The surface of the plate 2 5 0 b. In the second preferred embodiment proposed in the present invention, the number of wafers is mainly increased compared with the first preferred embodiment, and at the same time, it is not limited that all wafers are bonded to the carrier board by flip-chip bonding technology. The most important feature of the present invention is that at least one wafer is included in the chip packaging structure, and the wafer is bonded to a carrier board or other wafers using a flip-chip bonding technology. Moreover, a heat sink is arranged above the chip. There is a packaging material layer on the carrier board and in the flip-chip bonding gap. The packaging material layer is formed with the same packaging material at one time. The surface of the heat sink away from the chip is at least partially exposed to the outside world. As long as any implementation form that meets the above main features should fall within the scope of the present invention. In the following, the chip packaging process of the preferred embodiment of the present invention will be described, and the implementation manners will be described in detail. The chip packaging process mainly includes the following steps: (a) providing a carrier board and a plurality of wafers, each of which has an active surface, and at least one active surface is provided with a plurality of bumps. (B) The chip and the carrier are electrically connected. (D) A heat sink is adhered to the back of the chip by a thermally conductive adhesive layer. (E) Cover at least one buffer heat-resistant film on a part of the surface of the heat sink. (F) forming a packaging material layer on the carrier board,
11843twf.ptd 第19頁 200423342 五、發明說明（13) 並使封裝材料層填充於晶片與載板之間。 完成此晶片封裝製程所得到之晶片封裝結構具有下列 特徵。第7 A圖繪示為根據本發明所提出之較佳實施例的晶 片封裝結構，在完成晶片封裝製程後之成品的剖面圖。第 7 B圖繪示為根據本發明所提出之較佳實施例的晶片封裝結 構，在完成晶片封裝製程後之成品經切割後的剖面圖。請 共同參照第7 A圖與第7 B圖，為符合量產所需，本較佳實施 例之封裝製程在形成封裝材料層1 7 0後，例如更沿切割線L 進行切割（D i c i ng )，以形成多個晶片封裝結構1 0 0。其 中，每個晶片封裝結構1 0 0至少包括一個晶片1 5 0 。另外， 雖然在第7 A圖中繪示之封裝材料層1 7 0係連接為一體，但 亦可調整製程模具，形成多個互相獨立之封裝材料層 1 7 0，亦即在切割線部份不形成封裝材料層，以縮短後續 切割所需之時間。 值得注意的是，在根據本發明所提出之較佳實施例的 晶片封裝結構之製程中，形成封裝材料層的方法例如係一 減壓移轉注模成形法。減壓移轉注模成形法係指將欲封裝 之晶片結構放入模具，在模具進入減壓狀態後，於模具内 導入熱炫融材料，並進行加熱加壓處理使樹脂硬化的一種 處理方式。一般移轉注模成形法由於未進行減壓，易造成 覆晶接合間隙或晶片與散熱板之間的封裝材料填充不足， 若使模具内的減壓狀態保持在2 0毫米-汞柱以下則可獲得 較佳之封裝效果，減壓狀態之最佳值在1 0毫米-汞柱以 下。11843twf.ptd Page 19 200423342 V. Description of the invention (13) The packaging material layer is filled between the wafer and the carrier board. The chip packaging structure obtained by completing this chip packaging process has the following characteristics. FIG. 7A is a cross-sectional view of a finished product after the wafer packaging process is completed according to the preferred embodiment of the present invention. FIG. 7B is a cross-sectional view of a chip packaging structure according to a preferred embodiment of the present invention. The finished product is cut after the chip packaging process is completed. Please refer to FIG. 7A and FIG. 7B together. In order to meet the needs of mass production, the packaging process of the preferred embodiment after the packaging material layer 170 is formed, for example, cutting along the cutting line L (D ici ng ) To form a plurality of chip packaging structures 100. Among them, each chip package structure 100 includes at least one chip 150. In addition, although the packaging material layer 170 shown in Figure 7A is connected as a whole, the process mold can also be adjusted to form multiple independent packaging material layers 170, that is, in the cutting line portion No packaging material layer is formed to reduce the time required for subsequent cutting. It is worth noting that, in the manufacturing process of the chip packaging structure according to the preferred embodiment of the present invention, the method of forming the packaging material layer is, for example, a reduced-pressure transfer injection molding method. The decompression transfer injection molding method refers to a processing method in which a wafer structure to be packaged is placed in a mold, and after the mold enters a reduced pressure state, a hot melt material is introduced into the mold, and the resin is hardened by heat and pressure treatment. The general transfer injection molding method is not pressure-reduced, which may easily cause the chip-to-chip bonding gap or insufficient filling of the packaging material between the wafer and the heat sink. If the pressure-reduced state in the mold is kept below 20 mm-Hg A better packaging effect is obtained, and the optimal value of the decompressed state is below 10 mm-Hg.
11843twf.ptd 第20頁 200423342 五、發明說明（14) 封裝处構圖曰Ί根據本發明所提出之較佳實施例的晶片 面圖了靖^昭円轉注模成形模具*形成封裝材料層的剖 需的封f ίΛ，人移轉注模成形設備（圖未示）可依所 具3〗γΛ 式 適合的模具3 00，模具3〇〇主要俜由上模 :3 1 〇與下模具3 2 〇 杏要保由上核 卜達到較有效率；i空：i”3二與二拉具么〇合模 #. Q 1 π /、工欢禾 σ楔步脉係百先將上模 觸接Λ模具32吉0與模具3 0 0内之真空橡膠封環33〇輕微接 行 者以抽/、空幫浦（圖未示）經由抽真空管路3 7 〇進 (士 ^具腔34 0内的減壓真空處理。然後’投入膠餅 高1ΡΓ)(圖未示）於注膠管路3 5 0内，並維持1〜5秒以提 熱二=内$真空度，同時提升模具内之溫度以使勝餅成為 6 1狀恶之封裝材料。最後，將上模具3丨〇與下模具3 2 〇 完成減壓移轉 將成形溫度控制 成形溫度高過 二二?合，同時拉起柱S(plunger)36〇，以導入熱炫融狀 、、=之封裝材料，使其填滿於模具腔34 〇内 在模成形。 在 其中，減壓移轉注模成形在進行時 於^ 1凸塊1 6 〇之熔點至少攝氏1 0度為佳7 w %流沒向迴 產1日守胃’相對於成形時熔融狀態之封裝材料對晶片丨5 〇所 度生之壓力，凸塊1 6 〇對於晶片丨5 〇與載板丨8 〇覆晶接合強 二ί夠’容易在減壓移轉注模成形的過程中發生晶片1 5 0 机洛等現象。 製。另外’在根據本發明所提出之較佳實施例的晶片封裝 $，^ ’散熱片1 4 0欲在晶片封裝製程完成後暴露於外界 。卩份’必須在一緩衝耐熱膠片3 8 〇的被覆下進行封裝。11843twf.ptd Page 20, 200423342 V. Description of the invention (14) Packaging diagram According to the preferred embodiment of the present invention, the wafer side view shows Jing ^ Zhao 円 transfer injection molding mold * forming the packaging material layer The seal f ίΛ, the human transfer injection molding equipment (not shown in the figure) can be suitable according to the mold 3 〖γΛ type suitable mold 3 00, the mold 3 00 is mainly composed of the upper mold: 3 1 0 and the lower mold 3 2 0 It is necessary to ensure that the upper core is more efficient; i is empty: i "3 2 and 2 pull tool 0 closed mold #. Q 1 π /, Gong Huan He σ wedge step pulse system hundred first contact the upper mold Λ mold 32 Ji 0 and the vacuum rubber seal ring in the mold 3 0 0 0 Slightly connected to the pump / air pump (not shown) through the vacuum line 3 7 0 (decompression in the pressure chamber 3 0 0) Vacuum treatment. Then 'put the cake height 1PΓ) (not shown) in the injection pipe 3 50, and maintain it for 1 to 5 seconds to heat up 2 = internal $ vacuum degree, while increasing the temperature in the mold to win The cake becomes the packaging material of the 61-like evil. Finally, the upper mold 3 丨 〇 and the lower mold 3 2〇 are transferred under reduced pressure to control the forming temperature to be higher than 22? Then, simultaneously pull up the column S (plunger) 36 ° to introduce the hot-melt-like packaging material to fill the mold cavity with the inner mold molding. Among them, the decompression transfer injection molding is being performed. The melting point at ^ 1 bump 1 6 ℃ is at least 10 degrees Celsius is better 7 w% flow to the production 1 day Shouwei 'relative to the pressure of the packaging material on the wafer during the molding 丨 5 ℃ pressure The bumps 1 6 〇 for the wafer 丨 5 〇 and the carrier 丨 8 〇 flip chip bonding is strong enough 'easy to occur in the process of decompression transfer injection molding wafer 1 50 machine Luo and other phenomena. In the chip package according to the preferred embodiment of the present invention, the heat sink 1 40 is to be exposed to the outside after the chip packaging process is completed. The component must be covered with a buffer heat-resistant film 3 800. Package.
200423342 五、發明說明（15) 若沒有被覆緩衝耐熱膠片3 8 0而進行封裝，則散熱片1 4 0欲 暴露於外界的部份易發生溢膠（F 1 u sh )。但是，若為了防 止溢膠發生而將上模具3 1 0調整而直接加壓於散熱片1 4 0 上，則封裝時的模壓也會透過散熱片1 4 0而施加於晶片1 5 0 上而傷害晶片1 5 0。所以，被覆緩衝耐熱膠片3 8 0於散熱片 1 4 0上作為緩衝係較佳的解決方法。 緩衝耐熱膠片3 8 0之材質常用的有聚纖胺（Polyamide) 或氣樹脂糸材料’並無特別規定。緩衝耐熱膠片3 8 0 —般 使用之厚度係以2 5〜7 5微米，此厚度即可獲得本發明所提 及的緩衝作用。此外，緩衝财熱膠片3 8 0之材質亦可使用 氟化橡膠等橡膠材質。 而且，根據本發明所提出之較佳實施例的晶片封裝結 構在進行晶片封裝製程中，所使用之封裝材料之最大粒徑 以小於覆晶接合間隙之0. 5倍者為佳。若所使用之封裝材 料之最大粒徑大於覆晶接合間隙之0. 5倍時，覆晶接合間 隙或晶片與散熱板之間的封裝材料填充較為困難，甚至會 造成填充不完全的情形。而且，還會因封裝材料充填時與 晶片表面的摩擦，造成晶片表面的損傷，降低晶片的可靠 度。 以下將敘述本發明之實際應用例與對照例的實施條 件，以及所獲得之實施結果。 【實例1】將面積大小為8毫米X 8毫米，具8 0 0個共晶錫鉛 凸塊（熔點攝氏1 8 3度、間距為0 . 2 5毫米）、厚度0 · 3毫米之 晶片，以矩陣排列方式接合於面積3 5毫米X 3 5毫米、厚度200423342 V. Description of the invention (15) If the buffer heat-resistant film 3 8 0 is not covered for packaging, the portion of the heat sink 1 40 that is to be exposed to the outside is prone to overflow (F 1 u sh). However, if the upper mold 3 1 0 is adjusted to prevent the occurrence of glue overflow, and the pressure is directly applied to the heat sink 1 4 0, the molding pressure during packaging will also be applied to the wafer 1 50 through the heat sink 1 4 0. Injury the chip 1 50. Therefore, covering the buffer heat-resistant film 380 on the heat sink 140 is a better solution for the buffer system. The material of the buffer heat-resistant film 380 is usually polyamide or an aero-resin material. There is no special requirement. The buffer heat-resistant film 3800 is generally used in a thickness of 25 to 75 micrometers, and this thickness can obtain the buffering effect mentioned in the present invention. In addition, rubber material such as fluorinated rubber can also be used as the material of the buffer heat-storage film 380. Moreover, the chip packaging structure according to the preferred embodiment of the present invention, in the chip packaging process, the maximum particle size of the packaging material used is less than 0.5 times the flip-chip bonding gap. If the maximum particle size of the packaging material used is greater than 0.5 times the flip-chip bonding gap, the filling of the flip-chip bonding gap or the packaging material between the wafer and the heat sink is difficult, and may even cause incomplete filling. In addition, friction between the packaging material and the surface of the wafer may cause damage to the surface of the wafer and reduce the reliability of the wafer. The implementation conditions of the practical application examples and comparative examples of the present invention, and the implementation results obtained will be described below. [Example 1] A wafer with an area of 8 mm X 8 mm, with 800 eutectic tin-lead bumps (melting point 18 3 degrees Celsius, pitch 0.25 mm), and a thickness of 0.3 mm, Joined in a matrix arrangement with an area of 35 mm x 3 5 mm, thickness
11843twf.ptd 第22頁 200423342 五、發明說明（16) . 0 · 4毫米之載板（F R - 5 )上。為了使電流能夠均勻通過，並 在晶片表面加上紹製配線。覆晶接合間隙為5 0〜7 5微米: 利用市面販售的導熱黏著劑將2 2毫米X 2 2毫米大小、厚产 0 · 2毫米的銅板黏在該晶片上。銅板上面鍍鎳後，中間貼& 上市面販售的20毫米0PFA膠片（厚度50微米）。同樣的為 了提昇接著強度，下面施以表面粗化處理，並使用具減'壓 功能之移轉注模成形設備進行減壓移轉注模成形。空間内 減壓度約為1宅米-采柱。封裝材料使用的是松下電工（股） 製C V 8 7 0 0 F 2 (填充材最大粒徑2 1微米，平均粒徑5微米，添 加的材料全為矽）。進行上模空間厚度〇 · 6毫米，封裝部2 7 毫米x27毫米面積之成形。成形在攝氏170度，70公斤/平 方公分之壓力下進行2分鐘，再進行攝氏1 7 5度、4小時的 後硬化程序便可獲得構造如第4 C圖之晶片封裝結構。 【對照例1】使用與實例1晶片、承載板，以一般販賣之底 部填充填充材料（松下電工（股）製CV5 18 3F)以點膠設備進 行覆晶接合間隙之填充。封裝材料在一定的條件下硬化 後’所得晶片封裝結構為第2圖。 【對照例2】使用與實例1相同之晶片、承載板，除了沒有 以真空幫浦進行減壓處理外其他均相同，所得晶片封裝結 構為第4 C圖。 【實例2】除將實例1的真空度變更成第9圖所示外，其他 均相同’所得晶片封裝結構為第4 c圖。 【貫例3】除將實例1的真空度變更成第g圖所示外，其他 均相同，所得晶片封裝結構為第4C圖。11843twf.ptd Page 22 200423342 V. Description of the invention (16). On the carrier plate (F R-5) of 0.4 mm. In order to allow the current to flow uniformly, a stub wiring is added on the surface of the wafer. The flip-chip bonding gap is 50 to 7 5 micrometers: a 22 mm X 22 mm copper plate having a thickness of 0.2 mm and a thickness of 0.2 mm is bonded to the wafer using a commercially available thermally conductive adhesive. After the nickel plated on the copper plate, a 20mm 0PFA film (50 micron thickness) was sold on the market. Similarly, in order to improve the bonding strength, a surface roughening treatment is applied below, and a transfer injection molding device with a pressure reduction function of the appliance is used to perform the decompression transfer injection molding. The degree of decompression in the space is about 1 m-min. The packaging material is C V 8700 0 F 2 (the maximum particle size of the filler is 21 microns, the average particle size is 5 microns, and the added material is all silicon). The thickness of the upper mold space was 0.6 mm, and the area of the package portion was 27 mm x 27 mm. The forming is performed at 170 ° C, 70 kg / cm2 for 2 minutes, and then the post-curing process at 175 ° C and 4 hours can obtain the chip package structure as shown in Fig. 4C. [Comparative Example 1] The wafer and the carrier plate of Example 1 were used to fill a generally-filled bottom with a filling material (CV5 18 3F, manufactured by Matsushita Electric Works Co., Ltd.) to fill the chip-on-chip bonding gap with a dispensing device. The package structure obtained after the packaging material is hardened under certain conditions is shown in FIG. 2. [Comparative Example 2] The same wafer and carrier plate as in Example 1 were used except that the vacuum pump was not used for decompression treatment. The obtained chip package structure was shown in Fig. 4C. [Example 2] Except that the degree of vacuum of Example 1 was changed to that shown in Fig. 9, the other is the same. The obtained chip package structure is shown in Fig. 4c. [Exemplary Example 3] Except that the vacuum degree of Example 1 was changed to that shown in Fig. G, everything else was the same, and the obtained chip package structure was shown in Fig. 4C.
第23頁 200423342 五、發明說明（17) 【實例4】除將實例1的成形溫度變更成如第9圖所示外，· 其他均相同，所得晶片封裝結構為第4 C圖。 【實例5】除將實例1的成形溫度變更成如第9圖所示外， 其他均相同，所得晶片封裝結構為第4 C圖。 【對照例3】除將實例1所使用之材料最大粒徑變更成如第 9圖所示外，其他均相同，所得晶片封裝結構為第4C圖。 【對照例4】除將實例1所使用之材料最大粒徑變更成如第 9圖所示外，其他均相同，所得晶片封裝結構為第4C圖。 【實例6】除將實例1之PF A膠片變更為厚度5 0微米之聚醯 胺膠片外，其他均相同，所得晶片封裝結構為第4 C圖。 【實例7】除將實例1之散熱片材質變更成鋁板外，其他均 相同，所得晶片封裝結構為第4 C圖。 【實例8】除將實例1之PF A膠片厚度變更為3 0微米且進行 整體封裝（晶片封裝結構表面全部及模具内整體均被覆）， 即可獲得如第4 B圖所示上表面平整之晶片封裝結構。 【對照例5】實例8中除不使用膠片外，其他均相同，所得 晶片封裝結構為第4 B圖。 【對照例6】實例8中除不使用膠片外，且封裝厚度變更成 0 . 5毫米外，其他均相同，所得晶片封裝結構為第4B圖。 上述實例、對照例各晶片封裝結構之試驗條件與試驗 結果分別如第9圖與第1 0圖所示。 本發明所提出之較佳實施例的晶片封裝製程係採用 2 0 0 1年日本專利J P3 9 2 6 98所揭露之技術。但是，本發明針 對其封裝尺寸進行最佳化並設置散熱片，以使晶片封裝結Page 23 200423342 V. Explanation of the invention (17) [Example 4] Except that the molding temperature of Example 1 is changed as shown in Fig. 9, the others are the same, and the obtained chip package structure is shown in Fig. 4C. [Example 5] Except that the molding temperature of Example 1 was changed as shown in FIG. 9, everything else was the same, and the obtained chip package structure was shown in FIG. 4C. [Comparative Example 3] Except that the maximum particle diameter of the material used in Example 1 was changed to that shown in Fig. 9, everything else was the same, and the obtained chip package structure was shown in Fig. 4C. [Comparative Example 4] Except that the maximum particle diameter of the material used in Example 1 was changed to that shown in Fig. 9, everything else was the same, and the obtained chip package structure was shown in Fig. 4C. [Example 6] Except that the PFA film of Example 1 was changed to a polyimide film with a thickness of 50 micrometers, everything else was the same. The obtained chip package structure is shown in Figure 4C. [Example 7] Except that the material of the heat sink of Example 1 was changed to an aluminum plate, everything else was the same, and the obtained chip package structure was shown in Fig. 4C. [Example 8] Except changing the thickness of the PF A film in Example 1 to 30 micrometers and performing overall packaging (the entire surface of the chip packaging structure and the entire mold are covered), a flat surface with an upper surface as shown in Figure 4B can be obtained. Chip package structure. [Comparative Example 5] Except that no film was used in Example 8, everything was the same. The obtained chip package structure is shown in Figure 4B. [Comparative Example 6] Except that no film is used in Example 8 and the package thickness is changed to 0.5 mm, the others are the same. The obtained chip package structure is shown in FIG. 4B. The test conditions and test results of each chip package structure of the above examples and comparative examples are shown in Fig. 9 and Fig. 10, respectively. The chip packaging process of the preferred embodiment of the present invention uses the technology disclosed in Japanese Patent J P3 9 2 6 98 in 2001. However, the present invention optimizes the package size and provides a heat sink to make the chip package
11843twf.ptd 第24頁 200423342 五、發明說明（18) 構具有最佳之封裝可靠度與散熱性。 綜上所述，根據本發明所提出之較佳實施例的晶片封 裝結構，因含散熱晶片封裝結構且晶片均採同一材料一次 被覆，相較於習知之晶片封裝結構，其信賴性高且具高度 散熱效果。若使用熱傳導係數高的封裝材料，散熱效果更 佳。而且，此晶片封裝結構亦具有結構簡單，適於大量生 產之優勢。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。11843twf.ptd Page 24 200423342 V. Description of the invention (18) The structure has the best package reliability and heat dissipation. In summary, according to the chip package structure of the preferred embodiment of the present invention, since the chip package structure includes a heat dissipation chip and the wafers are covered with the same material at one time, compared with the conventional chip package structure, it has high reliability and high reliability. High heat dissipation effect. If a high thermal conductivity packaging material is used, the heat dissipation effect is better. Moreover, the chip package structure also has the advantage of being simple in structure and suitable for mass production. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.
11843twf.ptd 第25頁 200423342 圖式簡單說明 第1圖繪示為習知採導線連結式的晶片封裝結構之剖 面圖。 第2圖繪示為習知採覆晶接合技術的晶片封裝結構之 剖面圖。 第3圖繪示為習知採熱增強型球格陣列封裝的晶片封 裝結構之剖面圖。 第4 A〜4 I圖繪示為根據本發明所提出之第一較佳實施 例的各種晶片封裝結構之剖面圖。 第5圖與第6圖繪示為根據本發明所提出之第二較佳實 施例的晶片封裝結構之剖面圖。 第7 A圖繪示為根據本發明所提出之較佳實施例的晶片 封裝結構，在完成晶片封裝製程後之成品的剖面圖。 第7 B圖繪示為根據本發明所提出之較佳實施例的晶片 封裝結構，在完成晶片封裝製程後之成品經切割後的剖面 圖。 第8圖繪示為根據本發明所提出之較佳實施例的晶片 封裝結構於減壓移轉注模成形模具中形成封裝材料層的剖 面圖 。 第9圖繪示為移轉注模成形時所使用之條件。 第1 0圖繪示為移轉注模成形後所得之結果（含裝置性 能與信賴度）。 【圖式標示說明】 1 0、4 0、7 0 :晶片封裝結構 2 0 、5 0 、8 0 :晶片11843twf.ptd Page 25 200423342 Brief Description of Drawings Figure 1 shows a cross-sectional view of a conventional chip packaging structure using a wire connection type. FIG. 2 is a cross-sectional view of a chip package structure using a conventional flip-chip bonding technology. FIG. 3 is a cross-sectional view of a chip packaging structure of a conventional heat-enhanced ball grid array package. 4A to 4I are cross-sectional views of various chip packaging structures according to the first preferred embodiment of the present invention. 5 and 6 are cross-sectional views of a chip package structure according to a second preferred embodiment of the present invention. FIG. 7A is a cross-sectional view of a finished product after the chip packaging process is completed according to the preferred embodiment of the present invention. FIG. 7B is a cross-sectional view of a chip packaging structure according to a preferred embodiment of the present invention. The finished product is cut after the chip packaging process is completed. FIG. 8 is a cross-sectional view showing the formation of a packaging material layer in a reduced-pressure transfer injection molding mold for a chip packaging structure according to a preferred embodiment of the present invention. Figure 9 shows the conditions used in transfer injection molding. Figure 10 shows the results (including device performance and reliability) obtained after transfer injection molding. [Illustration of Graphical Symbols] 1 0, 4 0, 7 0: Chip package structure 2 0, 50, 8 0: Chip
11843twf.ptd 第26頁 200423342 圖式簡單說明 22、52、82:主動表面 2 4、8 4 :導線 3 0、6 0、9 0 :載板 3 2、6 2、9 2 :焊球 3 4、6 5、9 5 :封裝材料層 5 4 :凸塊 8 5 :散熱板 100、200 ·晶片封裝結構 140 、 240 :散熱片 1 4 5、2 4 5 :導熱性黏著層 1 5 0 ·晶片 1 52 :主動表面 1 6 0、2 6 0 :凸塊 1 7 0、2 7 0 :封裝材料層 1 8 0、2 8 0 :載板 1 9 0、2 9 0 :焊球 1 9 5、2 9 5 ··被動元件 2 5 0 a :第一晶片 2 5 0 b :第二晶片 2 5 0 c ··第三晶片 252a :第一主動表面 252b··第二主動表面 2 52 c :第三主動表面 2 5 4 b :導線11843twf.ptd Page 26 200423342 Brief description of drawings 22, 52, 82: Active surface 2 4, 8 4: Wire 3 0, 6 0, 9 0: Carrier board 3 2, 6 2, 9 2: Solder ball 3 4 , 6, 5, 9 5: Packaging material layer 5 4: Bump 8 5: Heat sink 100, 200 · Chip package structure 140, 240: Heat sink 1 4 5, 2 4 5: Thermally conductive adhesive layer 1 5 0 · Wafer 1 52: Active surface 1 6 0, 2 6 0: Bump 1 7 0, 2 7 0: Packaging material layer 1 8 0, 2 8 0: Carrier board 1 9 0, 2 9 0: Solder ball 1 9 5. 2 9 5 · Passive element 2 5 0 a: First wafer 2 5 0 b: Second wafer 2 5 0 c · Third wafer 252a: First active surface 252b · Second Active surface 2 52 c: First Three active surfaces 2 5 4 b: wire
11843twf.ptd 第27頁 200423342 圖式簡單說明 2 5 6 :覆晶接合間隙 260a :第一凸塊 260b :第二凸塊 3 0 0 :模具 3 1 0 :上模具 3 2 0 :下模具 3 3 0 :真空橡膠封環 3 4 0 :模具腔 3 5 0 :注膠管路 3 6 0 :柱塞 370 :抽真空管路 3 8 0 :緩衝耐熱膠片 L :切割線11843twf.ptd Page 27 200423342 Brief description of the drawing 2 5 6: flip-chip bonding gap 260 a: first bump 260 b: second bump 3 0 0: mold 3 1 0: upper mold 3 2 0: lower mold 3 3 0: Vacuum rubber seal ring 3 4 0: Mold cavity 3 5 0: Injection line 3 6 0: Plunger 370: Vacuum line 3 8 0: Buffer heat-resistant film L: Cutting line
11843twf.ptd 第28頁11843twf.ptd Page 28
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/707,687 US20040212080A1 (en) | 2003-04-22 | 2004-01-05 | [chip package structure and process for fabricating the same] |
| US11/309,106 US20070072339A1 (en) | 2003-04-22 | 2006-06-23 | Process for fabricating chip package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003117601A JP4283588B2 (en) | 2003-04-22 | 2003-04-22 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200423342A true TW200423342A (en) | 2004-11-01 |
| TWI332694B TWI332694B (en) | 2010-11-01 |
Family
ID=33497437
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW092129524A TWI332694B (en) | 2003-04-22 | 2003-10-24 | Chip package structure and process for fabricating the same |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP4283588B2 (en) |
| TW (1) | TWI332694B (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008028053A (en) * | 2006-07-20 | 2008-02-07 | Hitachi Ltd | Resin-mold power semiconductor apparatus |
| JPWO2008105535A1 (en) * | 2007-03-01 | 2010-06-03 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| JP2008218669A (en) | 2007-03-02 | 2008-09-18 | Nec Electronics Corp | Semiconductor device |
| JP5365373B2 (en) * | 2009-06-29 | 2013-12-11 | 富士通株式会社 | Electronic component package and manufacturing method thereof |
| TWI406377B (en) * | 2010-12-27 | 2013-08-21 | Powertech Technology Inc | Ball grid array package with three-dimensional pin 1 mark and its manufacturing method |
| JP2012216840A (en) * | 2011-03-31 | 2012-11-08 | Mitsubishi Chemicals Corp | Three-dimensional integrated circuit laminate |
| JP2012216838A (en) * | 2011-03-31 | 2012-11-08 | Mitsubishi Chemicals Corp | Three-dimensional integrated circuit laminate |
| EP2693476A4 (en) | 2011-03-31 | 2014-10-15 | Mitsubishi Chem Corp | Three-dimensional integrated circuit laminate and interlayer filler material for three-dimensional integrated circuit laminate |
| JP2012216839A (en) * | 2011-03-31 | 2012-11-08 | Mitsubishi Chemicals Corp | Three-dimensional integrated circuit laminate |
| US9209163B2 (en) * | 2011-08-19 | 2015-12-08 | Marvell World Trade Ltd. | Package-on-package structures |
| JP2014031460A (en) * | 2012-08-06 | 2014-02-20 | Panasonic Corp | Epoxy resin composition for encapsulation and semiconductor device using the same |
| JP5955911B2 (en) * | 2014-08-27 | 2016-07-20 | 株式会社ジェイデバイス | Semiconductor device |
| WO2019021720A1 (en) | 2017-07-24 | 2019-01-31 | 株式会社村田製作所 | Semiconductor device and production method for semiconductor device |
-
2003
- 2003-04-22 JP JP2003117601A patent/JP4283588B2/en not_active Expired - Lifetime
- 2003-10-24 TW TW092129524A patent/TWI332694B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| JP4283588B2 (en) | 2009-06-24 |
| JP2004327558A (en) | 2004-11-18 |
| TWI332694B (en) | 2010-11-01 |
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