JP2004172647A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2004172647A JP2004172647A JP2004069427A JP2004069427A JP2004172647A JP 2004172647 A JP2004172647 A JP 2004172647A JP 2004069427 A JP2004069427 A JP 2004069427A JP 2004069427 A JP2004069427 A JP 2004069427A JP 2004172647 A JP2004172647 A JP 2004172647A
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/151—Die mounting substrate
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Abstract
【解決手段】 パッケージ基板2の主面上に実装された半導体チップ8を封止部材11によって封止した構成を持つ半導体装置1において、パッケージ基板2の主面および裏面に、配線用の導体パターン4を配置した他に、その配線用の導体パターン4が配置されていない領域にダミー用の導体パターン4とを配置した。このようにパッケージ基板2における導体パターン4の密度を高めることにより、半導体装置1の製造工程中の熱処理によるパッケージ基板2の反りやうねり等を低減することができる。
【選択図】 図2
Description
(1).本発明によれば、複数の半導体チップを第1の面に実装した第1の基板を金型内にセットし、前記複数の半導体チップを一括して樹脂封止することにより封止部材を成型した後、前記金型から離形された前記第1の基板および封止部材を切断して複数の半導体装置を得ることにより、単位面積当たりの製品取得数を増加させることができるので、半導体装置の製造コストを低減することが可能となる。
(2).本発明によれば、前記第1の基板がこれを実装する第2の基板と熱膨張係数が等しくなるような絶縁材料を主体として構成されていることにより、半導体装置の信頼性を向上させることが可能となる。
図1は本発明の一実施の形態である半導体装置の斜視図、図2は図1のA1−A1線の断面図を示している。
本実施の形態2においては、前記半導体装置の製造方法の他の一例を説明する。図32および図33は、成形金型16に前記短冊基板12を搬送した状態を示している。なお、図33は、図32に直交する面の断面図である。
本実施の形態3においては、前記半導体装置の製造方法の他の一例を説明する。図38は、成形金型16に前記短冊基板12を搬送した状態を示している。
本実施の形態においては、前記半導体装置の構造の変形例を説明する。
本実施の形態においては、前記短冊基板の構造の変形例を説明する。
本実施の形態においては、前記短冊基板の構造の変形例を説明する。図47は、短冊基板12の変形例の平面図を示している。図47(a)は、短冊基板12のチップ実装面、(b)はその裏面のパッケージ実装面を示している。なお、図46においては図面を見易くするため一部にハッチングを付す。
2 パッケージ基板
3 基板本体
4 導体パターン
4m 導体パターン
5 ソルダレジスト(保護膜)
6 ベントホール
7 バンプ電極
8 半導体チップ
9 接着剤
10 ボンディングワイヤ
11 封止部材
12 短冊基板(第1の基板)
13,13a〜13e 補強パターン
14 導体膜除去領域
15a〜15c レジスト除去領域
16 成形金型
16a,16a2 下型
16b,16b2 上型
16c キャビティ
16d カルブロック
16e ゲート
16f ポット/プランジャ部
17 真空吸引孔
18 エジェクターピン
19 ツール
20 ダイシングブレード
21 電子装置
22 実装基板
23 半導体装置
24 外部端子
25 ラミネート機構部
25a ラミネートフィルム
25b リール
26 真空吸引孔
DA 半導体装置形成領域
Claims (11)
- 第1の基板の第1の面に実装された半導体チップを封止部材で封止してなる半導体装置において、前記第1の基板の前記第1の面およびそれに対向する第2の面に、配線用の導体パターンと、それが配置された領域以外の領域に配置されたダミー用の導体パターンとが設けられていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記ダミー用の導体パターンを分割して配置したことを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記第1の面、第2の面またはその両方の面における複数の半導体装置形成領域の各々の中央にダミー用の導体パターンを配置したことを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記第1、第2の面における導体パターンの配置状態が互いに近づくように各々の面に導体パターンを配置したことを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記第1の基板の前記第1、第2の面を被覆する絶縁膜を、前記配線用の導体パターンの無い領域にも設けたことを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記第1、第2の面に被覆された各々の絶縁膜の被覆状態が互いに近づくように各々の面に絶縁膜を設けたことを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記第1の基板の複数の半導体装置形成領域の各々に前記第1、第2の面間を貫通するホールを設け、前記第1の面における前記ホールの周囲に絶縁膜の一部を除去することで形成したダム領域を設けたことを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記第2の面の配線用の導体パターンにバンプ電極を設けたことを特徴とする半導体装置。
- 第1の基板の第1の面に実装された半導体チップを封止部材で封止してなる半導体装置において、前記第1の基板の前記第1、第2の面を被覆する絶縁膜を、配線用の導体パターンの無い領域にも設けたことを特徴とする半導体装置。
- 第1の基板の第1の面に実装された半導体チップを封止部材で封止してなる半導体装置において、前記第1、第2の面に被覆された各々の絶縁膜の被覆状態が互いに近づくように各々の面に絶縁膜を設けたことを特徴とする半導体装置。
- 請求項1〜10のいずれか1項に記載の半導体装置において、前記第1の基板は、これを実装する第2の基板と同一系の絶縁材料を主体として構成されていることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2004069427A JP2004172647A (ja) | 2004-03-11 | 2004-03-11 | 半導体装置 |
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JP2004069427A JP2004172647A (ja) | 2004-03-11 | 2004-03-11 | 半導体装置 |
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JP2000387825A Division JP3619773B2 (ja) | 2000-12-20 | 2000-12-20 | 半導体装置の製造方法 |
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JP2010265460A Division JP2011044747A (ja) | 2010-11-29 | 2010-11-29 | 半導体装置の製造方法 |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8431063B2 (en) | 2005-10-17 | 2013-04-30 | Intel Mobile Communications GmbH | Heat treatment for a panel and apparatus for carrying out the heat treatment method |
US8871532B2 (en) | 2011-10-20 | 2014-10-28 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
WO2014208044A1 (ja) * | 2013-06-28 | 2014-12-31 | 株式会社デンソー | 電子装置およびその電子装置の製造方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07273243A (ja) * | 1994-03-30 | 1995-10-20 | Toshiba Corp | 半導体パッケージ |
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- 2004-03-11 JP JP2004069427A patent/JP2004172647A/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07273243A (ja) * | 1994-03-30 | 1995-10-20 | Toshiba Corp | 半導体パッケージ |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8431063B2 (en) | 2005-10-17 | 2013-04-30 | Intel Mobile Communications GmbH | Heat treatment for a panel and apparatus for carrying out the heat treatment method |
US8871532B2 (en) | 2011-10-20 | 2014-10-28 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
WO2014208044A1 (ja) * | 2013-06-28 | 2014-12-31 | 株式会社デンソー | 電子装置およびその電子装置の製造方法 |
JP2015009466A (ja) * | 2013-06-28 | 2015-01-19 | 株式会社デンソー | 電子装置およびその電子装置の製造方法 |
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