JP4203489B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- JP4203489B2 JP4203489B2 JP2005075611A JP2005075611A JP4203489B2 JP 4203489 B2 JP4203489 B2 JP 4203489B2 JP 2005075611 A JP2005075611 A JP 2005075611A JP 2005075611 A JP2005075611 A JP 2005075611A JP 4203489 B2 JP4203489 B2 JP 4203489B2
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- output buffer
- output
- circuit
- sense
- buffer circuit
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- 239000004065 semiconductor Substances 0.000 title claims description 34
- 239000000872 buffer Substances 0.000 claims description 118
- 230000007704 transition Effects 0.000 claims description 7
- 238000003860 storage Methods 0.000 claims description 6
- 238000004904 shortening Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 5
- 230000003213 activating effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000009131 signaling function Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M1/00—Substation equipment, e.g. for use by subscribers
- H04M1/02—Constructional features of telephone sets
- H04M1/0202—Portable telephone sets, e.g. cordless phones, mobile phones or bar type handsets
- H04M1/026—Details of the structure or mounting of specific components
- H04M1/0264—Details of the structure or mounting of specific components for a camera module assembly
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
- G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
- G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/50—Constructional details
- H04N23/55—Optical parts specially adapted for electronic image sensors; Mounting thereof
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Hardware Design (AREA)
- Multimedia (AREA)
- Read Only Memory (AREA)
- Dram (AREA)
Description
そして、制御回路6から出力される第2センスデータラッチ制御信号Vsal2が“1”→“0”に遷移し(時間t6)、第2センスデータVout2が更新され、Vout2=Vsa=“1”となり、第2センスデータラッチ回路5に記憶される(時間t7)。以上のようにして、一つのメモリセル9に記憶された2ビットのデータを第1センスデータVout1、第2センスデータVout2として得ることが可能である。
ここで、センスデータ出力制御信号Voeが“0”→“1”になり出力バッファ回路が活性化されると、ラッチ回路62に保持されているデータVbufbと今回のセンスデータVoutが異なっている場合には、ラッチ回路62に保持されているデータVbufb、その反転データVbufがそれぞれ更新される。この時、Pchトランジスタ64およびNchトランジスタ65が同時にオンするタイミングが生じ、電源VccからグランドGNDに対して貫通電流が流れる。
3 センスアンプ
4 第1センスデータラッチ回路
5 第2センスデータラッチ回路
6、18 制御回路
7 第1の出力バッファ回路
8 第2の出力バッファ回路
9 選択セル
10〜12 リファレンス電流のリソース
13 センス線
14 リファレンス線
15 選択回路
16〜17 制御信号線
Vsa センスアンプの出力ノード
Vsal1 第1センスデータラッチ制御信号
Vsal2 第2センスデータラッチ制御信号
Vout1 第1センスデータ
Vout2 第2センスデータ
Voe1 第1センスデータ出力制御信号
Voe2 第2センスデータ出力制御信号
Vpad1 第1の出力パッド
Vpad2 第2の出力パッド
Claims (3)
- 複数ビットのデータを記憶しているメモリセルから異なる時間に複数回センス動作を行うセンスアンプと、前記センスアンプから異なる時間に出力された複数のセンスデータを各別に並列に出力する複数の出力バッファ回路と、前記出力バッファ回路の動作タイミングを制御する制御回路を備えてなる半導体記憶装置であって、
前記制御回路は、前記複数の出力バッファ回路のうち少なくとも一つが、他の少なくとも一つとの関係において対応する前記センスデータの前記センスアンプからの出力順に応じた異なるタイミングで動作するよう制御し、
前記複数の出力バッファ回路の内、最後に動作する特定の出力バッファ回路を除く前記出力バッファ回路夫々の出力遷移が、前記特定の出力バッファ回路の出力遷移終了までに完了するように、前記特定の出力バッファ回路を除く前記出力バッファ回路の夫々を構成するトランジスタの電流駆動能力を、前記特定の出力バッファ回路を構成するトランジスタの電流駆動能力より低く設定していることを特徴とする半導体記憶装置。 - 前記制御回路は、前記複数の出力バッファ回路のすべてが、対応する前記センスデータの前記センスアンプからの出力順に応じた異なるタイミングで動作するよう制御することを特徴とする請求項1に記載の半導体記憶装置。
- 前記トランジスタの電流駆動能力を、前記トランジスタのチャネル幅を短くすることにより低く設定することを特徴とする請求項1または2に記載の半導体記憶装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005075611A JP4203489B2 (ja) | 2005-03-16 | 2005-03-16 | 半導体記憶装置 |
KR1020060024541A KR100680562B1 (ko) | 2005-03-16 | 2006-03-16 | 반도체 기억 장치 |
US11/378,214 US7301827B2 (en) | 2005-03-16 | 2006-03-16 | Semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005075611A JP4203489B2 (ja) | 2005-03-16 | 2005-03-16 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006260660A JP2006260660A (ja) | 2006-09-28 |
JP4203489B2 true JP4203489B2 (ja) | 2009-01-07 |
Family
ID=37034982
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005075611A Active JP4203489B2 (ja) | 2005-03-16 | 2005-03-16 | 半導体記憶装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7301827B2 (ja) |
JP (1) | JP4203489B2 (ja) |
KR (1) | KR100680562B1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100694978B1 (ko) * | 2006-05-12 | 2007-03-14 | 주식회사 하이닉스반도체 | 데이터 입출력 속도를 증가시키는 구조를 가지는 플래시메모리 장치 및 그 데이터 입출력 동작 방법 |
KR100911197B1 (ko) * | 2007-12-27 | 2009-08-06 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 데이터 출력 회로 |
CN106356095B (zh) * | 2016-09-13 | 2019-11-15 | 中国科学院微电子研究所 | 一种用于非易失性存储器的读操作方法及装置 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5218569A (en) * | 1991-02-08 | 1993-06-08 | Banks Gerald J | Electrically alterable non-volatile memory with n-bits per memory cell |
JPH05100778A (ja) | 1991-10-04 | 1993-04-23 | Nec Ic Microcomput Syst Ltd | 半導体出力回路 |
JP3179943B2 (ja) * | 1993-07-12 | 2001-06-25 | 株式会社東芝 | 半導体記憶装置 |
JP2001084784A (ja) | 1999-09-08 | 2001-03-30 | Toshiba Corp | 半導体記憶装置 |
KR100326922B1 (ko) * | 1999-09-09 | 2002-03-13 | 윤종용 | 반도체 메모리 장치 |
JP2003008424A (ja) | 2001-06-25 | 2003-01-10 | Matsushita Electric Ind Co Ltd | 半導体装置のノイズ低減回路 |
KR20030066997A (ko) * | 2002-02-06 | 2003-08-14 | 주식회사 하이닉스반도체 | 데이터 출력 버퍼 블록 및 이의 구동 방법 |
KR100525095B1 (ko) * | 2003-03-31 | 2005-11-01 | 주식회사 하이닉스반도체 | 메모리 장치의 입력 버퍼에 발생하는 노이즈 방지 장치 및그 방법 |
KR100492781B1 (ko) * | 2003-05-23 | 2005-06-07 | 주식회사 하이닉스반도체 | 멀티비트 제어 기능을 갖는 불휘발성 강유전체 메모리 장치 |
KR100604864B1 (ko) * | 2004-06-03 | 2006-07-26 | 삼성전자주식회사 | 입출력 핀을 통하여 전송되는 신호의 특성을 제어하는반도체 장치 및 신호 특성 제어 방법 |
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2005
- 2005-03-16 JP JP2005075611A patent/JP4203489B2/ja active Active
-
2006
- 2006-03-16 US US11/378,214 patent/US7301827B2/en active Active
- 2006-03-16 KR KR1020060024541A patent/KR100680562B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
JP2006260660A (ja) | 2006-09-28 |
US20060215468A1 (en) | 2006-09-28 |
KR20060100291A (ko) | 2006-09-20 |
KR100680562B1 (ko) | 2007-02-08 |
US7301827B2 (en) | 2007-11-27 |
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