JP4154306B2 - リジット基板を用いた半導体装置の製造方法 - Google Patents
リジット基板を用いた半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4154306B2 JP4154306B2 JP2003338147A JP2003338147A JP4154306B2 JP 4154306 B2 JP4154306 B2 JP 4154306B2 JP 2003338147 A JP2003338147 A JP 2003338147A JP 2003338147 A JP2003338147 A JP 2003338147A JP 4154306 B2 JP4154306 B2 JP 4154306B2
- Authority
- JP
- Japan
- Prior art keywords
- rigid substrate
- substrate
- resin
- mold
- rigid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 title claims description 169
- 239000004065 semiconductor Substances 0.000 title claims description 97
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 229920005989 resin Polymers 0.000 claims description 105
- 239000011347 resin Substances 0.000 claims description 105
- 238000007789 sealing Methods 0.000 claims description 52
- 238000000034 method Methods 0.000 description 50
- 238000000465 moulding Methods 0.000 description 32
- 238000002347 injection Methods 0.000 description 23
- 239000007924 injection Substances 0.000 description 23
- 229910000679 solder Inorganic materials 0.000 description 22
- 239000010408 film Substances 0.000 description 7
- 239000013039 cover film Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000001721 transfer moulding Methods 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
図9は、図8のリジット基板を用いた半導体装置の一括モールド工程を説明するための図である。図9(a)は半導体装置の一括モールド工程における樹脂注入前の状態を示し、図9(b)は樹脂注入後の状態を示す。
まず、図9(a)に示すように、リジット基板1を上金型2と下金型3の間に配置する。
1a、1b チップアレイ領域
2 上金型
2a キャビティ
3 下金型
4 基板ベント側端部
5 基板ゲート側端部
7、7a、7b、7c、7d ソルダレジスト除去部
8 下金型形状変更部
9 ワイヤ変形
11 樹脂
12 ダイシングライン
13 ダイシングライン
20 リリースフィルム
21 スリット
22 カバーフィルム
Claims (2)
- 表面に1又は複数個の半導体素子を支持するリジット基板を樹脂封止するための金型へ配置した際に金型のベント側で上金型と下金型により挟み込まれる部分の基板端部における、半導体素子支持面の反対側の裏面側に切欠き部を形成して該基板端部の板厚を他の部分の板厚より薄くする工程と、
前記リジット基板を金型に配置する工程と、
前記金型の上金型と前記リジット基板との間に樹脂を流し込み前記半導体素子を樹脂封止する工程と
を含むことを特徴とする半導体装置の製造方法。 - 前記切欠き部を形成する部分は前記基板端部の一部分のみとすることを特徴とする請求項1記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003338147A JP4154306B2 (ja) | 2003-09-29 | 2003-09-29 | リジット基板を用いた半導体装置の製造方法 |
US10/781,794 US7122402B2 (en) | 2003-09-29 | 2004-02-20 | Method of manufacturing a semiconductor device using a rigid substrate including the vent-end edge portion of the substrate has a thickness smaller than the other portions of the substrate |
US11/516,584 US7781259B2 (en) | 2003-09-29 | 2006-09-07 | Method of manufacturing a semiconductor using a rigid substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003338147A JP4154306B2 (ja) | 2003-09-29 | 2003-09-29 | リジット基板を用いた半導体装置の製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008130919A Division JP4691575B2 (ja) | 2008-05-19 | 2008-05-19 | リジット基板を用いた半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005109019A JP2005109019A (ja) | 2005-04-21 |
JP4154306B2 true JP4154306B2 (ja) | 2008-09-24 |
Family
ID=34373302
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003338147A Expired - Fee Related JP4154306B2 (ja) | 2003-09-29 | 2003-09-29 | リジット基板を用いた半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US7122402B2 (ja) |
JP (1) | JP4154306B2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090026656A1 (en) * | 2007-07-23 | 2009-01-29 | Bautista Jr Jesus Bajo | Vented mold for encapsulating semiconductor components |
TWI770110B (zh) * | 2017-03-30 | 2022-07-11 | 日商日本碍子股份有限公司 | 暫時固定基板及電子元件的暫時固定方法 |
US11469149B2 (en) * | 2019-11-15 | 2022-10-11 | Semtech Corporation | Semiconductor device and method of forming mold degating structure for pre-molded substrate |
JP7465829B2 (ja) * | 2021-02-17 | 2024-04-11 | Towa株式会社 | 樹脂成形品の製造方法、成形型及び樹脂成形装置 |
US11955347B2 (en) * | 2021-12-02 | 2024-04-09 | Asmpt Singapore Pte. Ltd. | Encapsulation process for double-sided cooled packages |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4913638A (en) * | 1988-06-20 | 1990-04-03 | Eastman Kodak Company | Apparatus for operating an injection molding process utilizing an acceptable part and process window |
DE69524429T2 (de) * | 1994-09-08 | 2002-05-23 | Idemitsu Kosan Co | Verfahren zur abdichtung eines organischen elektrolumineszenten elements und organisches elektrolumineszentes element |
JPH09116050A (ja) | 1995-10-24 | 1997-05-02 | Oki Electric Ind Co Ltd | 樹脂封止半導体装置 |
US6081997A (en) * | 1997-08-14 | 2000-07-04 | Lsi Logic Corporation | System and method for packaging an integrated circuit using encapsulant injection |
JP2000058716A (ja) | 1998-08-14 | 2000-02-25 | Toshiba Corp | 半導体装置 |
JP2002110718A (ja) | 2000-09-29 | 2002-04-12 | Hitachi Ltd | 半導体装置の製造方法 |
JP4581301B2 (ja) | 2001-06-29 | 2010-11-17 | ソニー株式会社 | 半導体パッケージ |
JP2003077946A (ja) * | 2001-08-31 | 2003-03-14 | Hitachi Ltd | 半導体装置の製造方法 |
US20030201592A1 (en) * | 2002-04-26 | 2003-10-30 | Rich Cummines | Apparatus and method for a compression spindle assembly for clamping |
-
2003
- 2003-09-29 JP JP2003338147A patent/JP4154306B2/ja not_active Expired - Fee Related
-
2004
- 2004-02-20 US US10/781,794 patent/US7122402B2/en not_active Expired - Fee Related
-
2006
- 2006-09-07 US US11/516,584 patent/US7781259B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20050070051A1 (en) | 2005-03-31 |
US20070010046A1 (en) | 2007-01-11 |
JP2005109019A (ja) | 2005-04-21 |
US7781259B2 (en) | 2010-08-24 |
US7122402B2 (en) | 2006-10-17 |
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