JP3116215B2 - 二重ディレクトリー仮想キャッシュの制御方法 - Google Patents
二重ディレクトリー仮想キャッシュの制御方法Info
- Publication number
- JP3116215B2 JP3116215B2 JP08342315A JP34231596A JP3116215B2 JP 3116215 B2 JP3116215 B2 JP 3116215B2 JP 08342315 A JP08342315 A JP 08342315A JP 34231596 A JP34231596 A JP 34231596A JP 3116215 B2 JP3116215 B2 JP 3116215B2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- tag
- virtual
- entry
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950041977A KR970029072A (ko) | 1995-11-17 | 1995-11-17 | 이중 디렉토리 가상 캐쉬 및 그 제어 방법 |
KR1995P41977 | 1995-11-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH1091521A JPH1091521A (ja) | 1998-04-10 |
JP3116215B2 true JP3116215B2 (ja) | 2000-12-11 |
Family
ID=19434528
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP08342315A Expired - Fee Related JP3116215B2 (ja) | 1995-11-17 | 1996-11-18 | 二重ディレクトリー仮想キャッシュの制御方法 |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP3116215B2 (ko) |
KR (1) | KR970029072A (ko) |
GB (1) | GB2307319B (ko) |
TW (1) | TW324800B (ko) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6598128B1 (en) * | 1999-10-01 | 2003-07-22 | Hitachi, Ltd. | Microprocessor having improved memory management unit and cache memory |
US7139877B2 (en) * | 2003-01-16 | 2006-11-21 | Ip-First, Llc | Microprocessor and apparatus for performing speculative load operation from a stack memory cache |
US7139876B2 (en) | 2003-01-16 | 2006-11-21 | Ip-First, Llc | Microprocessor and apparatus for performing fast speculative pop operation from a stack memory cache |
US7136990B2 (en) | 2003-01-16 | 2006-11-14 | Ip-First, Llc. | Fast POP operation from RAM cache using cache row value stack |
US7191291B2 (en) | 2003-01-16 | 2007-03-13 | Ip-First, Llc | Microprocessor with variable latency stack cache |
US8612690B2 (en) * | 2012-01-17 | 2013-12-17 | Qualcomm Incorporated | Method for filtering traffic to a physically-tagged data cache |
US10831664B2 (en) | 2017-06-16 | 2020-11-10 | International Business Machines Corporation | Cache structure using a logical directory |
US10606762B2 (en) * | 2017-06-16 | 2020-03-31 | International Business Machines Corporation | Sharing virtual and real translations in a virtual cache |
US10698836B2 (en) | 2017-06-16 | 2020-06-30 | International Business Machines Corporation | Translation support for a virtual cache |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB8823077D0 (en) * | 1988-09-30 | 1988-11-09 | Int Computers Ltd | Data processing apparatus |
GB2260429B (en) * | 1991-10-11 | 1995-05-24 | Intel Corp | Versatile cache memory |
EP0651332B1 (en) * | 1993-10-29 | 2001-07-18 | Advanced Micro Devices, Inc. | Linearly addressable microprocessor cache |
-
1995
- 1995-11-17 KR KR1019950041977A patent/KR970029072A/ko not_active IP Right Cessation
-
1996
- 1996-11-18 JP JP08342315A patent/JP3116215B2/ja not_active Expired - Fee Related
- 1996-11-18 GB GB9623913A patent/GB2307319B/en not_active Expired - Fee Related
- 1996-11-21 TW TW085114360A patent/TW324800B/zh active
Also Published As
Publication number | Publication date |
---|---|
GB9623913D0 (en) | 1997-01-08 |
TW324800B (en) | 1998-01-11 |
JPH1091521A (ja) | 1998-04-10 |
KR970029072A (ko) | 1997-06-26 |
GB2307319B (en) | 2000-05-31 |
GB2307319A (en) | 1997-05-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7653789B2 (en) | Multiprocessor system that supports both coherent and non-coherent memory accesses | |
KR930004430B1 (ko) | 가상 캐쉬를 이용하는 다중 처리컴퓨터 시스템의 일치성 유지장치 | |
US7032074B2 (en) | Method and mechanism to use a cache to translate from a virtual bus to a physical bus | |
US5860146A (en) | Auxiliary translation lookaside buffer for assisting in accessing data in remote address spaces | |
US5996048A (en) | Inclusion vector architecture for a level two cache | |
US7496730B2 (en) | System and method for reducing the number of translation buffer invalidates an operating system needs to issue | |
JPH03142644A (ja) | キャッシュメモリ制御方法とこのキャッシュメモリ制御方法を用いたプロセッサおよび情報処理装置 | |
JPH0743670B2 (ja) | ストアスルーキャッシュ管理システム | |
JPS6135584B2 (ko) | ||
JPH08272693A (ja) | 仮想アドレスについてのキャッシュ可能性属性ビットを備えた変換テーブル・エントリ及びそのビットを用いた仮想アドレスの参照方法並びにその仮想アドレスの参照装置 | |
US7093080B2 (en) | Method and apparatus for coherent memory structure of heterogeneous processor systems | |
JP3116215B2 (ja) | 二重ディレクトリー仮想キャッシュの制御方法 | |
JP3295436B2 (ja) | マイクロプロセッサキャッシュの一貫性 | |
JPH10501914A (ja) | 共用キャッシュ・メモリ装置 | |
US20050091459A1 (en) | Flexible mechanism for enforcing coherency among caching structures | |
US5619673A (en) | Virtual access cache protection bits handling method and apparatus | |
US11561898B1 (en) | Address expansion | |
JP3626609B2 (ja) | マルチプロセッサシステム | |
US20020002659A1 (en) | System and method for improving directory lookup speed | |
CN117099087A (zh) | 用于处理储存请求的装置和方法 | |
JPH01288940A (ja) | 論理アドレスキャッシュ制御方式 | |
JPH03230238A (ja) | キャッシュメモリ制御方式 | |
JP2976980B2 (ja) | キャッシュ制御方式 | |
JP3507314B2 (ja) | メモリコントローラおよびコンピュータシステム | |
JP2637853B2 (ja) | キャッシュメモリ装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S633 | Written request for registration of reclamation of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313633 |
|
R360 | Written notification for declining of transfer of rights |
Free format text: JAPANESE INTERMEDIATE CODE: R360 |
|
R371 | Transfer withdrawn |
Free format text: JAPANESE INTERMEDIATE CODE: R371 |
|
S633 | Written request for registration of reclamation of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313633 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R360 | Written notification for declining of transfer of rights |
Free format text: JAPANESE INTERMEDIATE CODE: R360 |
|
R371 | Transfer withdrawn |
Free format text: JAPANESE INTERMEDIATE CODE: R371 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |