JP2022071220A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2022071220A JP2022071220A JP2022039747A JP2022039747A JP2022071220A JP 2022071220 A JP2022071220 A JP 2022071220A JP 2022039747 A JP2022039747 A JP 2022039747A JP 2022039747 A JP2022039747 A JP 2022039747A JP 2022071220 A JP2022071220 A JP 2022071220A
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
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Abstract
Description
特許文献1 国際公開2005/109521号パンフレット
Claims (10)
- 第1導電型のドリフト領域と、
半導体基板の上面と前記ドリフト領域との間に形成された第2導電型のベース領域と、
前記半導体基板の上面から前記ベース領域を貫通して形成されたゲートトレンチ部と、
前記半導体基板の上面から前記ベース領域を貫通して形成されたダミートレンチ部と、
前記ゲートトレンチ部および前記ダミートレンチ部に挟まれた第1メサ部において、前記半導体基板の上面から内部まで設けられた接続部と、
前記ゲートトレンチ部に隣接する、前記ドリフト領域よりもドーピング濃度が高い第1導電型のエミッタ領域と、
前記接続部の底面に接触する、前記ベース領域よりもドーピング濃度が高い第2導電型のコンタクト領域と、
前記半導体基板の上面の上方に設けられ、前記接続部と接触するエミッタ電極と、
前記半導体基板の上面と前記エミッタ電極との間に設けられた層間絶縁膜と、
を備え、
前記ゲートトレンチ部および前記ダミートレンチ部の配列方向の断面において、
前記ダミートレンチ部は、
前記層間絶縁膜に形成されたコンタクトホールを介して前記エミッタ電極と接続された第1ダミートレンチ部と、
前記層間絶縁膜により上方が覆われた第2ダミートレンチ部と、
を有する半導体装置。 - 前記断面において、前記ゲートトレンチ部および前記ダミートレンチ部に挟まれ、前記層間絶縁膜により上面が覆われた第2メサ部を有する
請求項1に記載の半導体装置。 - 前記エミッタ領域は、前記第1メサ部に設けられ、前記第2メサ部には設けられていない
請求項2に記載の半導体装置。 - 前記エミッタ領域は、上面視において、前記コンタクトホールに沿う方向に延伸して配置されている
請求項1から3のいずれか一項に記載の半導体装置。 - 前記コンタクト領域は、上面視において、前記コンタクトホールに沿う方向に延伸して配置されている
請求項1から4のいずれか一項に記載の半導体装置。 - 前記配列方向において、2つの前記ゲートトレンチ部の間には2つ以下の前記ダミートレンチ部が設けられている
請求項1から5のいずれか一項に記載の半導体装置。 - 前記接続部は、タングステンを含んだ金属で形成されている
請求項1から6のいずれか一項に記載の半導体装置。 - 前記コンタクトホールの下側に、前記半導体基板の上面から内部まで設けられた第2接続部を更に備え、
前記第2接続部は、タングステンを含んだ金属で形成されている
請求項1から7のいずれか一項に記載の半導体装置。 - 前記ゲートトレンチ部の下端および前記ダミートレンチ部の下端よりも下端が深く、前記ベース領域よりもドーピング濃度が高い第2導電型のウェル領域を更に備え、
前記ベース領域、前記コンタクトホールおよび前記第2接続部は、前記ウェル領域よりも内側に設けられている
請求項8に記載の半導体装置。 - 前記断面は、前記エミッタ領域を通過する断面である
請求項1から9のいずれか一項に記載の半導体装置。
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US10256331B2 (en) * | 2017-03-03 | 2019-04-09 | Pakal Technologies, Inc. | Insulated gate turn-off device having low capacitance and low saturation current |
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US11081554B2 (en) * | 2017-10-12 | 2021-08-03 | Semiconductor Components Industries, Llc | Insulated gate semiconductor device having trench termination structure and method |
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JP7279356B2 (ja) * | 2018-12-19 | 2023-05-23 | 富士電機株式会社 | 半導体装置 |
JP7351086B2 (ja) * | 2019-03-05 | 2023-09-27 | 富士電機株式会社 | 絶縁ゲート型半導体装置及びその製造方法 |
JP7199270B2 (ja) | 2019-03-20 | 2023-01-05 | 株式会社東芝 | 半導体装置及び半導体回路 |
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US11694984B2 (en) * | 2019-08-30 | 2023-07-04 | Advanced Semiconductor Engineering, Inc. | Package structure including pillars and method for manufacturing the same |
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