JP2020074562A - フェライトビーズを有するスイッチング回路 - Google Patents
フェライトビーズを有するスイッチング回路 Download PDFInfo
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- 239000011324 bead Substances 0.000 title claims abstract description 76
- 229910000859 α-Fe Inorganic materials 0.000 title claims abstract description 75
- 230000003071 parasitic effect Effects 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 230000001627 detrimental effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 22
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- 239000000758 substrate Substances 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- UQSXHKLRYXJYBZ-UHFFFAOYSA-N Iron oxide Chemical compound [Fe]=O UQSXHKLRYXJYBZ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
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- 230000001052 transient effect Effects 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
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Abstract
Description
Claims (35)
- 少なくとも第1のリードを備えた電子構成要素パッケージ、
前記電子構成要素パッケージ内のIII‐N装置であって、ドレイン、ゲート、及びソースを備え、前記ソースが前記第1のリードに接続されている、III‐N装置、
第1の端子及び第2の端子を備えたゲートドライバであって、前記第1の端子が前記第1のリードに接続されている、ゲートドライバ、並びに
前記III‐Nトランジスタの前記ゲートと前記ゲートドライバの前記第2の端子との間に接続されているフェライトビーズを備える、回路。 - 前記ゲートドライバの前記第2の端子、前記フェライトビーズ、前記III‐N装置、前記第1のリード、及び前記第1の端子が、ゲートループを形成し、前記第1のリードが、寄生インダクタンスを有し、前記フェライトビーズが、前記寄生インダクタンスによる前記ゲートループ内の振動及び電磁干渉を低減させるように構成されている、請求項1に記載の回路。
- 前記III‐N装置及び前記電子構成要素パッケージがローサイドスイッチを形成し、前記第1のリードがグランドノードに接続され、前記回路が前記III‐N装置の前記ドレインと高電圧ノードとの間に接続されたハイサイドスイッチを更に備え、前記ハイサイドスイッチが前記ゲートドライバの第3の端子に接続されたハイサイドゲートを備える、請求項1に記載の回路。
- 前記ゲートドライバが、前記第1の端子に対して前記第2の端子にローサイド制御信号を印加し、前記ゲートドライバの第4の端子に対して前記第3の端子にハイサイド制御信号を印加するように構成され、前記第4の端子が、前記ハイサイドスイッチのハイサイドソースに接続されている、請求項3に記載の回路。
- 前記ゲートドライバと少なくとも1つの他のゲートドライバとに接続されたプロセッサ、及び
実行可能な指示命令であって、前記プロセッサによって実行されたときに、前記プロセッサが前記回路をハーフブリッジとして動作させるように前記ゲートドライバと前記他のゲートドライバを制御することをもたらす、指示命令を記憶しているメモリを備える、請求項3に記載の回路。 - 前記グランドノードに対する前記高電圧ノードにおける電圧が、約400V以上である、請求項3に記載の回路。
- 前記ゲートドライバが、前記第1の端子に対して前記第2の端子に制御信号を印加するように構成され、前記制御信号が、30kHzと10MHzの間の周波数を有している、請求項6に記載の回路。
- 前記ハイサイドゲートと前記ゲートドライバの前記第3の端子との間に接続された、第2のフェライトビーズを更に備える、請求項3に記載の回路。
- 前記ゲートドライバが、前記第1の端子に対して前記第2の端子に制御信号を印加するように構成され、前記制御信号が、30kHzと10MHzの間の周波数を有している、請求項1に記載の回路。
- 前記III‐N装置が、エンハンスメントモードトランジスタである、請求項1に記載の回路。
- 前記III‐N装置が、ディプリーションモードのIII‐Nトランジスタとエンハンスメントモードのシリコントランジスタとを備えた、ハイブリッド装置である、請求項1に記載の回路。
- 前記フェライトビーズが、100MHzより上の周波数を有する電磁干渉を遮断するように構成された、受動的なローパスフィルタを形成している、請求項1に記載の回路。
- 前記電子構成要素パッケージが、第2のリードであって、前記ソースとグランドノードとに接続された、第2のリードを更に備え、前記第1のリードが、前記ゲートドライバの前記第1の端子と電気的に接続されている、請求項1に記載の回路。
- 第1及び第2のハイサイド出力端子と第1及び第2のローサイド出力端子とを備えたゲートドライバ、
ハイサイドIII‐N装置であって、
前記ゲートドライバの前記第1のハイサイド出力端子に接続されたハイサイドゲートと、
高電圧ノードに接続されたハイサイドドレインと、
負荷ノードに接続されたハイサイドソースとを備えた、ハイサイドIII‐N装置、
ローサイドIII‐N装置であって、
前記ゲートドライバの前記第1のローサイド出力端子に接続されたローサイドゲートと、
前記負荷ノードに接続されたローサイドドレインと、
グランドノードに接続されたローサイドソースとを備えた、ローサイドIII‐N装置、並びに
前記ハイサイドゲートと前記ゲートドライバの前記第1のハイサイド出力端子との間に接続されたフェライトビーズを備える、回路。 - 前記ゲートドライバに接続されたプロセッサ、及び
実行可能な指示命令であって、前記プロセッサによって実行されたときに、前記プロセッサが前記回路をハーブリッジとして動作させるように前記ゲートドライバを制御することをもたらす、指示命令を記憶しているメモリを備える、請求項14に記載の回路。 - 前記回路の動作の間に、前記グランドノードに対する前記高電圧ノードにおける電圧が、少なくとも約400Vである、請求項14に記載の回路。
- 前記ゲートドライバが、前記第2のハイサイド出力端子に対して前記第1のハイサイド出力端子に制御信号を印加し、前記第2のローサイド出力端子に対して前記第1のローサイド出力端子に制御信号を印加するように構成され、前記制御信号が、30kHzと10MHzの間の周波数を有している、請求項14に記載の回路。
- 前記ハイサイドIII‐N装置が、III‐Nエンハンスメントモードトランジスタを備える、請求項14に記載の回路。
- 前記ハイサイドIII‐N装置が、ディプリーションモードのIII‐Nトランジスタとエンハンスメントモードのシリコントランジスタとを備えた、ハイブリッド装置である、請求項14に記載の回路。
- 前記フェライトビーズが、100MHzより上の周波数を有する電磁干渉を遮断するように構成された、受動的なローパスフィルタを形成している、請求項14に記載の回路。
- 少なくとも第1のリードを含む電子パッケージ、
ゲートを備えたIII‐Nスイッチング装置であって、前記電子パッケージ内に入れられた、III‐Nスイッチング装置、及び
前記電子パッケージ内に入れられたフェライトビーズであって、前記ゲートと前記第1のリードとの間に接続された、フェライトビーズを備える、電子構成要素。 - 前記III‐Nスイッチング装置が、ディプリーションモードのIII‐Nトランジスタとエンハンスメントモードトランジスタとを備えた、ハイブリッド装置であり、前記ゲートが前記エンハンスメントモードトランジスタの第1のゲートである、請求項21に記載の電子構成要素。
- 前記電子パッケージが、導電性構造ベースを更に備え、前記ディプリーションモードのIII‐Nトランジスタが、第2のゲートを備えたラテラルIII‐Nトランジスタであり、前記III‐Nトランジスタの前記第2のゲートが、前記電子パッケージの前記導電性構造ベースと電気的に接続されている、請求項22に記載の電子構成要素。
- 前記電子パッケージが、導電性構造ベースを更に備え、前記III‐Nスイッチング装置と前記フェライトビーズが、両方とも、前記導電性構造ベース上に取り付けられている、請求項21に記載の電子構成要素。
- 前記フェライトビーズと前記ゲートとの間の第1のワイヤー接合、及び前記フェライトビーズと前記第1のリードとの間の第2のワイヤー接合を備える、請求項21に記載の電子構成要素。
- 前記III‐Nスイッチング装置が、前記電子パッケージの第2及び第3のリードに接続されたソース及びドレインを備えたIII‐Nトランジスタを備え、前記電子パッケージが、直接的に前記ソースをゲートドライバに接続するために前記ソースに接続された第4のリードを含む、請求項21に記載の電子構成要素。
- 前記III‐Nスイッチング装置が、エンハンスメントモードのIII‐Nトランジスタを備える、請求項21に記載の電子構成要素。
- 前記電子パッケージが、導電性構造ベースを更に備え、前記エンハンスメントモードのIII‐Nトランジスタが、ラテラルIII‐Nトランジスタであり、前記ゲートが、前記エンハンスメントモードのIII‐Nトランジスタのゲートであり、且つ、前記エンハンスメントモードのIII‐Nトランジスタのソース又はドレインが、前記電子パッケージの前記導電性構造ベースと電気的に接続されている、請求項27に記載の電子構成要素。
- ハイサイド及びローサイド出力端子を備えたゲートドライバ、
第1の電子構成要素であって、
第1の導電性構造ベースを備えた第1の電子パッケージと、
前記第1の電子パッケージ内に入れられたハイサイドIII‐N装置であって、前記第1の電子パッケージ内に入れられたフェライトビーズによって前記ゲートドライバの前記ハイサイド出力端子に接続されたハイサイドゲート、負荷ノードに接続されたハイサイドソース、及び前記第1の電子パッケージの前記第1の導電性構造ベースによって高電圧ノードに接続されたハイサイドドレインを備えた、ハイサイドIII‐N装置とを備えた、第1の電子構成要素、並びに
第2の電子構成要素であって、
第2の導電性構造ベースを備えた第2の電子パッケージと、
前記第2の電子パッケージ内に入れられたローサイドIII‐N装置であって、前記ゲートドライバの前記ローサイド出力端子に接続されたローサイドゲート、前記負荷ノードに接続されたローサイドドレイン、及び前記第2の電子パッケージの前記第2の導電性構造ベースによってグランドノードに接続されたローサイドソースを備えた、ローサイドIII‐N装置とを備えた、第2の電子構成要素を備える、回路。 - 前記ゲートドライバに接続されたプロセッサ、及び
実行可能な指示命令であって、前記プロセッサによって実行されたときに、前記プロセッサが前記回路をハーブリッジとして動作させるように前記ゲートドライバを制御することをもたらす、指示命令を記憶しているメモリを備える、請求項29に記載の回路。 - 動作の間に、前記グランドノードに対する前記高電圧ノードにおける電圧が約400V以上であるように構成されている、請求項29に記載の回路。
- 前記ゲートドライバが、前記ハイサイド及びローサイド出力端子にそれぞれの制御信号を出力するように構成され、前記制御信号が、50kHzと1MHzの間の周波数を有している、請求項29に記載の回路。
- 前記ハイサイドIII‐N装置が、エンハンスメントモードトランジスタである、請求項29に記載の回路。
- 前記ハイサイドIII‐N装置が、ディプリーションモードのIII‐Nトランジスタとエンハンスメントモードトランジスタとを備えた、ハイブリッド装置である、請求項29に記載の回路。
- 前記フェライトビーズが、100MHzより上の周波数を有する電磁干渉を遮断するように構成された、受動的なローパスフィルタを形成している、請求項29に記載の回路。
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