JP2014199905A - 半導体装置および半導体装置の作製方法 - Google Patents
半導体装置および半導体装置の作製方法 Download PDFInfo
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- JP2014199905A JP2014199905A JP2013211070A JP2013211070A JP2014199905A JP 2014199905 A JP2014199905 A JP 2014199905A JP 2013211070 A JP2013211070 A JP 2013211070A JP 2013211070 A JP2013211070 A JP 2013211070A JP 2014199905 A JP2014199905 A JP 2014199905A
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- oxide semiconductor
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Abstract
【解決手段】下地絶縁層と、下地絶縁層上の酸化物半導体層を含む酸化物積層と、酸化物積層上のソース電極層およびドレイン電極層と、酸化物積層、ソース電極層およびドレイン電極層上のゲート絶縁層と、ゲート絶縁層上のゲート電極層と、ゲート電極層上の層間絶縁層と、を有する半導体装置において、酸化物半導体層中の欠陥密度を低減する。
【選択図】図1
Description
本発明の一態様の半導体装置であるトランジスタ420について図1に示す。図1(B)は、トランジスタ420の上面図であり、図1(A)は図1(B)に示す一点鎖線A−Bにおける断面図である。
酸化物積層404は、酸化物層404aと、酸化物層404a上の酸化物半導体層404bと、酸化物半導体層404b上の酸化物層404cとを有する。ここでは、酸化物積層404が3層である場合を示すが、酸化物積層は少なくとも酸化物半導体層を有する多数の酸化物層の積層であればよく、2層であってもよいし、4層以上であっても構わない。例えば、酸化物半導体層と、酸化物半導体層とゲート絶縁層との間に形成された酸化物層との2層であってもよいし、下地絶縁層上に酸化物層が形成され、酸化物半導体層が形成されていてもよい。
酸化物積層404のバンド構造について、図2を用いて説明する。図2に示すバンド構造は、酸化物層404aとしてエネルギーギャップが3.15eVであるIn−Ga−Zn酸化物を用い、酸化物半導体層404bとしてエネルギーギャップが2.8eVであるIn−Ga−Zn酸化物を用い、酸化物層404cとして酸化物層404aと同様の物性を有する酸化物層を用いた。また、酸化物層404aと酸化物半導体層404bとの界面近傍のエネルギーギャップを3eVとし、酸化物層404cと酸化物半導体層404bとの界面近傍のエネルギーギャップを3eVとした。エネルギーギャップは、分光エリプソメータ(HORIBA JOBIN YVON社 UT−300)を用いて測定した。また、酸化物層404aの厚さを10nm、酸化物半導体層404bの厚さを10nm、酸化物層404cの厚さを10nmとした。
酸化物積層404を用いたトランジスタに安定した電気特性を付与するためには、酸化物半導体層404bを高純度真性化することが有効である。具体的には、酸化物半導体層404bのキャリア密度を1×1017/cm3未満、1×1015/cm3未満、または1×1013/cm3未満とすればよい。酸化物半導体層404bにおいて、水素、窒素、炭素、シリコン、および主成分以外の金属元素は不純物となる。酸化物半導体層404b中の不純物濃度を低減するためには、近接する酸化物層404a中および酸化物層404c中の不純物濃度も酸化物半導体層404bと同程度まで低減することが好ましい。
酸化物半導体層404bに形成される酸素欠損はドナーを形成し、キャリアとなるため、酸化物半導体層中に酸素欠損が形成されると、トランジスタの特性が変化し、信頼性が低下する。そのため、酸化物半導体層中に含まれる酸素欠損は低減されていることが好ましい。例えば、磁場の向きを膜面に対して平行に印加した電子スピン共鳴法によるg値が1.93(1.90以上1.95以下)の信号に対応するスピン密度は、1.5×1018spins/cm3以下、好ましくは1×1017spins/cm3以下であるとよい。また、g値が1.93の信号に対応する単位面積当たりのスピン密度が1.5×1012spins/cm2以下、好ましくは1×1011spins/cm2以下であるとよい。なお、電子スピン共鳴法におけるg値が1.93の信号に対応するスピン密度は、酸化物半導体層中に含まれる酸素欠損の存在量に対応する。なお、酸化物半導体層の組成等によって、酸素欠損に対応するg値は異なるため、検出されるg値には、例えばプラスマイナス5%程度ずれて信号が現れてもよく、ここでは1.90以上1.95以下程度の値であればよい。酸化物半導体層に含まれる酸素欠損をできる限り低減することで、キャリアの生成を低減することができる。そのため、トランジスタがノーマリオン特性となることを抑制することができ、半導体装置の電気特性および信頼性を向上させることができる。
ゲート絶縁層408の電子スピン共鳴法によって計測される信号において、g値が2.001(2.00以上2.01以下)の信号に対応するスピン密度は2×1018spins/cm3以上、好ましくは2×1019spins/cm3以上であるとよい。また、g値が2.001の信号に対応する単位面積当たりのスピン密度が2×1012spins/cm2以上、好ましくは2×1013spins/cm2以上であるとよい。g値が2.001の信号に対応するスピン密度はゲート絶縁層408中に含まれるダングリングボンドに対応する。ただし、絶縁層の組成、種類によって、g値は異なるため、ここで検出されるg値には例えば、プラスマイナス5%程度ずれて信号が現れてもよく、ここでは2.00以上2.01以下程度の値であればよい。当該ダングリングボンドを多く含むゲート絶縁層408は、加熱処理などによる酸素の放出量が多い。従って、ダングリングボンドを多く含有しているゲート絶縁層408を酸化物半導体層404b上に設けることで、ゲート絶縁層408から放出される酸素によって、酸化物半導体層404b中の酸素欠損を補填し、電気特性の安定したトランジスタとすることができる。
次に、トランジスタ420の作製方法について説明する。
まず、基板400上に下地絶縁層402を形成する。使用できる基板に大きな制限はないが、少なくとも後の熱処理に耐えうる程度の耐熱性を有していることが必要となる。例えばバリウムホウケイ酸ガラスやアルミノホウケイ酸ガラスなどのガラス基板、セラミック基板、石英基板、サファイア基板などを用いることができる。
次に、下地絶縁層402上に酸化物層404a、酸化物半導体層404b、および酸化物層404cが積層された酸化物積層404を形成する(図3(A)参照)。酸化物層404a、酸化物半導体層404b、および酸化物層404cに適用可能な酸化物層は少なくともインジウム(In)または亜鉛(Zn)を含むことが好ましい。または、InとZnの双方を含むことが好ましい。また、該酸化物層を用いたトランジスタの電気特性のばらつきを減らすため、それらと共に、スタビライザーの一または複数を有することが好ましい。
次に、ソース電極層406aおよびドレイン電極層406bとなる導電層を成膜し、一部をエッチングすることでソース電極層406aおよびドレイン電極層406bを形成する(図3(B)参照)。
次に、ソース電極層406aおよびドレイン電極層406b上にゲート絶縁層408を形成する(図3(C)参照)。ゲート絶縁層408としては、酸化アルミニウム、酸化マグネシウム、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジム、酸化ハフニウムおよび酸化タンタルを一種以上含む絶縁層を、単層で、または積層で用いればよい。
次に、ゲート絶縁層408上にゲート電極層410となる導電層を形成し、該導電層をエッチングすることで、ゲート電極層410を形成する(図3(D)参照)。ゲート電極層410としては、アルミニウム、チタン、クロム、コバルト、ニッケル、銅、イットリウム、ジルコニウム、モリブデン、ルテニウム、銀、タンタルおよびタングステンを一種以上含む導電層を、単層で、または積層で用いればよい。
次に、ゲート絶縁層408およびゲート電極層410上に層間絶縁層412および層間絶縁層414を形成する(図4(A)参照)。層間絶縁層412および層間絶縁層414としては、酸化アルミニウム、酸化マグネシウム、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジム、酸化ハフニウムおよび酸化タンタルを一種以上含む絶縁層を、単層で、または積層で用いればよい。ここでは、層間絶縁層412および層間絶縁層414を積層して形成する例を図示した。
半導体装置の一例として、上記のトランジスタを用いることのできる論理回路であるNOR型回路の回路図の一例を図6(A)に示す。図6(B)はNAND型回路の回路図である。
上記のような半導体装置を、スマートフォン、電子書籍などの電子機器に応用した場合の例を図9乃至図12を用いて説明する。
251 メモリセルアレイ
251a メモリセルアレイ
251b メモリセルアレイ
253 周辺回路
254 容量素子
260 トランジスタ
262 トランジスタ
264 容量素子
302 素子分離絶縁層
306a ソース領域
306b ドレイン領域
308 ゲート絶縁層
300 トランジスタ
310 ゲート電極層
316a ソース電極層
316b ドレイン電極層
320 トランジスタ
322 導電層
324 導電層
326 導電層
328 絶縁層
330 絶縁層
332 絶縁層
340 トランジスタ
400 基板
402 下地絶縁層
404 酸化物積層
404a 酸化物層
404b 酸化物半導体層
404c 酸化物層
405a ソース領域
405b ドレイン領域
406a ソース電極層
406b ドレイン電極層
408 ゲート絶縁層
410 ゲート電極層
412 層間絶縁層
414 層間絶縁層
416a ソース配線層
416b ドレイン配線層
418a ソース電極層
418b ドレイン電極層
419a ソース電極層
419b ドレイン電極層
420 トランジスタ
430 トランジスタ
440 トランジスタ
450 トランジスタ
801 トランジスタ
802 トランジスタ
803 トランジスタ
804 トランジスタ
812 トランジスタ
813 トランジスタ
901 RF回路
902 アナログベースバンド回路
903 デジタルベースバンド回路
904 バッテリー
905 電源回路
906 アプリケーションプロセッサ
907 CPU
908 DSP
910 フラッシュメモリ
911 ディスプレイコントローラ
912 メモリ回路
913 ディスプレイ
914 表示部
915 ソースドライバ
916 ゲートドライバ
917 音声回路
918 キーボード
919 タッチセンサ
950 メモリ回路
951 メモリコントローラ
952 メモリ
953 メモリ
954 スイッチ
955 スイッチ
956 ディスプレイコントローラ
957 ディスプレイ
1001 バッテリー
1002 電源回路
1003 マイクロプロセッサ
1004 フラッシュメモリ
1005 音声回路
1006 キーボード
1007 メモリ回路
1008 タッチパネル
1009 ディスプレイ
1010 ディスプレイコントローラ
9033 留め具
9034 スイッチ
9035 電源スイッチ
9036 スイッチ
9038 操作スイッチ
9630 筐体
9631a 表示部
9631b 表示部
9632a 領域
9632b 領域
9633 太陽電池
9634 充放電制御回路
9635 バッテリー
9636 DCDCコンバータ
9638 操作キー
9639 ボタン
Claims (9)
- 酸化物層と、前記酸化物層上の前記酸化物層よりも電子親和力が0.1eV以上大きい酸化物半導体層と、を含む酸化物積層と、
前記酸化物積層と接して設けられたゲート絶縁層と、
前記ゲート絶縁層を介して、前記酸化物積層と重なって設けられたゲート電極層と、を有し、
電子スピン共鳴法によって、g値が1.90以上1.95以下の信号に対応するスピン密度が1.5×1012spins/cm2以下であり、g値が2.00以上2.01以下の信号に対応するスピン密度が2×1012spins/cm2以上である半導体装置。 - 下地絶縁層と、
前記下地絶縁層上の酸化物層と、前記酸化物層上の前記酸化物層よりも電子親和力が0.1eV以上大きい酸化物半導体層と、を含む酸化物積層と、
前記酸化物積層と接するソース電極層およびドレイン電極層と、
前記ソース電極層および前記ドレイン電極層上のゲート絶縁層と、
前記ゲート絶縁層上のゲート電極層と、
前記ゲート電極層上の層間絶縁層と、を有し、
前記酸化物半導体層は、電子スピン共鳴法によって計測される信号において、g値が1.90以上1.95以下の信号に対応するスピン密度が1.5×1018spins/cm3以下であり、
前記ゲート絶縁層は、電子スピン共鳴法によって計測される信号において、g値が2.00以上2.01以下の信号に対応するスピン密度が2×1018spins/cm3以上である半導体装置。 - 請求項1または請求項2において、
前記酸化物半導体層および前記酸化物層は、少なくともインジウムを含み、前記酸化物半導体層中のインジウムの含有割合は、前記酸化物層のインジウムの含有割合よりも高い半導体装置。 - 請求項1乃至請求項3のいずれか一において、
前記酸化物半導体層および前記酸化物層は、少なくともインジウム、亜鉛、およびガリウムを含有する半導体装置。 - 請求項1乃至請求項4のいずれか一項において、
前記酸化物半導体層は、上面と略垂直な方向にc軸が配向した結晶を有する半導体装置。 - 請求項1乃至請求項5のいずれか一項において、前記酸化物半導体層に含まれるシリコンの濃度は2×1018atoms/cm3未満である半導体装置。
- 下地絶縁層を形成し、
前記下地絶縁層上に酸化物半導体層を含む酸化物積層を形成し、
前記酸化物積層上にソース電極層およびドレイン電極層を形成し、
前記ソース電極層および前記ドレイン電極層上にゲート絶縁層を形成し、
前記ゲート絶縁層上にゲート電極層を形成し、
前記ゲート電極層上に層間絶縁層を形成し、
前記層間絶縁層の形成後に300℃以上450℃未満の加熱処理を行い、
前記ゲート絶縁層は、処理室内の圧力を100Pa以上300Pa以下とするプラズマCVD法を用いて成膜する半導体装置の作製方法。 - 請求項7において、
前記酸化物積層の形成後に、加熱処理を行う、半導体装置の作製方法。 - 請求項7または請求項8において、
前記下地絶縁層にイオンインプランテーション法によって、酸素を注入する半導体装置の作製方法。
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JP6712338B2 (ja) | 2020-06-17 |
US20160111546A1 (en) | 2016-04-21 |
JP2019110314A (ja) | 2019-07-04 |
KR102219628B1 (ko) | 2021-02-23 |
US9166021B2 (en) | 2015-10-20 |
JP6482694B2 (ja) | 2019-03-13 |
KR20140049934A (ko) | 2014-04-28 |
US20140106502A1 (en) | 2014-04-17 |
US9660098B2 (en) | 2017-05-23 |
JP2018078344A (ja) | 2018-05-17 |
JP6290577B2 (ja) | 2018-03-07 |
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