JP2013201167A - 電力用半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 169
- 239000000758 substrate Substances 0.000 claims abstract description 99
- 239000012535 impurity Substances 0.000 claims description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000009413 insulation Methods 0.000 abstract description 3
- 230000005684 electric field Effects 0.000 description 38
- 108091006146 Channels Proteins 0.000 description 12
- 230000002093 peripheral effect Effects 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 7
- 230000004048 modification Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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Abstract
【解決手段】半導体装置10は、p型のベース層、ソース電極12を有する素子部および終端部からなり、n型の半導体基板11、pピラー層18、第1のトレンチ41、および第1の絶縁膜23を具備する。pピラー層18は、半導体基板11のうち、ソース電極12の下およびソース電極12から露出する終端部の半導体基板11に、所定の間隔で配列される。pピラー層18のそれぞれは、半導体基板11の上面またはベース層の下面に接する上面18aを有し、上面18aから深さ方向に形成された平面状のものである。第1のトレンチ41は、pピラー層18の一端面18bを含む一端部の間、およびpピラー層18の他端面18cを含む他端部の間、の終端部の半導体基板11に設けられる。第1の絶縁膜23は、第1のトレンチ41の側面および底面に設けられる。
【選択図】図1
Description
11、11´・・・半導体基板
11a・・・半導体層
12・・・ソース電極
13・・・MOSFET素子
14・・・ゲートパッド
15・・・ゲート電極
15a・・・ゲート絶縁膜
16・・・フィールドプレート電極パッド
17・・・EQPR電極パッド
18、18´・・・pピラー層
18a、18a´・・・pピラー層の上面
18b、18b´・・・pピラー層の一端面
18c、18c´・・・pピラー層の他端面
18d、18d´・・・pピラー層の側面
19・・・nピラー層
22・・・電界緩和層
23・・・第1の絶縁膜
24・・・電界緩和層
25・・・第2の絶縁膜
26・・・素子部
27・・・終端部
28・・・ベース層
29・・・コンタクト層
30・・・ベース層
31・・・コンタクト層
32・・・ソース層
33・・・高濃度半導体基板
34、34´・・・ドレイン電極
35・・・フィールド酸化膜
36、36´・・・フィールドプレート電極
37・・・チャネルストップ層
37−1・・・p型のチャネルストップ層
37−2・・・n型のチャネルストップ層
38、38´・・・EQPR電極
39・・・第3の絶縁膜
40・・・トレンチ
41・・・第1のトレンチ
42・・・第2のトレンチ
Claims (8)
- 電力用半導体素子が設けられた素子部、および前記素子部の周囲に設けられた終端部、からなる電力用半導体装置であって、
第1導電型の半導体基板と、
前記半導体基板の上面のうち、前記素子部の一部に設けられた第2導電型の第1の不純物層と、
前記第1の不純物層にゲート絶縁膜を介して接するように設けられたゲート電極と、
前記第1の不純物層の上面の一部に設けられた第1導電型の第2の不純物層と、
前記半導体基板の下面に設けられた第1の電極と、
前記半導体基板の前記上面に、少なくとも前記第2の不純物層に接するように設けられた第2の電極と、
それぞれが、前記半導体基板の上面から露出する帯状の上面または前記ベース層の下面に接する帯状の上面、前記上面を構成する短辺の一方を含み、前記上面に対して垂直な平面である一端面、前記上面を構成する短辺の他方を含み、前記上面に対して垂直な平面である他端面、および前記上面を構成する長辺のいずれか一方を含み、前記上面に対して垂直な平面である側面、を有し、前記上面から前記半導体基板の深さ方向に埋め込まれるように設けられた平面状であって、前記第2の電極の下および前記第2の電極から露出する前記終端部において、前記上面が所定の間隔でストライプ状に配列されるように設けられた複数の第2導電型のピラー層と、
前記終端部の前記半導体基板の上面に、前記複数の第2導電型のピラー層の前記上面を囲うように設けられた、前記半導体基板より高濃度である前記第1導電型の前記第3の不純物層第と、
前記第3の不純物層上に設けられた、ポリシリコンからなるEQPR電極と、
前記第2の電極から露出する前記終端部の前記半導体基板であって、前記ピラー層の前記一端面を含む一端部の間の前記半導体基板、および前記ピラー層の前記他端面を含む他端部の間の前記半導体基板、にそれぞれ設けられた複数の第1のトレンチと、
それぞれの前記第1のトレンチの側面および底面に設けられた第1の絶縁膜と、
それぞれの前記第1のトレンチの内部に設けられ、前記EQPR電極に電気的に接続された第1のポリシリコンと、
前記第2の電極から露出する前記終端部の前記半導体基板に、前記ピラー層の側面に沿って設けられた第2のトレンチと、
前記第2のトレンチの側面および底面に設けられた第2の絶縁膜と、
前記第2のトレンチの内部に設けられ、前記EQPR電極に電気的に接続された第2のポリシリコンと、
を具備することを特徴とする電力用半導体装置。 - 電力用半導体素子が設けられた素子部、および前記素子部の周囲に設けられた終端部、からなる電力用半導体装置であって、
第1導電型の半導体基板と、
前記半導体基板の上面のうち、前記素子部の一部に設けられた第2導電型の第1の不純物層と、
前記第1の不純物層の上面の一部に設けられた第1導電型の第2の不純物層と、
前記ベース層にゲート絶縁膜を介して接するように設けられたゲート電極と、
前記半導体基板の下面に設けられた第1の電極と、
前記半導体基板の前記上面に、少なくとも前記第1の不純物層に接するように設けられた第2の電極と、
それぞれが、前記半導体基板の上面から露出する帯状の上面または前記ベース層の下面に接する帯状の上面、前記上面を構成する短辺の一方を含み、前記上面に対して垂直な平面である一端面、前記上面を構成する短辺の他方を含み、前記上面に対して垂直な平面である他端面、および前記上面を構成する長辺のいずれか一方を含み、前記上面に対して垂直な平面である側面、を有し、前記上面から前記半導体基板の深さ方向に埋め込まれるように設けられた平面状であって、前記第2の電極の下および前記第2の電極から露出する前記終端部において、前記上面が所定の間隔でストライプ状に配列されるように設けられた複数の第2導電型のピラー層と、
前記第2の電極から露出する前記終端部の前記半導体基板であって、前記ピラー層の前記一端面を含む一端部の間の前記半導体基板、および前記ピラー層の前記他端面を含む他端部の間の前記半導体基板、にそれぞれ設けられた複数の第1のトレンチと、
それぞれの前記第1のトレンチの側面および底面に設けられた第1の絶縁膜と、
を具備することを特徴とする電力用半導体装置。 - 前記半導体基板の上面に、前記複数の第2導電型のピラー層の前記上面を囲うように設けられた、前記半導体基板より高濃度である前記第1導電型の前記第3の不純物層と、
前記第3の不純物層上に設けられたEQPR電極と、
前記第1の絶縁膜が設けられた第1のトレンチの内部に設けられ、前記EQPR電極に電気的に接続された第1のフローティング電極と、
をさらに具備することを特徴とする請求項2に記載の電力用半導体装置。 - 前記EQPR電極および前記第1のフローティング電極はそれぞれ、ポリシリコンからなることを特徴とする請求項3に記載の電力用半導体装置。
- 前記第2の電極から露出する前記終端部の前記半導体基板に、前記ピラー層の側面に沿って設けられた第2のトレンチと、
前記第2のトレンチの側面および底面に設けられた第2の絶縁膜と、
をさらに具備することを特徴とする請求項2乃至4のいずれかに記載の電力用半導体装置。 - 前記第2のトレンチは、最も外側の前記ピラー層のさらに外側の前記半導体基板に、前記ピラー層の側面に沿って設けられたことを特徴とする請求項5に記載の電力用半導体装置。
- 前記半導体基板の上面に、前記複数の第2導電型のピラー層の前記上面を囲うように設けられた、前記半導体基板より高濃度である前記第1導電型の前記第3の不純物層と、
前記第3の不純物層上に設けられたEQPR電極と、
前記第2の絶縁膜が設けられた第2のトレンチの内部に設けられ、前記EQPR電極に電気的に接続された第2のフローティング電極と、
をさらに具備することを特徴とする請求項5または6に記載の電力用半導体装置。 - 前記EQPR電極および前記第2のフローティング電極はそれぞれ、ポリシリコンからなることを特徴とする請求項7に記載の電力用半導体装置。
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CN2012103186164A CN103325774A (zh) | 2012-03-23 | 2012-08-31 | 电力用半导体装置 |
US13/610,532 US8716789B2 (en) | 2012-03-23 | 2012-09-11 | Power semiconductor device |
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JP2012074441A (ja) * | 2010-09-28 | 2012-04-12 | Toshiba Corp | 電力用半導体装置 |
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JP5701802B2 (ja) * | 2012-03-23 | 2015-04-15 | 株式会社東芝 | 電力用半導体装置 |
US9842911B2 (en) | 2012-05-30 | 2017-12-12 | Vishay-Siliconix | Adaptive charge balanced edge termination |
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JP6185440B2 (ja) * | 2014-09-16 | 2017-08-23 | 株式会社東芝 | 半導体装置 |
JP2016171279A (ja) * | 2015-03-16 | 2016-09-23 | 株式会社東芝 | 半導体装置 |
TWI652791B (zh) * | 2015-03-27 | 2019-03-01 | 力智電子股份有限公司 | 半導體裝置 |
TWI737889B (zh) * | 2018-02-05 | 2021-09-01 | 力智電子股份有限公司 | 功率半導體元件 |
US11302785B2 (en) * | 2019-06-18 | 2022-04-12 | Texas Instruments Incorporated | Method for testing a high voltage transistor with a field plate |
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