JP2013197589A - 電界効果トランジスタの製造方法 - Google Patents
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- 230000005669 field effect Effects 0.000 title claims abstract description 71
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 65
- 238000005530 etching Methods 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 239000004065 semiconductor Substances 0.000 claims abstract description 59
- 238000000034 method Methods 0.000 claims description 67
- 238000002955 isolation Methods 0.000 claims description 36
- 230000003247 decreasing effect Effects 0.000 claims description 10
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 230000002265 prevention Effects 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 29
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000004943 liquid phase epitaxy Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 238000000927 vapour-phase epitaxy Methods 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- 229910005542 GaSb Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Abstract
【解決手段】 第1領域RG1及び第2領域RG2を含む基板100上に第1マスクパターン及び第2マスク層を形成した後、第1マスクパターンを露出する第2マスクパターンをエッチングマスクとして基板100をエッチングし第1フィン部F1を形成する。第2領域RG2を覆い第1領域RG1を露出するエピタキシャル防止マスクパターンを形成した後、第1領域RG1上に第1半導体層SP1を形成し第1領域RG1上に第1フィン部F1より幅が広い第2フィン部F2を形成する。第2マスクパターン及びエピタキシャル防止マスクパターンなどを除去した後、第1フィン部F1及び第2フィン部F2上にゲート誘電パターン141及びゲート電極パターン143を形成する。これにより、第1フィン部F1及び第2フィン部F2は、互いに異なる幅を有することができる。
【選択図】 図11
Description
図1乃至図12に基づいて本発明の第1実施形態による電界効果トランジスタの製造方法を説明する。図1、図3、図5、図7、図9、及び図11は、第1実施形態による電界効果トランジスタの製造方法を説明するための斜視図であり、図2、図4、図6、図8、図10、及び図12は、各々図1、図3、図5、図7、図9、及び図11のA−A’線断面図である。
図13乃至図20を参照して、本発明の第2実施形態による電界効果トランジスタの製造方法が説明される。図13、図15、図17、及び図19は、本発明の第2実施形態による電界効果トランジスタの製造方法を説明するための斜視図であり、図14、図16、図18、及び図20は各々図13、図15、図17、及び図19のA−A’線断面図である。説明を簡単にするために第1実施形態と重複する構成の説明は省略され得る。
図21乃至図24を参照して、本発明の第3実施形態による電界効果トランジスタの製造方法を説明する。図21及び図23は本発明の第3実施形態による電界効果トランジスタの製造方法を説明するための斜視図であり、図22及び図24は各々図21及び図23のA−A’線断面図である。説明を簡単にするために第1実施形態又は第2実施形態と重複する構成の説明は省略され得る。
図25乃至図28を参照して、本発明の第4実施形態による電界効果トランジスタの製造方法を説明する。図25及び図27は本発明の第4実施形態による電界効果トランジスタの製造方法を説明するための斜視図であり、図26及び図28は各々図25及び図27のA−A’線断面図である。説明を簡単にするために第1実施形態から第3実施形態と重複する構成の説明は省略され得る。
図29乃至図42を参照して、本発明の第5実施形態による電界効果トランジスタの製造方法が説明される。図29、図31、図33、図35、図37、図39、及び図41は本発明の第5実施形態による電界効果トランジスタの製造方法を説明するための斜視図であり、図30、図32、図34、図36、図38、図40及び図42は、各々図29、図31、図33、図35、図37、図39、及び図41のA−A’線断面図である。説明を簡単にするために第1実施形態から第4実施形態と重複する構成の説明は省略され得る。
110 ・・・素子分離膜、
F1、F2 ・・・フィン部、
SP1、SP2・・・半導体層、
141 ・・・ゲート誘電パターン、
143 ・・・ゲート電極パターン。
Claims (10)
- 第1領域及び第2領域を含む基板を準備する段階と、
前記基板から突出し第1幅を有するフィン部を前記第1領域上及び前記第2領域上に形成する段階と、
前記第1領域上の前記フィン部を露出しつつ前記第2領域上の前記フィン部を覆う第1マスクパターンを形成する段階と、
前記第1領域上の前記フィン部の幅を増加又は減少させる段階と、
を含む電界効果トランジスタの製造方法。 - 前記フィン部の幅を増加又は減少させる段階は、前記フィン部から半導体層を成長させる段階を含むことを特徴とする請求項1に記載の電界効果トランジスタの製造方法。
- 前記フィン部の下部側壁上に素子分離膜を形成する段階をさらに含み、
前記半導体層は、前記素子分離膜を形成する前に形成されることを特徴とする請求項2に記載の電界効果トランジスタの製造方法。 - 前記フィン部を形成する段階は、
前記基板上に第2マスクパターンを形成する段階と、
前記第2マスクパターンをエッチングマスクとして前記基板をエッチングする段階と、
を含み、
前記半導体層は、前記第1マスクパターン及び前記第2マスクパターンによって露出された前記フィン部の側壁及び前記基板上に形成されることを特徴とする請求項3に記載の電界効果トランジスタの製造方法。 - 前記フィン部の下部側壁上に素子分離膜を形成する段階をさらに含み、
前記第1マスクパターン及び前記半導体層は、前記素子分離膜を形成した後に形成されることを特徴とする請求項2に記載の電界効果トランジスタの製造方法。 - 前記フィン部の幅を増加又は減少させる段階は、前記第1領域上の前記フィン部をエッチングする段階を含むことを特徴とする請求項1に記載の電界効果トランジスタの製造方法。
- 前記フィン部の下部側壁上に素子分離膜を形成する段階をさらに含み、
前記素子分離膜は、前記フィン部をエッチングした後に形成されることを特徴とする請求項6に記載の電界効果トランジスタの製造方法。 - 前記フィン部を形成する段階は、
前記基板上に第2マスクパターンを形成する段階と、
前記第2マスクパターンをエッチングマスクとして前記基板をエッチングする段階と、
を含み、
前記フィン部をエッチングする段階は、前記第1マスクパターン及び前記第2マスクパターンによって露出された前記フィン部の側壁及び前記基板の上面をエッチングする段階を含むことを特徴とする請求項7に記載の電界効果トランジスタの製造方法。 - 前記フィン部の下部側壁上に素子分離膜を形成する段階をさらに含み、
前記素子分離膜は、前記フィン部をエッチングする前に形成され、
前記フィン部をエッチングする段階は、前記第1マスクパターン及び前記素子分離膜によって露出された前記フィン部の上面及び上部側壁をエッチングする段階を含むことを特徴とする請求項6に記載の電界効果トランジスタの製造方法。 - 前記フィン部を形成する段階は、
前記基板上に第2マスクパターンを形成する段階と、
前記第2マスクパターンをエッチングマスクとして前記基板をエッチングする段階と、
を含み、
前記第2マスクパターンを形成する段階は、
前記基板上に第3マスクパターンを形成する段階と、
前記第3マスクパターンの側壁上にスペーサー工程を遂行する段階と、
前記第3マスクパターンを除去する段階と、
を含むことを特徴とする請求項1に記載の電界効果トランジスタの製造方法。
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Also Published As
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US8987100B2 (en) | 2015-03-24 |
US20150162437A1 (en) | 2015-06-11 |
CN106252417A (zh) | 2016-12-21 |
TWI566279B (zh) | 2017-01-11 |
US9287402B2 (en) | 2016-03-15 |
JP6211275B2 (ja) | 2017-10-11 |
CN103325736A (zh) | 2013-09-25 |
US20160155804A1 (en) | 2016-06-02 |
KR101823105B1 (ko) | 2018-01-30 |
KR20130106091A (ko) | 2013-09-27 |
US9443935B2 (en) | 2016-09-13 |
US20130244392A1 (en) | 2013-09-19 |
CN103325736B (zh) | 2018-01-02 |
TW201340186A (zh) | 2013-10-01 |
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