JP2012204733A - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP2012204733A JP2012204733A JP2011069606A JP2011069606A JP2012204733A JP 2012204733 A JP2012204733 A JP 2012204733A JP 2011069606 A JP2011069606 A JP 2011069606A JP 2011069606 A JP2011069606 A JP 2011069606A JP 2012204733 A JP2012204733 A JP 2012204733A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- row
- element connection
- wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Abstract
【解決手段】外周側から1番目の列L1〜3番目の列L3を有して格子状に配列形成された半導体素子接続パッド5と、2番目の列L2および3番目の列L3の半導体素子接続パッド5から1番目の列L1の半導体素子接続パッド5の間を通って外側へ延びる引出配線4aと、半導体素子接続パッド5を引出配線4aの一部とともに1番目の列L1〜3番目の列L3毎に露出させるスリット状の開口部7aを有するソルダーレジスト層7とを備えて成る配線基板10であって、引出配線4aは、半導体素子接続パッド5とともに開口部7a内に露出する部位が1番目の列L1と2番目の列L2と3番目の列L3とで全て同じ方向に延びている。
【選択図】図2
Description
4a 引出配線
5 半導体素子接続パッド
7 ソルダーレジスト層
7a 開口部
10a 搭載部
L1 搭載部10aの外周側から1番目の半導体素子接続パッド5の列
L2 搭載部10aの外周側から2番目の半導体素子接続パッド5の列
L3 搭載部10aの外周側から3番目の半導体素子接続パッド5の列
S 半導体素子
Claims (1)
- 上面中央部に半導体素子が搭載される搭載部を有する絶縁基板と、前記搭載部に外周側から1番目の列および2番目の列および3番目の列を有して格子状に配列形成された半導体素子接続パッドと、前記2番目の列および3番目の列の半導体素子接続パッドから前記1番目の列の半導体素子接続パッドの間を通って前記絶縁基板の上面を前記搭載部の外側へ延びる引出配線と、前記絶縁基板の上面に被着されており、前記半導体素子接続パッドを該半導体素子接続パッドから延びる前記引出配線の一部とともに前記1番目の列と2番目の列と3番目の列毎に露出させるスリット状の開口部を有するソルダーレジスト層とを備えて成る配線基板であって、前記引出配線は、前記半導体素子接続パッドとともに前記開口部内に露出する部位が前記1番目の列と2番目の列と3番目の列とで全て同じ方向に延びていることを特徴とする配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011069606A JP5709309B2 (ja) | 2011-03-28 | 2011-03-28 | 配線基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011069606A JP5709309B2 (ja) | 2011-03-28 | 2011-03-28 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012204733A true JP2012204733A (ja) | 2012-10-22 |
JP5709309B2 JP5709309B2 (ja) | 2015-04-30 |
Family
ID=47185334
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011069606A Expired - Fee Related JP5709309B2 (ja) | 2011-03-28 | 2011-03-28 | 配線基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5709309B2 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104009012A (zh) * | 2013-02-22 | 2014-08-27 | 瑞萨电子株式会社 | 半导体芯片和半导体器件 |
KR20170061081A (ko) * | 2015-11-25 | 2017-06-02 | 가부시키가이샤 재팬 디스프레이 | 검출 장치 및 표시 장치 |
WO2021199475A1 (ja) * | 2020-03-31 | 2021-10-07 | 株式会社村田製作所 | モジュール基板、高周波モジュール及び通信装置 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1013026A (ja) * | 1996-06-19 | 1998-01-16 | Ibiden Co Ltd | 多層プリント配線板 |
JP2009010073A (ja) * | 2007-06-27 | 2009-01-15 | Shinko Electric Ind Co Ltd | 半導体パッケージおよびこれを用いた半導体装置 |
-
2011
- 2011-03-28 JP JP2011069606A patent/JP5709309B2/ja not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1013026A (ja) * | 1996-06-19 | 1998-01-16 | Ibiden Co Ltd | 多層プリント配線板 |
JP2009010073A (ja) * | 2007-06-27 | 2009-01-15 | Shinko Electric Ind Co Ltd | 半導体パッケージおよびこれを用いた半導体装置 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104009012A (zh) * | 2013-02-22 | 2014-08-27 | 瑞萨电子株式会社 | 半导体芯片和半导体器件 |
JP2014187343A (ja) * | 2013-02-22 | 2014-10-02 | Renesas Electronics Corp | 半導体チップ及び半導体装置 |
KR20170061081A (ko) * | 2015-11-25 | 2017-06-02 | 가부시키가이샤 재팬 디스프레이 | 검출 장치 및 표시 장치 |
KR101873119B1 (ko) | 2015-11-25 | 2018-06-29 | 가부시키가이샤 재팬 디스프레이 | 검출 장치 및 표시 장치 |
WO2021199475A1 (ja) * | 2020-03-31 | 2021-10-07 | 株式会社村田製作所 | モジュール基板、高周波モジュール及び通信装置 |
Also Published As
Publication number | Publication date |
---|---|
JP5709309B2 (ja) | 2015-04-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6013960B2 (ja) | 配線基板 | |
JP6272173B2 (ja) | 配線基板 | |
CN106024723A (zh) | 布线基板 | |
JP5709309B2 (ja) | 配線基板 | |
JP2018082084A (ja) | プリント配線板およびプリント配線板の製造方法 | |
JP7247046B2 (ja) | 配線基板及び配線基板の製造方法 | |
JP2010232616A (ja) | 半導体装置及び配線基板 | |
JP2017152448A (ja) | 多数個取り配線基板 | |
JP2016127134A (ja) | 配線基板 | |
US20150027977A1 (en) | Method of manufacturing wiring board | |
JP6215784B2 (ja) | 配線基板 | |
JP2016051747A (ja) | 配線基板 | |
JP5835725B2 (ja) | 配線基板 | |
JP6626687B2 (ja) | 配線基板、半導体装置及び配線基板の製造方法 | |
JP5808055B2 (ja) | 配線基板 | |
JP5586328B2 (ja) | 配線基板 | |
JP6466722B2 (ja) | 配線基板 | |
JP2013175518A (ja) | 配線基板 | |
JP6259045B2 (ja) | 配線基板の製造方法 | |
JP5959562B2 (ja) | 配線基板 | |
JP2018032652A (ja) | 配線基板およびこれを用いた半導体素子の実装構造 | |
JP6470095B2 (ja) | 配線基板 | |
JP6165436B2 (ja) | 多層基板、および多層基板の設計方法 | |
JP2014192363A (ja) | 配線基板およびその製造方法 | |
JP2018032802A (ja) | 配線基板およびこれを用いた半導体素子の実装構造 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20131105 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20140807 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140922 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20141112 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20150302 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20150302 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5709309 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |