JP2011243897A - 多層プリント基板及びその製造方法 - Google Patents
多層プリント基板及びその製造方法 Download PDFInfo
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Abstract
【解決手段】端部が自由端であるフレキシブル配線層14bを含む半導体パッケージ1が内蔵され、フレキシブル配線層14bがプリント基板の内層配線層24cと電気的に接続される多層プリント基板2を提供する。
【選択図】図2
Description
図1は、第1の実施の形態に係る半導体装置(半導体パッケージ)1の断面図である。図1に示すように、半導体パッケージ1は、半導体チップ11、リジッド配線層12、端子13及びフレキシブル配線層14を有する。本実施の形態において、リジッド配線層12およびフレキシブル配線層14は、後述するリジッド・フレックス基板を構成する。なお、本実施の形態において、半導体チップ11はリジッド配線層12上に接続される。必要に応じて半導体チップは半導体チップ単体でも、半導体チップを封止樹脂で封止した構造を採用してもよい。パッケージングの形態としては、例えば、BGA(Ball Grid Array)、CSP(Chip Size Package)等が挙げられる。ここで、リジッド配線層12を構成する絶縁層および/または導体層とフレキシブル配線層14を構成する絶縁層および導体層が互いに積層され、リジッド・フレックス基板を成す。以下に、各構成について説明する。
(付記1)
内層配線層を備える多層プリント基板であって、端部が自由端であるフレキシブル配線層を含む半導体パッケージが内蔵され、前記フレキシブル配線層が前記内層配線層と電気的に接続される多層プリント基板。
(付記2)
前記フレキシブル配線層は、前記半導体パッケージの内蔵領域よりも外側に延在された状態で前記内層配線層と電気的に接続される付記1に記載のプリント基板。
(付記3)
前記フレキシブル配線層の一部は、前記半導体パッケージの表面に密着されており、貫通ビアを介して前記内層配線層と接続される付記1に記載のプリント基板。
(付記4)
前記フレキシブル配線層の一部は、封止材を介して前記半導体パッケージの表面に配置されており、前記内層配線層と直接接続される付記1に記載のプリント基板。
(付記5)
前記フレキシブル配線層の一部は、前記半導体パッケージの内蔵領域よりも外側に設けられる端子パッドに導電材にて接続される付記1に記載のプリント基板。
(付記6)
内層配線層を有する多層プリント基板の製造方法であって、
表面に導電パッドが形成される内層基板上に、端部が自由端であるフレキシブル配線層を含む半導体パッケージを前記導電パッドに位置合わせして搭載する工程と、
前記半導体パッケージの周囲に絶縁層を設ける工程と、
前記フレキシブル配線層を前記絶縁層上に形成される内層配線層と電気的に接続する工程と、を備えることを特徴とする多層プリント基板の製造方法。
(付記7)
前記フレキシブル配線層の一部を、前記半導体パッケージの表面に密着して配置し、
貫通ビアを介して前記内層配線層と接続する、付記6に記載の多層プリント基板の製造方法。
(付記8)
前記フレキシブル配線層の一部を、封止材を介して前記半導体パッケージの表面に配置する、付記6に記載の多層プリント基板の製造方法。
(付記9)
前記フレキシブル配線層の一部を、前記半導体パッケージの内蔵領域よりも外側に設けられる端子パッドに導電材にて接続する、付記6に記載の多層プリント基板の製造方法。
Claims (6)
- 内層配線層を備える多層プリント基板であって、
端部が自由端であるフレキシブル配線層を含む半導体パッケージが内蔵され、
前記フレキシブル配線層が前記内層配線層と電気的に接続されることを特徴とする多層プリント基板。 - 前記フレキシブル配線層は、前記半導体パッケージの内蔵領域よりも外側に延在された状態で前記内層配線層と電気的に接続されることを特徴とする請求項1に記載のプリント基板。
- 前記フレキシブル配線層の一部は、前記半導体パッケージの表面に密着されており、貫通ビアを介して前記内層配線層と接続されることを特徴とする請求項1に記載のプリント基板。
- 前記フレキシブル配線層の一部は、封止材を介して前記半導体パッケージの表面に配置されており、前記内層配線層と直接接続されることを特徴とする請求項1に記載のプリント基板。
- 前記フレキシブル配線層の一部は、前記半導体パッケージの内蔵領域よりも外側に設けられる端子パッドに導電材にて接続されることを特徴とする請求項1に記載のプリント基板。
- 内層配線層を有する多層プリント基板の製造方法であって、
表面に導電パッドが形成される内層基板上に、端部が自由端であるフレキシブル配線層を含む半導体パッケージを前記導電パッドに位置合わせして搭載する工程と、
前記半導体パッケージの周囲に絶縁層を設ける工程と、
前記フレキシブル配線層を前記絶縁層上に形成される内層配線層と電気的に接続する工程と、を備えることを特徴とする多層プリント基板の製造方法。
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JP2010117011A JP2011243897A (ja) | 2010-05-21 | 2010-05-21 | 多層プリント基板及びその製造方法 |
TW100108533A TW201206267A (en) | 2010-05-21 | 2011-03-14 | Multilayer printed circuit board using flexible interconnect structure, and method of making same |
EP11158346A EP2389049B1 (en) | 2010-05-21 | 2011-03-15 | Multilayer printed circuit board using flexible interconnect structure, and method of making same |
US13/048,056 US20110286188A1 (en) | 2010-05-21 | 2011-03-15 | Multilayer printed circuit board using flexible interconnect structure, and method of making same |
KR1020110028869A KR101139084B1 (ko) | 2010-05-21 | 2011-03-30 | 다층 프린트 기판 및 그 제조 방법 |
CN2011100804004A CN102256435A (zh) | 2010-05-21 | 2011-03-31 | 使用柔性互连结构的多层印制电路板及其制作方法 |
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CN104051405A (zh) * | 2013-03-11 | 2014-09-17 | 欣兴电子股份有限公司 | 嵌埋有电子组件的线路板结构及其制法 |
CN104640350B (zh) * | 2013-11-11 | 2018-04-20 | 日月光半导体制造股份有限公司 | 电路板模块 |
KR20170026676A (ko) | 2015-08-26 | 2017-03-09 | 에스케이하이닉스 주식회사 | 슬라이딩 상호 연결 배선 구조를 포함하는 플렉서블 소자 |
JP2018098487A (ja) * | 2016-12-14 | 2018-06-21 | 株式会社村田製作所 | 半導体モジュール |
US10410963B1 (en) | 2018-06-07 | 2019-09-10 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Deformed layer for short electric connection between structures of electric device |
JP7211267B2 (ja) | 2019-05-29 | 2023-01-24 | 株式会社デンソー | 半導体パッケージの製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0697225A (ja) * | 1992-09-11 | 1994-04-08 | Toshiba Corp | 半導体装置 |
JPH0969588A (ja) * | 1995-06-20 | 1997-03-11 | Shinko Electric Ind Co Ltd | 半導体装置 |
JP2008147228A (ja) * | 2006-12-06 | 2008-06-26 | Toppan Printing Co Ltd | 配線基板及びその製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5426263A (en) * | 1993-12-23 | 1995-06-20 | Motorola, Inc. | Electronic assembly having a double-sided leadless component |
US6940729B2 (en) * | 2001-10-26 | 2005-09-06 | Staktek Group L.P. | Integrated circuit stacking system and method |
US7141874B2 (en) * | 2003-05-14 | 2006-11-28 | Matsushita Electric Industrial Co., Ltd. | Electronic component packaging structure and method for producing the same |
JP4503349B2 (ja) | 2003-05-14 | 2010-07-14 | パナソニック株式会社 | 電子部品実装体及びその製造方法 |
JP2005039227A (ja) | 2003-07-03 | 2005-02-10 | Matsushita Electric Ind Co Ltd | 半導体内蔵モジュールとその製造方法 |
JP4536430B2 (ja) * | 2004-06-10 | 2010-09-01 | イビデン株式会社 | フレックスリジッド配線板 |
WO2006043388A1 (ja) * | 2004-10-21 | 2006-04-27 | Matsushita Electric Industrial Co., Ltd. | 半導体内蔵モジュール及びその製造方法 |
JP5168838B2 (ja) | 2006-07-28 | 2013-03-27 | 大日本印刷株式会社 | 多層プリント配線板及びその製造方法 |
US20100155109A1 (en) * | 2008-12-24 | 2010-06-24 | Ibiden Co., Ltd. | Flex-rigid wiring board and method for manufacturing the same |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0697225A (ja) * | 1992-09-11 | 1994-04-08 | Toshiba Corp | 半導体装置 |
JPH0969588A (ja) * | 1995-06-20 | 1997-03-11 | Shinko Electric Ind Co Ltd | 半導体装置 |
JP2008147228A (ja) * | 2006-12-06 | 2008-06-26 | Toppan Printing Co Ltd | 配線基板及びその製造方法 |
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KR20110128227A (ko) | 2011-11-29 |
EP2389049A1 (en) | 2011-11-23 |
CN102256435A (zh) | 2011-11-23 |
KR101139084B1 (ko) | 2012-06-01 |
US20110286188A1 (en) | 2011-11-24 |
TW201206267A (en) | 2012-02-01 |
EP2389049B1 (en) | 2013-03-06 |
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