JP2011151394A - 半導体装置およびその作製方法 - Google Patents
半導体装置およびその作製方法 Download PDFInfo
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- JP2011151394A JP2011151394A JP2010287718A JP2010287718A JP2011151394A JP 2011151394 A JP2011151394 A JP 2011151394A JP 2010287718 A JP2010287718 A JP 2010287718A JP 2010287718 A JP2010287718 A JP 2010287718A JP 2011151394 A JP2011151394 A JP 2011151394A
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- Prior art keywords
- oxide semiconductor
- semiconductor layer
- insulating layer
- transistor
- drain electrode
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Images
Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
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Abstract
【解決手段】酸化物半導体層と、酸化物半導体層と電気的に接続するソース電極およびドレイン電極と、酸化物半導体層、ソース電極およびドレイン電極を覆うゲート絶縁層と、ゲート絶縁層上のゲート電極と、を有し、酸化物半導体層の厚さは1nm以上10nm以下であり、ゲート絶縁層は、ゲート絶縁層に用いられる材料の比誘電率をεr、ゲート絶縁層の厚さをdとして、εr/dが、0.08(nm−1)以上7.9(nm−1)以下の関係を満たし、ソース電極とドレイン電極との間隔は10nm以上1μm以下である半導体装置である。
【選択図】図1
Description
本実施の形態では、開示する発明の一態様に係る半導体装置の構成について、図1を参照して説明する。なお、以下では、トップゲート型のトランジスタを例に挙げて説明するが、トランジスタの構成をトップゲート型に限る必要はない。
本実施の形態では、酸化物半導体(特に非晶質構造)を用いた半導体装置の作製方法、具体的には、図1(A)に相当する半導体装置の作製方法について、図2を用いて説明する。なお、以下では、トップゲート型のトランジスタを例に挙げて説明するが、トランジスタの構成をトップゲート型に限る必要はない。
本実施の形態では、酸化物半導体を用いた半導体装置の作製方法について、図3を用いて説明する。本実施の形態では、酸化物半導体層として、結晶領域を有する第1の酸化物半導体層と、第1の酸化物半導体層の結晶領域から結晶成長させた第2の酸化物半導体層を用いる場合、すなわち、図1(B)に相当する半導体装置の作製方法について、詳細に説明する。なお、第1の酸化物半導体層のみで必要な厚さを確保できる場合には、第2の酸化物半導体層は不要である。また、以下では、トップゲート型のトランジスタを例に挙げて説明するが、トランジスタの構成をトップゲート型に限る必要はない。
本実施の形態では、酸化物半導体を用いた半導体装置の作製方法、具体的には、図1(C)に相当する半導体装置の作製方法について、図4を用いて説明する。なお、本実施の形態に係る半導体装置の作製方法は、先の実施の形態(特に、実施の形態2)において説明した半導体装置の作製方法と多くの部分で共通している。このため、以下では主として相違点について説明することとする。なお、本実施の形態の作製方法を先の実施の形態(実施の形態3など)の一部と組み合わせることで、図1(D)に相当する半導体装置を作製することも可能である。
本実施の形態では、先の実施の形態に示すトランジスタを用いた半導体装置の例につき、図5乃至図8を参照して説明する。
図5(A)に、先の実施の形態に示すトランジスタを、ダイオードとして用いる場合の回路構成を示す。ダイオード接続されたトランジスタ110は、ゲート端子および第1端子側がアノードであり、第2端子側がカソードとなる。
次に、先の実施の形態に係るトランジスタを用いた、不揮発性の記憶装置の構成例について、図7および図8を用いて説明する。
本実施の形態では、上述の実施の形態で説明した半導体装置を電子機器に適用する場合について、図9を用いて説明する。本実施の形態では、コンピュータ、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯情報端末(携帯型ゲーム機、音響再生装置なども含む)、デジタルカメラ、デジタルビデオカメラ、電子ペーパー、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう)などの電子機器に、上述の半導体装置を適用する場合について説明する。
112 トランジスタ
114 トランジスタ
120 メモリセルアレイ
130 メモリセル
131 トランジスタ
132 容量素子
140 メモリセルアレイ
150 メモリセル
151 トランジスタ
152 トランジスタ
153 トランジスタ
154 トランジスタ
155 トランジスタ
156 トランジスタ
160 トランジスタ
162 トランジスタ
164 容量素子
190 メモリセル
200 基板
202 絶縁層
206 酸化物半導体層
206a 酸化物半導体層
208a ソース電極又はドレイン電極
208b ソース電極又はドレイン電極
212 ゲート絶縁層
214 ゲート電極
216 層間絶縁層
218 層間絶縁層
250 トランジスタ
300 基板
302 絶縁層
304 酸化物半導体層
304a 酸化物半導体層
305 酸化物半導体層
306 酸化物半導体層
306a 酸化物半導体層
308a ソース電極又はドレイン電極
308b ソース電極又はドレイン電極
312 ゲート絶縁層
314 ゲート電極
316 層間絶縁層
318 層間絶縁層
350 トランジスタ
400 基板
402 絶縁層
406 酸化物半導体層
406a 酸化物半導体層
408 導電層
408a ソース電極又はドレイン電極
408b ソース電極又はドレイン電極
410 絶縁層
410a 絶縁層
410b 絶縁層
411a 酸化領域
411b 酸化領域
412 ゲート絶縁層
414 ゲート電極
416 層間絶縁層
418 層間絶縁層
450 トランジスタ
500 基板
502 絶縁層
504a 酸化物半導体層
506a 酸化物半導体層
508a ソース電極又はドレイン電極
508b ソース電極又はドレイン電極
510a 絶縁層
510b 絶縁層
511a 酸化領域
511b 酸化領域
512 ゲート絶縁層
514 ゲート電極
516 層間絶縁層
518 層間絶縁層
550 トランジスタ
601 筐体
602 筐体
603 表示部
604 キーボード
611 本体
612 スタイラス
613 表示部
614 操作ボタン
615 外部インターフェイス
620 電子書籍
621 筐体
623 筐体
625 表示部
627 表示部
631 電源
633 操作キー
635 スピーカー
637 軸部
640 筐体
641 筐体
642 表示パネル
643 スピーカー
644 マイクロフォン
646 ポインティングデバイス
647 カメラ用レンズ
648 外部接続端子
649 太陽電池セル
650 外部メモリスロット
661 本体
663 接眼部
664 操作スイッチ
665 表示部
666 バッテリー
667 表示部
670 テレビジョン装置
671 筐体
673 表示部
675 スタンド
680 リモコン操作機
Claims (14)
- 酸化物半導体層と、前記酸化物半導体層と電気的に接続するソース電極およびドレイン電極と、前記酸化物半導体層、前記ソース電極および前記ドレイン電極を覆うゲート絶縁層と、前記ゲート絶縁層上のゲート電極と、を有し、
前記酸化物半導体層の厚さは1nm以上10nm以下であり、
前記ゲート絶縁層は、前記ゲート絶縁層に用いられる材料の比誘電率をεr、前記ゲート絶縁層の厚さをdとして、εr/dが、0.08(nm−1)以上7.9(nm−1)以下の関係を満たし、
前記ソース電極と前記ドレイン電極との間隔は10nm以上1μm以下である半導体装置。 - 前記ソース電極および前記ドレイン電極は、その側面が酸化された酸化領域を有する、請求項1に記載の半導体装置。
- 前記ソース電極および前記ドレイン電極の酸化領域は、300MHz以上300GHz以下の高周波電力、および、酸素とアルゴンの混合ガスを用いたプラズマ処理により形成されたものである、請求項2に記載の半導体装置。
- 前記酸化物半導体層は、前記プラズマ処理によって酸素が供給されたものである、請求項3に記載の半導体装置。
- 前記ソース電極および前記ドレイン電極の上に、平面形状が前記ソース電極および前記ドレイン電極と略同一の絶縁層を有する、請求項1乃至請求項4のいずれか一に記載の半導体装置。
- オフ電流密度が100zA/μm以下である、請求項1乃至請求項4のいずれか一に記載の半導体装置。
- 算術平均粗さが1nm以下の表面上に形成された、請求項1乃至請求項6のいずれか一に記載の半導体装置。
- 基板上に酸化物半導体層を形成し、
前記酸化物半導体層と電気的に接続するソース電極およびドレイン電極を形成し、
前記ソース電極および前記ドレイン電極の側面を酸化した後に、前記酸化物半導体層、前記ソース電極および前記ドレイン電極を覆うゲート絶縁層を形成し、
前記ゲート絶縁層上にゲート電極を形成する、半導体装置の作製方法。 - 前記ソース電極および前記ドレイン電極の側面の酸化は、300MHz以上300GHz以下の高周波電力、および、酸素とアルゴンの混合ガスを用いたプラズマ処理によって行われる、請求項8に記載の半導体装置の作製方法。
- 前記プラズマ処理によって、前記酸化物半導体層に酸素を供給する、請求項9に記載の半導体装置の作製方法。
- 前記プラズマ処理を行う前に、前記酸化物半導体層の水素を低減する処理を行う、請求項9または請求項10に記載の半導体装置の作製方法。
- 前記酸化物半導体層を、その厚さが1nm以上10nm以下となるように形成し、
前記ゲート絶縁層を、前記ゲート絶縁層に用いられる材料の比誘電率をεr、前記ゲート絶縁層の厚さをdとして、εr/dが、0.08(nm−1)以上7.9(nm−1)以下の関係を満たすように形成し、
前記ソース電極と前記ドレイン電極を、その間隔が10nm以上1μm以下となるように形成する、請求項8乃至請求項11のいずれか一に記載の半導体装置の作製方法。 - 前記ソース電極および前記ドレイン電極上に、平面形状が前記ソース電極および前記ドレイン電極と略同一の絶縁層を形成する、請求項8乃至請求項12のいずれか一に記載の半導体装置の作製方法。
- 前記基板として、算術平均粗さが1nm以下の表面を有する基板を用いる、請求項8乃至請求項13のいずれか一に記載の半導体装置の作製方法。
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US9543445B2 (en) | 2017-01-10 |
JP5079076B2 (ja) | 2012-11-21 |
JP6109372B2 (ja) | 2017-04-05 |
KR101811203B1 (ko) | 2017-12-22 |
US8664652B2 (en) | 2014-03-04 |
KR102111309B1 (ko) | 2020-05-15 |
TWI503977B (zh) | 2015-10-11 |
KR20170142998A (ko) | 2017-12-28 |
KR20120106874A (ko) | 2012-09-26 |
JP2016129265A (ja) | 2016-07-14 |
KR20130054469A (ko) | 2013-05-24 |
JP2013030783A (ja) | 2013-02-07 |
US20150194535A1 (en) | 2015-07-09 |
TWI608622B (zh) | 2017-12-11 |
TW201539766A (zh) | 2015-10-16 |
JP2015092638A (ja) | 2015-05-14 |
WO2011077966A1 (en) | 2011-06-30 |
US20110156022A1 (en) | 2011-06-30 |
TW201138117A (en) | 2011-11-01 |
US20140127874A1 (en) | 2014-05-08 |
US9006025B2 (en) | 2015-04-14 |
KR20190029791A (ko) | 2019-03-20 |
TW201719899A (zh) | 2017-06-01 |
KR101301463B1 (ko) | 2013-08-29 |
TWI553872B (zh) | 2016-10-11 |
JP5917737B2 (ja) | 2016-05-18 |
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