JP2009194059A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2009194059A JP2009194059A JP2008031543A JP2008031543A JP2009194059A JP 2009194059 A JP2009194059 A JP 2009194059A JP 2008031543 A JP2008031543 A JP 2008031543A JP 2008031543 A JP2008031543 A JP 2008031543A JP 2009194059 A JP2009194059 A JP 2009194059A
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- Lead Frames For Integrated Circuits (AREA)
Abstract
【解決手段】タブ1fと、タブ1fの周囲に配置された複数のリード1aと、タブ1f上に搭載された半導体チップ2と、半導体チップ2の電極パッド2eとリード1aとを電気的に接続する複数のワイヤ4と、半導体チップ2を樹脂封止する封止体とを有している。さらに半導体チップ2の主面の第1辺の中央部から端部に向かうにつれてリード1aのチップ側の先端部を段階的に短くするとともに、主面の第1辺の中央部の第1リード1bと端部側の第2リード1cとにおいて、第2リード1cに隣接する第1リード1bの先端部を短くしたことで、第2リード1cに接続される第2ワイヤ4bとこの第2リード1cに隣接する第1リード1bの先端部との距離を広げることができ、その結果、モールド樹脂の流動抵抗によりワイヤ流れが発生してもワイヤショート不良を防止することができる。
【選択図】図3
Description
図1は本発明の実施の形態の半導体装置の構造の一例を示す平面図、図2は図1に示すA−A線に沿って切断した構造の一例を示す断面図、図3は図1に示す半導体装置におけるワイヤリング状態の一例を示す拡大部分平面図である。また、図13は本発明の実施の形態の変形例の半導体装置の組み立てにおけるワイヤボンディング後の構造を示す部分平面図である。
1a リード
1b 第1リード
1c 第2リード
1d アウタ部
1e インナ部
1f タブ(チップ搭載部)
1g チップ支持面
1h 裏面
1i 段差部
1j 吊りリード
1k 曲げ部
1m ワイヤ接続面
1n 肉逃げ部
1p ノンコネクト用リード
2 半導体チップ
2a 主面
2b 裏面
2c 第1辺(辺)
2d 第2辺(他の辺)
2e 電極パッド
2f 第1電極パッド
2g 第2電極パッド
3 封止体
3a 実装面
4 ワイヤ
4a 第1ワイヤ
4b 第2ワイヤ
4c 第3ワイヤ
5 QFN(半導体装置)
6 モールドライン
7 キャピラリ
Claims (16)
- チップ支持面を備えたチップ搭載部と、
前記チップ搭載部を支持する吊りリードと、
四角形の主面を有し、前記主面の第1辺の中央部に配置された第1電極パッド及び前記第1電極パッドよりも前記第1辺の角部側に配置された第2電極パッドが設けられ、前記チップ搭載部の前記チップ支持面上に搭載された半導体チップと、
前記半導体チップの前記第1辺の前記中央部に対応して設けられた第1リードと、
前記第1リードよりも前記吊りリード側に配置された第2リードと、
前記第1電極パッドと前記第1リードを電気的に接続する第1ワイヤと、
前記第2電極パッドと前記第2リードを電気的に接続する第2ワイヤとを有し、
前記半導体チップの前記主面には、前記第1電極パッド及び前記第2電極パッドを含む複数の電極パッドが形成され、
前記チップ搭載部の周囲には、前記第1リード及び前記第2リードを含む複数のリードが配置され、
前記第1ワイヤ及び前記第2ワイヤを含む複数のワイヤが設けられ、
前記第1ワイヤは、前記第2ワイヤより短いことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、前記第1ワイヤは、前記半導体チップの前記第1辺と直角に交差する方向に形成されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記第1ワイヤは、前記第1辺と交差する他の辺に平行な方向に形成されていることを特徴とする半導体装置。
- 請求項2記載の半導体装置において、前記第2ワイヤは、前記第2ワイヤと前記第1辺との成す角度が、前記第1ワイヤと前記第1辺との成す角度より小さくなるように形成されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記第1リードのチップ側の先端部は、前記第2リードのチップ側の先端部より前記半導体チップの近くに位置していることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記第1電極パッドは、信号用の電極パッドであることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記チップ搭載部の外形寸法は、前記半導体チップの外形寸法より小さいことを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記複数の電極パッドのうち隣接する電極パッドのピッチは、前記複数のリードのうち隣接するリードのピッチより小さいことを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記複数のリードは、チップ側から放射状に延在していることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記半導体チップの前記第1辺に対応した前記複数のリードそれぞれのチップ側の先端部は、前記第1辺の前記中央部から端部に向かうにつれて前記半導体チップから段階的に離れていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記半導体チップの前記第2電極パッドと前記吊りリードとを電気的に接続する第3ワイヤが設けられていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記複数のリードそれぞれのワイヤ接続面は、前記チップ搭載部の裏面を基準にして前記チップ支持面側において前記チップ支持面より遠ざかる方向に位置していることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記半導体チップ及び前記複数のワイヤを封止する封止体が形成され、前記チップ搭載部は前記封止体の実装面から露出していることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記半導体チップ及び前記複数のワイヤを封止する封止体が形成され、前記複数のリードそれぞれは、前記封止体の実装面に露出するアウタ部と前記封止体の内部に配置されるインナ部とを有していることを特徴とする半導体装置。
- (a)チップ支持面を備えたチップ搭載部と、前記チップ搭載部を支持する吊りリードと、前記チップ搭載部の周囲に設けられた複数のリードとを有するリードフレームを準備する工程と、
(b)主面が四角形を成し、かつ前記主面に複数の電極パッドが形成された半導体チップを前記チップ搭載部の前記チップ支持面上に搭載する工程と、
(c)前記半導体チップの前記複数の電極パッドのうち、前記半導体チップの前記主面の第1辺の中央部に設けられた第1電極パッドと、前記第1辺の前記中央部に対応して設けられた第1リードとを第1ワイヤによって電気的に接続するとともに、前記第1電極パッドよりも前記第1辺の端部側に設けられた第2電極パッドと、前記第1リードよりも前記吊りリード側に位置する第2リードとを第2ワイヤによって電気的に接続する工程とを有し、
前記(c)工程では、前記複数の電極パッドとそれぞれに対応する前記複数のリードとを、それぞれキャピラリを用いてワイヤにより前記電極パッド側を接続した後、前記リード側を接続し、
前記第1ワイヤを前記第2ワイヤより短く形成することを特徴とする半導体装置の製造方法。 - 請求項15記載の半導体装置の製造方法において、前記(c)工程の後、前記半導体チップと複数の前記ワイヤを樹脂封止する樹脂封止工程を有することを特徴とする半導体装置の製造方法。
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US12/883,468 US7964941B2 (en) | 2008-02-13 | 2010-09-16 | Semiconductor device and manufacturing method of the same |
US13/115,639 US8148200B2 (en) | 2008-02-13 | 2011-05-25 | Semiconductor device and manufacturing method of the same |
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JP2019071488A (ja) * | 2019-02-06 | 2019-05-09 | ローム株式会社 | 半導体装置 |
WO2023189650A1 (ja) * | 2022-03-31 | 2023-10-05 | ローム株式会社 | 半導体装置 |
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JP5588147B2 (ja) * | 2009-10-26 | 2014-09-10 | キヤノン株式会社 | 半導体装置及び半導体装置を搭載したプリント基板 |
CN102487025B (zh) * | 2010-12-08 | 2016-07-06 | 飞思卡尔半导体公司 | 用于长结合导线的支撑体 |
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US10271448B2 (en) * | 2012-08-06 | 2019-04-23 | Investar Corporation | Thin leadframe QFN package design of RF front-ends for mobile wireless communication |
US20150262919A1 (en) * | 2014-03-14 | 2015-09-17 | Texas Instruments Incorporated | Structure and method of packaged semiconductor devices with qfn leadframes having stress-absorbing protrusions |
JP6695156B2 (ja) * | 2016-02-02 | 2020-05-20 | エイブリック株式会社 | 樹脂封止型半導体装置 |
FR3064817B1 (fr) * | 2017-04-04 | 2021-07-23 | United Monolithic Semiconductors Sas | Boitier plastique non coplanaire d'encapsulation d'un composant electronique hyperfrequence de puissance |
JP7338204B2 (ja) * | 2019-04-01 | 2023-09-05 | 富士電機株式会社 | 半導体装置 |
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JPH06216303A (ja) * | 1992-03-27 | 1994-08-05 | Hitachi Ltd | リードフレーム、その製造方法およびそれを用いた半導体集積回路装置の製造方法 |
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WO2023189650A1 (ja) * | 2022-03-31 | 2023-10-05 | ローム株式会社 | 半導体装置 |
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