JP2008288489A - チップ内蔵基板の製造方法 - Google Patents
チップ内蔵基板の製造方法 Download PDFInfo
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- JP2008288489A JP2008288489A JP2007133947A JP2007133947A JP2008288489A JP 2008288489 A JP2008288489 A JP 2008288489A JP 2007133947 A JP2007133947 A JP 2007133947A JP 2007133947 A JP2007133947 A JP 2007133947A JP 2008288489 A JP2008288489 A JP 2008288489A
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- 239000000758 substrate Substances 0.000 title claims abstract description 169
- 238000000034 method Methods 0.000 title claims abstract description 24
- 230000008569 process Effects 0.000 title abstract description 11
- 229920005989 resin Polymers 0.000 claims abstract description 49
- 239000011347 resin Substances 0.000 claims abstract description 49
- 238000007789 sealing Methods 0.000 claims abstract description 37
- 229910000679 solder Inorganic materials 0.000 claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 claims description 22
- 238000005476 soldering Methods 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 230000004907 flux Effects 0.000 description 15
- 238000004140 cleaning Methods 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
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- H—ELECTRICITY
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
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- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
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- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1305—Moulding and encapsulation
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
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- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
【解決手段】第1の基板10にチップ部品13をワイヤ14で接続する工程と、第2の基板20に電極21を設ける工程と、第1の基板10のバンプ接続用パッド12の配列に対応して形成された突出部31及びチップ部品13の搭載領域に対応して形成されたキャビティ32とを有する金型30を第1の基板10に装着してチップ部品13及びワイヤ14を封止する第1の封止樹脂34形成する工程と、電極21とバンプ接続用パッド12をはんだ接合して第1の基板10と第2の基板20とを接合する工程と、第1の基板10と第2の基板20との離間部分に第2の封止樹脂40を充填する工程とを有する。
【選択図】図1
Description
接続用パッドが形成された第1の基板に、チップ部品をワイヤボンディング接続する工程と、
第2の基板に基板表面から突出する電極を設ける工程と、
前記接続用パッドの配列と対応して形成された突出部と、前記チップ部品の搭載領域に対応して形成されたキャビティとを有する金型を前記第1の基板に装着し、前記突出部を前記接続用パッド表面に当接させると共に該キャビティに第1の樹脂を充填して前記チップ部品及びワイヤを樹脂封止する工程と、
前記接続用パッドと前記電極を接合し、樹脂封止された前記チップ部品が内蔵されるよう前記第1の基板と前記第2の基板を接合する工程と、
前記第1の基板と前記第2の基板との離間部分に第2の樹脂を充填する工程と
を有することを特徴とするチップ内蔵基板の製造方法により解決することができる。
特に本実施例では、溝部36内にバンプ接続用パッド12が形成されることにより、全てのバンプ接続用パッド12を第1の基板10の外周位置に配置する必要がなくなる。以下、これについて説明する。
10 第1の基板
11,12 ワイヤ接続用パッド
13 チップ部品
14 ワイヤ
20 第2の基板
21 電極
22 銅コア
23 はんだ被膜
25 空間部
30 金型
31 突出部
32 キャビティ
34 第1の封止樹脂
35 はんだフラックス
40 第2の封止樹脂
50A,50B 電子装置
51 はんだボール
62 電子部品
Claims (3)
- 接続用パッドが形成された第1の基板に、チップ部品をワイヤボンディング接続する工程と、
第2の基板に基板表面から突出する電極を設ける工程と、
前記接続用パッドの配列と対応して形成された突出部と、前記チップ部品の搭載領域に対応して形成されたキャビティとを有する金型を前記第1の基板に装着し、前記突出部を前記接続用パッド表面に当接させると共に該キャビティに第1の樹脂を充填して前記チップ部品及びワイヤを樹脂封止する工程と、
前記接続用パッドと前記電極をはんだ接合し、樹脂封止された前記チップ部品が内蔵されるよう前記第1の基板と前記第2の基板を接合する工程と、
前記第1の基板と前記第2の基板との離間部分に第2の樹脂を充填する工程と
を有することを特徴とするチップ内蔵基板の製造方法。 - 前記電極は、銅よりなる金属コアにはんだ膜が被膜された構成であることを特徴とする請求項1記載のチップ内蔵基板の製造方法。
- 前記接続用パッドは、隣接する前記チップ部品が樹脂封止される封止領域の間の位置に設けられていることを特徴とする請求項1又は2記載のチップ内蔵基板の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2007133947A JP4864810B2 (ja) | 2007-05-21 | 2007-05-21 | チップ内蔵基板の製造方法 |
US12/123,744 US7807510B2 (en) | 2007-05-21 | 2008-05-20 | Method of manufacturing chip integrated substrate |
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JP2007133947A JP4864810B2 (ja) | 2007-05-21 | 2007-05-21 | チップ内蔵基板の製造方法 |
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JP2008288489A true JP2008288489A (ja) | 2008-11-27 |
JP2008288489A5 JP2008288489A5 (ja) | 2010-03-25 |
JP4864810B2 JP4864810B2 (ja) | 2012-02-01 |
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JP2007133947A Active JP4864810B2 (ja) | 2007-05-21 | 2007-05-21 | チップ内蔵基板の製造方法 |
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US (1) | US7807510B2 (ja) |
JP (1) | JP4864810B2 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010192812A (ja) * | 2009-02-20 | 2010-09-02 | Sharp Corp | 電子機器モジュール |
KR20100129577A (ko) * | 2009-06-01 | 2010-12-09 | 삼성전자주식회사 | 반도체 소자 패키지의 형성방법 |
JP2011192854A (ja) * | 2010-03-16 | 2011-09-29 | Casio Computer Co Ltd | 半導体装置及び半導体装置の製造方法 |
JP2013183137A (ja) * | 2012-03-05 | 2013-09-12 | Denso Corp | 回路基板及び回路部品を基板に搭載する方法 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5563918B2 (ja) * | 2010-07-22 | 2014-07-30 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 回路装置の製造方法 |
US8569882B2 (en) * | 2011-03-24 | 2013-10-29 | Stats Chippac Ltd. | Integrated circuit packaging system with collapsed multi-integration package and method of manufacture thereof |
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US20080293189A1 (en) | 2008-11-27 |
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