JP2008218980A - 電子素子パッケージ及びその製造方法 - Google Patents
電子素子パッケージ及びその製造方法 Download PDFInfo
- Publication number
- JP2008218980A JP2008218980A JP2008001872A JP2008001872A JP2008218980A JP 2008218980 A JP2008218980 A JP 2008218980A JP 2008001872 A JP2008001872 A JP 2008001872A JP 2008001872 A JP2008001872 A JP 2008001872A JP 2008218980 A JP2008218980 A JP 2008218980A
- Authority
- JP
- Japan
- Prior art keywords
- electronic device
- insulating layer
- cavity
- device package
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
- 239000000853 adhesive Substances 0.000 claims abstract description 37
- 230000001070 adhesive effect Effects 0.000 claims abstract description 37
- 239000000463 material Substances 0.000 claims description 13
- 239000004642 Polyimide Substances 0.000 claims description 9
- 229920001721 polyimide Polymers 0.000 claims description 9
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 2
- 230000005855 radiation Effects 0.000 abstract description 2
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 48
- 238000000034 method Methods 0.000 description 42
- 229910000679 solder Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/38—Cooling arrangements using the Peltier effect
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01076—Osmium [Os]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/066—Heatsink mounted on the surface of the PCB
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
【解決手段】本発明に係る電子素子パッケージの製造方法は、第1絶縁層の一面に電子素子を実装するステップと、電子素子をカバーするように、電子素子に対応してキャビティが形成された放熱板を第1絶縁層の一面にボンディングするステップと、キャビティに接着剤を充填するステップと、第1絶縁層の他面に回路パターンを形成するステップと、を含むことを特徴とする。
【選択図】図3
Description
20:第1絶縁層
22,52:ビアホール
24、54:回路パターン
26,56:メッキ層
30:接着剤
40:放熱板
42:キャビティ
44:注入口
46:吸入口
50:第2絶縁層
62:ソルダレジスト
64:ランド
66:ソルダバンプ
Claims (11)
- 第1絶縁層の一面に電子素子を実装するステップと、
前記電子素子をカバーするように、前記電子素子に対応してキャビティが形成された放熱板を前記第1絶縁層の一面にボンディングするステップと、
前記キャビティに接着剤を充填するステップと、
前記第1絶縁層の他面に回路パターンを形成するステップと、
を含む電子素子パッケージの製造方法。 - 前記放熱板には、前記キャビティに前記接着剤を注入するための注入口と、前記キャビティに陰圧を提供するための吸入口が形成され、
前記接着剤を充填するステップが、
前記吸入口を介して前記キャビティに陰圧を提供するステップと、
前記注入口を介して前記キャビティに前記接着剤を注入するステップと、
を含むことを特徴とする請求項1に記載の電子素子パッケージの製造方法。 - 前記注入口と前記吸入口が、互いに対向する面に形成されることを特徴とする請求項2に記載の電子素子パッケージの製造方法。
- 前記接着剤が、熱媒介物質(TIM)を含む材質からなることを特徴とする請求項1に記載の電子素子パッケージの製造方法。
- 前記第1絶縁層が、ポリイミド(PI)を含む材質からなることを特徴とする請求項1に記載の電子素子パッケージの製造方法。
- 前記第1絶縁層の他面にレイアップ層を積層するステップをさらに含む請求項1に記載の電子素子パッケージの製造方法。
- 第1絶縁層と、
前記第1絶縁層の一面に実装される電子素子と、
前記電子素子に対応してキャビティが形成され、前記電子素子をカバーするように前記第1絶縁層の一面にボンディングされる放熱板と、
前記キャビティに充填される接着剤と、
前記第1絶縁層の他面に形成される回路パターンと、
を含み、
前記放熱板には、前記放熱板を貫通する注入口と吸入口が各々形成されることを特徴とする電子素子パッケージ。 - 前記注入口と前記吸入口が、互いに対向する面に形成されることを特徴とする請求項7に記載の電子素子パッケージ。
- 前記接着剤が、熱媒介物質(TIM)を含む材質からなることを特徴とする請求項7に記載の電子素子パッケージ。
- 前記第1絶縁層が、ポリイミド(PI)を含む材質からなることを特徴とする請求項7に記載の電子素子パッケージ。
- 前記第1絶縁層の他面に積層されるレイアップ層をさらに含む請求項7に記載の電子素子パッケージ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070020940A KR100810491B1 (ko) | 2007-03-02 | 2007-03-02 | 전자소자 패키지 및 그 제조방법 |
KR10-2007-0020940 | 2007-03-02 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008218980A true JP2008218980A (ja) | 2008-09-18 |
JP4839471B2 JP4839471B2 (ja) | 2011-12-21 |
Family
ID=39397760
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008001872A Expired - Fee Related JP4839471B2 (ja) | 2007-03-02 | 2008-01-09 | 電子素子パッケージ及びその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US8779580B2 (ja) |
JP (1) | JP4839471B2 (ja) |
KR (1) | KR100810491B1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014082233A (ja) * | 2012-10-12 | 2014-05-08 | Sumitomo Electric Ind Ltd | 半導体装置及びその製造方法 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101003585B1 (ko) * | 2008-06-25 | 2010-12-22 | 삼성전기주식회사 | 전자부품 내장형 인쇄회로기판 및 그 제조방법 |
US8518749B2 (en) * | 2009-06-22 | 2013-08-27 | Stats Chippac, Ltd. | Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die |
US8497587B2 (en) * | 2009-12-30 | 2013-07-30 | Stmicroelectronics Pte Ltd. | Thermally enhanced expanded wafer level package ball grid array structure and method of making the same |
CN102738022B (zh) * | 2011-04-15 | 2017-05-17 | 飞思卡尔半导体公司 | 组装包括绝缘衬底和热沉的半导体器件的方法 |
CN104350592A (zh) * | 2012-02-09 | 2015-02-11 | 诺基亚通信公司 | 用于在安装具有导热垫的组件时减少机械应力的方法和装置 |
US20200035614A1 (en) * | 2018-07-30 | 2020-01-30 | Powertech Technology Inc. | Package structure and manufacturing method thereof |
US11348857B2 (en) * | 2020-06-16 | 2022-05-31 | Micron Technology, Inc. | Lidded microelectronic device packages and related systems, apparatus, and methods of manufacture |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04124859A (ja) * | 1990-09-14 | 1992-04-24 | Fujitsu Ltd | 半導体装置 |
JPH07254668A (ja) * | 1994-01-11 | 1995-10-03 | Samsung Electron Co Ltd | 高熱放出用の半導体パッケージ |
JPH07263618A (ja) * | 1994-03-24 | 1995-10-13 | Nippondenso Co Ltd | 混成集積回路装置 |
JP2002100872A (ja) * | 1999-09-02 | 2002-04-05 | Ibiden Co Ltd | プリント配線板及びプリント配線板の製造方法 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6150353A (ja) * | 1984-08-20 | 1986-03-12 | Oki Electric Ind Co Ltd | Eprom装置 |
US5817545A (en) * | 1996-01-24 | 1998-10-06 | Cornell Research Foundation, Inc. | Pressurized underfill encapsulation of integrated circuits |
US6016006A (en) * | 1996-06-24 | 2000-01-18 | Intel Corporation | Thermal grease insertion and retention |
KR100258854B1 (ko) * | 1996-12-31 | 2000-06-15 | 김영환 | 에리어 어레이형 반도체 패키지 및 그 제조 방법 |
US6008536A (en) * | 1997-06-23 | 1999-12-28 | Lsi Logic Corporation | Grid array device package including advanced heat transfer mechanisms |
TW411037U (en) * | 1999-06-11 | 2000-11-01 | Ind Tech Res Inst | Integrated circuit packaging structure with dual directions of thermal conduction path |
JP3277997B2 (ja) | 1999-06-29 | 2002-04-22 | 日本電気株式会社 | ボールグリッドアレイパッケージとその製造方法 |
US6187613B1 (en) * | 1999-11-04 | 2001-02-13 | Industrial Technology Research Institute | Process for underfill encapsulating flip chip driven by pressure |
US6617682B1 (en) * | 2000-09-28 | 2003-09-09 | Intel Corporation | Structure for reducing die corner and edge stresses in microelectronic packages |
JP2002221801A (ja) * | 2001-01-29 | 2002-08-09 | Hitachi Ltd | 配線基板の製造方法 |
KR100446290B1 (ko) * | 2001-11-03 | 2004-09-01 | 삼성전자주식회사 | 댐을 포함하는 반도체 패키지 및 그 제조방법 |
KR20030043172A (ko) * | 2001-11-27 | 2003-06-02 | 오리엔트 세미컨덕터 일렉트로닉스 리미티드 | 방열판 및 그를 구비한 반도체 칩 패키지 |
US6767765B2 (en) * | 2002-03-27 | 2004-07-27 | Intel Corporation | Methods and apparatus for disposing a thermal interface material between a heat source and a heat dissipation device |
US20040126547A1 (en) * | 2002-12-31 | 2004-07-01 | Coomer Boyd L. | Methods for performing substrate imprinting using thermoset resin varnishes and products formed therefrom |
US20040178514A1 (en) * | 2003-03-12 | 2004-09-16 | Lee Sang-Hyeop | Method of encapsulating semiconductor devices on a printed circuit board, and a printed circuit board for use in the method |
TWI228806B (en) * | 2003-05-16 | 2005-03-01 | Advanced Semiconductor Eng | Flip chip package |
US6747350B1 (en) * | 2003-06-06 | 2004-06-08 | Silicon Integrated Systems Corp. | Flip chip package structure |
US6979600B2 (en) * | 2004-01-06 | 2005-12-27 | Intel Corporation | Apparatus and methods for an underfilled integrated circuit package |
US7160758B2 (en) * | 2004-03-31 | 2007-01-09 | Intel Corporation | Electronic packaging apparatus and method |
US20070200210A1 (en) * | 2006-02-28 | 2007-08-30 | Broadcom Corporation | Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages |
US8115301B2 (en) * | 2006-11-17 | 2012-02-14 | Stats Chippac, Inc. | Methods for manufacturing thermally enhanced flip-chip ball grid arrays |
-
2007
- 2007-03-02 KR KR1020070020940A patent/KR100810491B1/ko not_active IP Right Cessation
-
2008
- 2008-01-09 JP JP2008001872A patent/JP4839471B2/ja not_active Expired - Fee Related
- 2008-01-23 US US12/010,321 patent/US8779580B2/en not_active Expired - Fee Related
-
2014
- 2014-07-01 US US14/321,214 patent/US20140313676A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04124859A (ja) * | 1990-09-14 | 1992-04-24 | Fujitsu Ltd | 半導体装置 |
JPH07254668A (ja) * | 1994-01-11 | 1995-10-03 | Samsung Electron Co Ltd | 高熱放出用の半導体パッケージ |
JPH07263618A (ja) * | 1994-03-24 | 1995-10-13 | Nippondenso Co Ltd | 混成集積回路装置 |
JP2002100872A (ja) * | 1999-09-02 | 2002-04-05 | Ibiden Co Ltd | プリント配線板及びプリント配線板の製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014082233A (ja) * | 2012-10-12 | 2014-05-08 | Sumitomo Electric Ind Ltd | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20080212288A1 (en) | 2008-09-04 |
KR100810491B1 (ko) | 2008-03-07 |
US20140313676A1 (en) | 2014-10-23 |
JP4839471B2 (ja) | 2011-12-21 |
US8779580B2 (en) | 2014-07-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4839471B2 (ja) | 電子素子パッケージ及びその製造方法 | |
JP5267604B2 (ja) | 配線板及びその製造方法 | |
TWI476888B (zh) | 嵌埋穿孔中介層之封裝基板及其製法 | |
US9456492B2 (en) | Printed circuit board with warpage prevention layer | |
CN100463128C (zh) | 半导体芯片埋入基板的三维构装结构及其制作方法 | |
JP4730426B2 (ja) | 実装基板及び半導体モジュール | |
JP2008028376A (ja) | 回路基板、半導体モジュールおよび回路基板の製造方法 | |
TW200302685A (en) | Circuit component built-in module and method of manufacturing the same | |
JP2009032918A (ja) | 配線基板及びその製造方法と電子部品装置及びその製造方法 | |
JP2001217337A (ja) | 半導体装置及びその製造方法 | |
JP2007535156A (ja) | 埋込み構成要素からの熱伝導 | |
US8581421B2 (en) | Semiconductor package manufacturing method and semiconductor package | |
JP2015106615A (ja) | プリント配線板、プリント配線板の製造方法 | |
JP2012212786A (ja) | 半導体装置の製造方法 | |
JP2008311520A (ja) | 電子部品内蔵基板の製造方法 | |
TWI391084B (zh) | 具有散熱件之電路板結構 | |
JP6228851B2 (ja) | 配線基板、配線基板の製造方法 | |
JP2010062199A (ja) | 回路基板 | |
JP4408090B2 (ja) | 部品内蔵モジュールの製造方法 | |
JP2017143096A (ja) | 配線基板、半導体装置及び配線基板の製造方法 | |
JP2022145713A (ja) | ベーパーチャンバー製造用金属部材 | |
KR101092945B1 (ko) | 패키지 기판, 이를 구비한 전자소자 패키지, 및 패키지 기판 제조 방법 | |
JP2008243966A (ja) | 電子部品が実装されたプリント基板及びその製造方法 | |
KR100872125B1 (ko) | 반도체 패키지 및 그 제조방법 | |
JP2017103426A (ja) | 半導体パッケージおよびパッケージ・オン・パッケージ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100928 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101005 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101118 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110215 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110513 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110906 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110914 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141014 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |