JP2008166373A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2008166373A JP2008166373A JP2006352041A JP2006352041A JP2008166373A JP 2008166373 A JP2008166373 A JP 2008166373A JP 2006352041 A JP2006352041 A JP 2006352041A JP 2006352041 A JP2006352041 A JP 2006352041A JP 2008166373 A JP2008166373 A JP 2008166373A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 235
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 239000011347 resin Substances 0.000 claims abstract description 40
- 229920005989 resin Polymers 0.000 claims abstract description 40
- 229910000679 solder Inorganic materials 0.000 claims description 23
- 239000004020 conductor Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 15
- 239000000853 adhesive Substances 0.000 claims description 9
- 230000001070 adhesive effect Effects 0.000 claims description 8
- 230000005855 radiation Effects 0.000 claims description 5
- 230000017525 heat dissipation Effects 0.000 claims 4
- 239000000463 material Substances 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000011159 matrix material Substances 0.000 description 11
- 230000002950 deficient Effects 0.000 description 6
- 238000007789 sealing Methods 0.000 description 5
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007306 functionalization reaction Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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Abstract
【解決手段】半導体装置は、基板11上にフリップチップ接続された半導体素子12を有し、基板11と半導体素子12の間にはアンダーフィル樹脂13が充填されている。半導体素子の外周部には接合ランド14が設けられ、基板11全域が樹脂15により封止されている。また、樹脂15上面から接合ランド14に至る開口部16か形成されている。
【選択図】図1
Description
図1(a)はPoPの断面構造の一例である。第1の半導体パッケージ100と第2の半導体パッケージ200が積層接続された構造となっている。本実施の形態では、2層構造の半導体装置であるため、第2の半導体パッケージ200が最上段に配置された半導体パッケージとなる。ここで、第1の半導体パッケージ100は、基板11上にフリップチップ接続された半導体素子12を有し、基板11と半導体素子12の間にはアンダーフィル樹脂13が充填されている。半導体素子12の外周部には接合ランド14が設けられ、半導体素子12形成部を除く基板11全域が樹脂15により封止されている。樹脂15は半導体素子12部を含め基板11全域を覆うように形成されていてもよいが、積層型半導体装置としての薄型化を考慮した場合、図1(a)のように樹脂15は半導体素子12部を除く基板11上に形成し、半導体素子12の裏面は露出させる構成とした方が好ましい。
本実施の形態は、第1の半導体パッケージがワイヤーボンディングにより形成されている点で、第1の実施例と異なる。
本実施の形態は、第1の半導体パッケージ上に第2の半導体パッケージを積層する工程において特徴を有するものである。したがって、他の製造工程は第1の実施の形態、または第2の実施の形態と同様であるため、その説明を省略する。
本実施の形態は、第1の半導体パッケージ上に第2の半導体パッケージを積層する工程において特徴を有するものである。したがって、他の製造工程は第1の実施の形態、または第2の実施の形態と同様であるため、その説明を省略する。
本実施の形態は、第1の半導体パッケージ上に第2の半導体パッケージを積層する工程において特徴を有するものである。したがって、他の製造工程は第1の実施の形態、または第2の実施の形態と同様であるため、その説明を省略する。
12 半導体素子
13 アンダーフィル樹脂
14 接続ランド
15 樹脂
16 開口部
17 ボール電極
18 半田ボール
19 導電体(半田バンプ)
20 マトリクス基板
21 不良部位
22 スクリーンマスク
23 半田ペースト
24 スキージ
25 熱硬化接着材剤
26 放熱ペースト
27 接続不良部
100 第1の半導体パッケージ
200 第2の半導体パッケージ
Claims (13)
- 2個以上の半導体パッケージが積層してなる積層型半導体装置であって、
最上段に配置された半導体パッケージ以外の第1の半導体パッケージが、
基板に搭載された半導体素子と前記基板上に形成された樹脂を有し、
前記樹脂上面から前記基板上の接続ランドに至る複数の開口部を有し、
前記基板の裏面に外部接続端子を有し、
さらに前記開口部内に前記第1の半導体パッケージ上に積層される第2の半導体パッケージと接続するための導電体が形成されていることを特徴とする積層型半導体装置。 - 前記開口部に形成されている導電体が半田ペーストであることを特徴とする請求項1に記載の積層型半導体装置。
- 前記第1の半導体パッケージの上面と、
前記第2の半導体パッケージの下面との間に接着剤を有し、
前記半導体パッケージ相互が前記接着剤を介して固着されていることを特徴とする請求項1に記載の積層型半導体装置。 - 前記第1の半導体パッケージの半導体素子がフリップチップ接続されている積層型半導体装置において、
前記半導体素子の裏面と前記第2の半導体パッケージの下面の間に放熱機能を有する膜が形成されていることを特徴とする請求項1に記載の積層型半導体装置。 - 前記膜が放熱ペーストであることを特徴とする請求項4に記載の積層型半導体装置。
- 2個以上の半導体パッケージを積層する積層型の半導体装置の製造方法であって、
最上段に配置される半導体パッケージ以外の第1の半導体パッケージが
接続ランドを有する基板上に半導体素子を搭載する工程と、
前記基板上に樹脂を形成する工程と、
前記樹脂上面から前記接続ランドに至る複数の開口部を形成する工程と、
前記基板の裏面に外部接続端子を形成する工程と
前記第1の半導体パッケージ上に第2の半導体パッケージを積層接続する工程とを含むことを特徴とする積層型半導体装置の製造方法。 - 前記第1の半導体パッケージ上に第2の半導体パッケージを積層接続する工程において、
前記第2の半導体パッケージの裏面に形成された導電体を前記第2の半導体パッケージの開口部に適合させる工程を含むことを特徴とする請求項6に記載の積層型半導体装置の製造方法。 - 前記第1の半導体パッケージ上に第2の半導体パッケージを積層接続する工程において、
前記開口部に導電体を充填する工程を含むことを特徴とする請求項6に記載の積層型半導体装置の製造方法。 - 前記開口部に充填される導電体が半田ペーストであることを特徴とする請求項8に記載の積層型半導体装置の製造方法。
- 前記第1の半導体パッケージ上に第2の半導体パッケージを積層接続する工程において、
第1の半導体パッケージの上面と第2の半導体パッケージの下面を接着剤により固着する工程を含むことを特徴とする請求項6乃至9のいずれかに記載の積層型半導体装置の製造方法。 - 前記第1の半導体パッケージ上に第2の半導体パッケージを積層接続する工程において、
前記接着材を前記第2の半導体パッケージ裏面の導電体が形成されている領域以外に塗布する工程を含むことを特徴とする請求項10に記載の積層型半導体装置の製造方法。 - 前記第1の半導体パッケージ上に第2の半導体パッケージを積層接続する工程において、
フリップチップ接続された半導体素子の裏面に放熱機能を有する膜を形成する工程を含むことを特徴とする請求項6乃至11のいずれかに記載の積層型半導体装置の製造方法。 - 前記放熱機能を有する膜が放熱ペーストであることを特徴とする請求項12に記載の半導体装置の製造方法。
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