JP2008141109A - Wiring board, and its manufacturing method - Google Patents

Wiring board, and its manufacturing method Download PDF

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JP2008141109A
JP2008141109A JP2006328180A JP2006328180A JP2008141109A JP 2008141109 A JP2008141109 A JP 2008141109A JP 2006328180 A JP2006328180 A JP 2006328180A JP 2006328180 A JP2006328180 A JP 2006328180A JP 2008141109 A JP2008141109 A JP 2008141109A
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resist layer
wiring
conductive protrusion
solder resist
electronic component
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JP5091469B2 (en
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Koichi Osumi
孝一 大隅
Hiroichi Yamada
博一 山田
Yoshitaka Shiga
美隆 志賀
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Kyocera SLC Technologies Corp
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Kyocera SLC Technologies Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board wherein electric insulation reliability between wiring patterns for flip-chip connection is excellent, a conductive projection and a conductive bump can be connected with high reliability, the filling property of a filling resin is excellent, and the generation of voids is suppressed. <P>SOLUTION: For the wiring board 10, an insulating layer 4 and a wiring conductor 5 are alternately laminated, and the wiring conductor 5 for electronic component connection is formed at a part on the insulating layer 4 of the outmost layer. On the wiring conductor 5, a plurality of belt-like first wiring pattern parts 5A with a first connection part 5a where a first electronic component E1 is flip-chip connected and a plurality of second wiring pattern parts 5B with a second connection part 5b where a second electronic component E2 is solder-ball connected are provided side by side respectively. The conductive projection 12 is formed by a width matched with the width of the first connection part 5a on the first connection part 5a, and a solder resist layer 6 for exposing the conductive projection 12 and the upper surface of the second connection part 5B is attached on the wiring conductor 5 and on the insulating layer 4 of the outermost layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は配線基板およびその製造方法に関し、より詳細には、例えばペリフェラル型の半導体集積回路素子等の第一電子部品をフリップチップ接続により搭載するとともに、さらにその上に別の第二電子部品を半田ボール接続またはワイヤボンド接続により搭載するのに好適な配線基板およびその製造方法に関する。   The present invention relates to a wiring board and a method for manufacturing the same, and more specifically, for example, a first electronic component such as a peripheral type semiconductor integrated circuit element is mounted by flip chip connection, and another second electronic component is further provided thereon. The present invention relates to a wiring board suitable for mounting by solder ball connection or wire bond connection and a method for manufacturing the same.

従来から、電子部品である半導体集積回路素子として、多数の電極端子を、その一方の主面の外周に沿って配設した、いわゆるペリフェラル型の半導体集積回路素子がある。
このような半導体集積回路素子を配線基板に搭載する方法として、フリップチップ接続により接続する方法がある。フリップチップ接続とは、配線基板上に設けた電子部品接続用の配線導体の一部を電子部品の電極端子の配置に対応した並びに露出させ、この電子部品接続用の配線導体の露出部と前記電子部品の電極端子とを対向させ、これらを半田や金等からなる導電バンプを介して電気的に接続する方法である。
また、近時はこのようなフリップチップ接続により第一電子部品を配線基板上に搭載し、さらにその上に別の第二電子部品を半田ボール接続またはワイヤボンド接続により搭載して、配線基板への電子部品の搭載密度を高めることが行われている。 2. Description of the Related Art Conventionally, as a semiconductor integrated circuit element that is an electronic component, there is a so-called peripheral type semiconductor integrated circuit element in which a large number of electrode terminals are arranged along the outer periphery of one main surface thereof.
As a method of mounting such a semiconductor integrated circuit element on a wiring board, there is a method of connecting by flip chip connection. The flip-chip connection means that a part of the wiring conductor for connecting the electronic component provided on the wiring board is exposed corresponding to the arrangement of the electrode terminals of the electronic component, and the exposed portion of the wiring conductor for connecting the electronic component and the above-mentioned In this method, the electrode terminals of the electronic component are opposed to each other, and these are electrically connected via conductive bumps made of solder, gold or the like.
Recently, the first electronic component is mounted on the wiring board by such flip-chip connection, and another second electronic component is mounted thereon by solder ball connection or wire bond connection to the wiring board. Increasing the mounting density of electronic components.

図１１は、第一電子部品としてのペリフェラル型の半導体集積回路素子をフリップチップ接続により搭載し、さらにその上に第二電子部品しての半導体素子搭載基板を半田ボール接続した従来の配線基板の一例を示す概略断面図であり、図１２は、図１１の配線基板を示す平面図である。   FIG. 11 shows a conventional wiring substrate in which a peripheral type semiconductor integrated circuit element as a first electronic component is mounted by flip-chip connection, and a semiconductor element mounting substrate as a second electronic component is further soldered to the substrate. It is a schematic sectional drawing which shows an example, and FIG. 12 is a top view which shows the wiring board of FIG.

図１１に示すように、従来の配線基板１１０は、上面から下面にかけてコア用の配線導体１０２が配設されたコア用の絶縁基板１０３の上下面に、複数のビルドアップ用の絶縁層１０４とビルドアップ用の配線導体１０５とが交互に積層され、さらに、その最表面には保護用のソルダーレジスト層１０６が被着されている。   As shown in FIG. 11, the conventional wiring board 110 includes a plurality of build-up insulating layers 104 on the upper and lower surfaces of the core insulating board 103 in which the core wiring conductors 102 are disposed from the upper surface to the lower surface. Build-up wiring conductors 105 are alternately laminated, and a protective solder resist layer 106 is deposited on the outermost surface.

コア用の絶縁基板１０３の上面から下面にかけては複数のスルーホール１０７が形成されており、絶縁基板１０３の上下面およびスルーホール１０７の内面にはコア用の配線導体１０２が被着され、スルーホール１０７の内部には埋め込み樹脂１０８が充填されている。ビルドアップ用の絶縁層１０４には、それぞれに複数のビアホール１０９が形成されており、各絶縁層１０４の表面およびビアホール１０９の内面には、ビルドアップ用の配線導体１０５が被着形成されている。
この配線導体１０５のうち、配線基板１１０の上面側における最外層の絶縁層１０４上に被着された一部は、第一電子部品としての半導体集積回路素子Ｅ１の電極端子に導電バンプＢ１を介してフリップチップ接続により電気的に接続される第一接続部１０５ａを有する第一配線パターン部１０５Ａであり、この第一配線パターン部１０５Ａは複数並んで帯状に形成されている。さらに、配線導体１０５のうち、配線基板１１０の上面側における最外層の絶縁層１０４上に被着された他の一部は、第二電子部品としての半導体素子搭載基板Ｅ２の電極端子に半田ボールＢ２を介して半田ボール接続により電気的に接続される第二接続部１０５ｂを有する第二配線パターン部１０５Ｂであり、この第二配線パターン部１０５Ｂは複数並んで形成されている。そして、これら第一配線パターン部１０５Ａおよび第二配線パターン部１０５Ｂのうち、第一接続部１０５ａおよび第二接続部１０５ｂがソルダーレジスト層１０６から露出しており、第一接続部１０５ａに半導体集積回路素子Ｅ１の電極端子が半田や金等から成る導電バンプＢ１を介して電気的に接続され、第二接続部１０５ｂに半導体素子搭載基板Ｅ２の電極端子が半田ボールＢ２を介して電気的に接続される。
さらに、配線基板１１０の下面側における最外層の絶縁層１０４上に被着された一部は、外部電気回路基板の配線導体に電気的に接続される外部接続用の第三接続部１０５ｃを有する第三配線パターン部１０５Ｃであり、この第三配線パターン部１０５Ｃは複数並んで形成されている。この第三配線パターン部１０５Ｃのうち、第三接続部１０５ｃがソルダーレジスト層１０６から露出しており、第三接続部１０５ｃに、外部電気回路基板の配線導体が半田ボールＢ３を介して電気的に接続される。 A plurality of through holes 107 are formed from the upper surface to the lower surface of the core insulating substrate 103, and the core wiring conductor 102 is attached to the upper and lower surfaces of the insulating substrate 103 and the inner surface of the through hole 107. An embedding resin 108 is filled in the inside 107. A plurality of via holes 109 are formed in each of the build-up insulating layers 104, and a build-up wiring conductor 105 is formed on the surface of each insulating layer 104 and the inner surface of the via holes 109. .
A part of the wiring conductor 105 deposited on the outermost insulating layer 104 on the upper surface side of the wiring substrate 110 is connected to the electrode terminal of the semiconductor integrated circuit element E1 as the first electronic component via the conductive bump B1. A first wiring pattern portion 105A having a first connection portion 105a that is electrically connected by flip-chip connection, and a plurality of the first wiring pattern portions 105A are formed side by side. Further, the other part of the wiring conductor 105 deposited on the outermost insulating layer 104 on the upper surface side of the wiring substrate 110 is solder balls on the electrode terminals of the semiconductor element mounting substrate E2 as the second electronic component. A second wiring pattern portion 105B having a second connection portion 105b electrically connected by solder ball connection via B2, and a plurality of the second wiring pattern portions 105B are formed side by side. Of the first wiring pattern portion 105A and the second wiring pattern portion 105B, the first connection portion 105a and the second connection portion 105b are exposed from the solder resist layer 106, and a semiconductor integrated circuit is connected to the first connection portion 105a. The electrode terminal of the element E1 is electrically connected via a conductive bump B1 made of solder, gold or the like, and the electrode terminal of the semiconductor element mounting substrate E2 is electrically connected to the second connection portion 105b via a solder ball B2. The
Further, a part of the lower surface side of the wiring board 110 that is deposited on the outermost insulating layer 104 has a third connection portion 105c for external connection that is electrically connected to the wiring conductor of the external electric circuit board. This is a third wiring pattern portion 105C, and a plurality of the third wiring pattern portions 105C are formed side by side. Of the third wiring pattern portion 105C, the third connection portion 105c is exposed from the solder resist layer 106, and the wiring conductor of the external electric circuit board is electrically connected to the third connection portion 105c via the solder ball B3. Connected.

ソルダーレジスト層１０６は、最外層の配線導体１０５を保護するとともに、第一接続部１０５ａおよび第二接続部１０５ｂや外部接続用の第三接続部１０５ｃ部を画定する。このようなソルダーレジスト層１０６は、感光性を有する熱硬化性樹脂ペーストまたはフィルムを配線導体１０５が形成された最外層の絶縁層１０４上に積層したのち、電子部品接続用の第一接続部１０５ａおよび第二接続部１０５ｂや外部接続用の第三接続部１０５ｃを露出させる開口を有するように露光および現像し、硬化させることにより形成される。このため、電子部品接続用の第一接続部１０５ａおよび第二接続部１０５ｂは、ソルダーレジスト層１０６の表面から凹んで位置することになる。
なお、図１２に示すように、上面側のソルダーレジスト層１０６は、第一接続部１０５ａを露出させるスリット状の開口および第二接続部１０５ｂを露出させる円形状の開口を有している。 The solder resist layer 106 protects the outermost wiring conductor 105 and defines the first connection portion 105a, the second connection portion 105b, and the third connection portion 105c for external connection. Such a solder resist layer 106 is formed by laminating a thermosetting resin paste or film having photosensitivity on the outermost insulating layer 104 on which the wiring conductor 105 is formed, and then the first connection portion 105a for connecting an electronic component. In addition, it is formed by exposing, developing and curing so as to have an opening for exposing the second connection portion 105b and the third connection portion 105c for external connection. For this reason, the first connection part 105 a and the second connection part 105 b for connecting the electronic components are located recessed from the surface of the solder resist layer 106.
As shown in FIG. 12, the solder resist layer 106 on the upper surface side has a slit-like opening that exposes the first connecting portion 105a and a circular opening that exposes the second connecting portion 105b.

そして、半導体集積回路素子Ｅ１の電極端子と第一接続部１０５ａとを導電バンプＢ１を介して電気的に接続した後、半導体集積回路素子Ｅ１と配線基板１１０との間の隙間にエポキシ樹脂等の熱硬化性樹脂から成るアンダーフィルと呼ばれる充填樹脂Ｕ１を充填し、半導体集積回路素子Ｅ１が配線基板１１０上に実装される。さらに、その上に半導体素子搭載基板Ｅ２の電極端子と第二接続部１０５ｂとを半田ボールＢ２を介して電気的に接続することにより半導体素子搭載基板Ｅ２が配線基板１１０上に実装され、これにより配線基板１１０上に複数の電子部品が高密度に実装されることとなる。   Then, after electrically connecting the electrode terminal of the semiconductor integrated circuit element E1 and the first connection portion 105a via the conductive bump B1, the gap between the semiconductor integrated circuit element E1 and the wiring substrate 110 is made of epoxy resin or the like. Filling resin U <b> 1 called underfill made of thermosetting resin is filled, and semiconductor integrated circuit element E <b> 1 is mounted on wiring substrate 110. Furthermore, the semiconductor element mounting board E2 is mounted on the wiring board 110 by electrically connecting the electrode terminal of the semiconductor element mounting board E2 and the second connection portion 105b thereon via the solder ball B2. A plurality of electronic components are mounted on the wiring board 110 with high density.

ところが近時、第一電子部品である半導体集積回路素子Ｅ１は、その高集積度化が急激に進み、半導体集積回路素子Ｅ１における電極端子のピッチは１００μｍ以下と狭ピッチになってきている。これに伴い、この半導体集積回路素子Ｅ１の電極端子がフリップチップ接続される第一接続部１０５ａの幅も狭くなってきている（例えば５０μｍ以下）。第一接続部１０５ａの幅が狭くなると、この第一接続部１０５ａに形成される導電バンプＢ１も小さなものにならざるを得ず、この小さな導電バンプＢ１を介して半導体集積回路素子Ｅ１を実装した場合には、半導体集積回路素子Ｅ１とソルダーレジスト層１０６との間の隙間が狭くなるという問題がある（例えば４５μｍ以下）。   Recently, however, the semiconductor integrated circuit element E1, which is the first electronic component, has rapidly increased in the degree of integration, and the pitch of the electrode terminals in the semiconductor integrated circuit element E1 has become narrower than 100 μm. Along with this, the width of the first connection portion 105a to which the electrode terminal of the semiconductor integrated circuit element E1 is flip-chip connected is also becoming narrower (for example, 50 μm or less). When the width of the first connection portion 105a becomes narrower, the conductive bump B1 formed on the first connection portion 105a has to be small, and the semiconductor integrated circuit element E1 is mounted via the small conductive bump B1. In this case, there is a problem that the gap between the semiconductor integrated circuit element E1 and the solder resist layer 106 becomes narrow (for example, 45 μm or less).

前記隙間が狭くなると、この隙間内への充填樹脂Ｕ１の充填性が低下すると共に、充填された充填樹脂Ｕ１中にボイドが発生しやすくなる。ボイドの発生は、半導体集積回路素子Ｅ１が実装された後の配線基板１１０を外部電気回路基板に接続する際の熱や半導体集積回路素子Ｅ１が作動時に発生する熱、あるいは外部環境からの熱等が加えられた際に充填樹脂Ｕ１におけるクラック発生の起点となり、このクラックにより、半導体集積回路素子Ｅ１に対する耐湿性が低下したり、そのクラックが配線基板１１０にまで進行し、ビルドアップ用の配線導体１０５が断線したりする恐れがある。   When the gap is narrowed, the filling property of the filling resin U1 into the gap is lowered, and voids are easily generated in the filled filling resin U1. The generation of voids includes heat when connecting the wiring board 110 after the semiconductor integrated circuit element E1 is mounted to the external electric circuit board, heat generated when the semiconductor integrated circuit element E1 is operated, heat from the external environment, and the like. Is applied as a starting point of crack generation in the filling resin U1, and the crack reduces moisture resistance with respect to the semiconductor integrated circuit element E1, or the crack progresses to the wiring substrate 110, and the wiring conductor for build-up. There is a risk that 105 may be disconnected.

半導体集積回路素子Ｅ１とソルダーレジスト層１０６との間の隙間を広くする方法として、ソルダーレジスト層１０６から露出した第一接続部１０５ａ上にめっきで導電突起を形成することにより、導電突起とソルダーレジスト層１０６とを実質的に同一の高さにする方法がある。この方法によると、前記導電突起上に導電バンプＢ１を形成するので、前記導電突起が、導電バンプＢ１を少量の半田等で十分な高さとするための下地部材として機能すると共に、バンプＢ１の高さに相当する隙間を確保できるようになり、充填樹脂Ｕ１の充填性に優れ、その結果、ボイドの発生が抑制されるとともに、半導体集積回路素子Ｅ１が実装された後の配線基板１１０を外部電気回路基板に接続する際の熱や半導体集積回路素子Ｅ１が作動時に発生する熱、あるいは外部環境からの熱等が加えられた際におけるクラックの発生が抑制される。
なお、ソルダーレジスト層１０６から露出した第一接続部１０５ａ上に上述の導電突起を形成する場合、先ず上面側における最外層の絶縁層１０４の表面に、配線導体１０５（第一接続部１０５ａを有する複数並んだ帯状の第一配線パターン部１０５Ａを含む）を形成した後、その上に、第一配線パターン部１０５Ａの各パターンの幅よりも若干狭い幅の第一の開口を前記第一接続部１０５ａに対応する位置に有する第一のレジスト層を形成する。次に、前記第一の開口内に露出する第一接続部１０５ａ上および第一のレジスト層の表面に電解めっき用の下地金属層を無電解めっきにより形成する。次に、前記下地金属層上に前記第一の開口に対応する第二の開口を有する第二のレジスト層を形成した後、この第二の開口内に露出する下地金属層上に電解めっきにより前記導電突起を形成する。そして、次に、前記第二のレジスト層と、第一のレジスト層上の下地金属層と、第一のレジスト層とを除去した後、最外層の絶縁層１０４上および配線導体１０５上に前記導電突起の上面を露出させるようにしてソルダーレジスト層１０６を形成する方法が採用されている（特許文献１参照）。 As a method of widening the gap between the semiconductor integrated circuit element E1 and the solder resist layer 106, the conductive protrusion and the solder resist are formed by forming conductive protrusions by plating on the first connection portion 105a exposed from the solder resist layer 106. There is a method of making the layer 106 substantially the same height. According to this method, since the conductive bump B1 is formed on the conductive protrusion, the conductive protrusion functions as a base member for making the conductive bump B1 sufficiently high with a small amount of solder and the like. As a result, the filling resin U1 is excellent in filling property, and as a result, generation of voids is suppressed, and the wiring board 110 after the semiconductor integrated circuit element E1 is mounted is connected to the external electric circuit. Occurrence of cracks when heat applied to the circuit board, heat generated when the semiconductor integrated circuit element E1 operates, heat from the external environment, or the like is suppressed.
When the above-described conductive protrusion is formed on the first connection portion 105a exposed from the solder resist layer 106, first, the wiring conductor 105 (having the first connection portion 105a is formed on the surface of the outermost insulating layer 104 on the upper surface side. A plurality of strip-shaped first wiring pattern portions 105A are formed), and a first opening having a width slightly narrower than the width of each pattern of the first wiring pattern portion 105A is formed thereon. A first resist layer having a position corresponding to 105a is formed. Next, a base metal layer for electrolytic plating is formed by electroless plating on the first connection portion 105a exposed in the first opening and on the surface of the first resist layer. Next, after forming a second resist layer having a second opening corresponding to the first opening on the base metal layer, electrolytic plating is performed on the base metal layer exposed in the second opening. The conductive protrusion is formed. Then, after removing the second resist layer, the base metal layer on the first resist layer, and the first resist layer, the outermost insulating layer 104 and the wiring conductor 105 are placed on the wiring conductor 105. A method of forming the solder resist layer 106 so as to expose the upper surface of the conductive protrusion is employed (see Patent Document 1).

しかしながら、上述の方法で第一接続部１０５ａ上に導電突起を形成する場合、前記第一の開口および第二の開口は第一接続部１０５ａの幅よりも若干狭い幅になるので、必然的に導電突起の幅は第一接続部１０５ａの幅よりも狭いものとなり、第一接続部１０５ａ自体の幅が狭い場合、その上に十分な幅の導電突起を設けることが困難になるのである。また、前記第一のレジスト層に第一の開口を設ける際および第二のレジスト層に第二の開口を設ける際に、これらの間に生じる位置合わせの誤差に起因して、第一接続部１０５ａと第一の開口との間および第一の開口と第二の開口との間に多少のずれが発生する。そして、第一接続部１０５ａの幅が狭い場合、その第一接続部１０５ａ上に前記導電突起を所定の幅および形状で位置精度良く設けることができず、導電突起が第一接続部１０５ａからはみ出てしまったり、導電突起の断面形状が歪なものとなったりして、隣接する第一接続部１０５ａ間での電気的な絶縁信頼性が低下したり、導電突起と導電バンプＢ１との続信頼性が低下したりする。   However, when the conductive protrusion is formed on the first connection portion 105a by the above-described method, the first opening and the second opening are slightly narrower than the width of the first connection portion 105a. The width of the conductive protrusion is narrower than the width of the first connection portion 105a. When the width of the first connection portion 105a itself is narrow, it is difficult to provide a conductive protrusion having a sufficient width thereon. Further, when the first opening is provided in the first resist layer and when the second opening is provided in the second resist layer, the first connection portion is caused by an alignment error generated between them. Some deviation occurs between 105a and the first opening and between the first opening and the second opening. When the width of the first connecting portion 105a is narrow, the conductive protrusion cannot be provided on the first connecting portion 105a with a predetermined width and shape with high positional accuracy, and the conductive protrusion protrudes from the first connecting portion 105a. Or the cross-sectional shape of the conductive protrusion becomes distorted, and the electrical insulation reliability between the adjacent first connection portions 105a decreases, or the continuous reliability between the conductive protrusion and the conductive bump B1. The sex will be reduced.

特開２００３−８２２８号公報JP 2003-8228 A

本発明の課題は、第一電子部品がフリップチップ接続され、さらにその上に第二電子部品が半田ボール接続またはワイヤボンド接続される配線基板において、第一電子部品がフリップチップ接続される第一接続部間の電気的絶縁信頼性に優れるとともに、第一接続部上に形成された導電突起と導電バンプとを信頼性高く接続することが可能であり、かつ第一電子部品と配線基板との間に充填される充填樹脂の充填性に優れ、充填樹脂中でのボイドの発生が抑制された高密度実装型の配線基板およびその製造方法を提供することである。   An object of the present invention is to provide a first electronic component in which the first electronic component is flip-chip connected in a wiring board in which the first electronic component is flip-chip connected and the second electronic component is further connected to the solder ball or wire bond. It is excellent in electrical insulation reliability between the connecting parts, and it is possible to connect the conductive protrusions and conductive bumps formed on the first connecting part with high reliability, and between the first electronic component and the wiring board. An object of the present invention is to provide a high-density mounting type wiring board in which the filling resin filled in between is excellent and the generation of voids in the filling resin is suppressed, and a method for manufacturing the same.

本発明者は、上記課題を解決すべく鋭意検討を重ねた結果、所定のレジスト層を用いて最外層の絶縁層の表面に第一電子部品がフリップチップ接続される第一接続部を有する電子部品接続用の配線導体を形成し、さらにこの配線導体の前記第一接続部の表面に導電突起を形成し、次いで、前記レジスト層を除去した後に前記絶縁層および配線導体の表面にソルダーレジスト層を被着することにより、前記導電突起を第一接続部の表面に十分な幅および形状で確実に形成することができ、その結果、隣接する第一接続部間の電気的絶縁信頼性に優れるとともに、前記導電突起と第一接続部上の導電突起に接続される導電バンプとの接続信頼性にも優れることと、また、導電突起とソルダーレジスト層との高低差が小さくなるので、充填樹脂の充填性に優れ、かつボイドの発生が抑制され、電極端子が狭ピッチな半導体集積回路素子を微小な導電バンプを介してフリップチップ搭載することができる配線基板が得られるという新たな知見を見出し、本発明を完成するに至った。   As a result of intensive studies to solve the above problems, the present inventor has an electronic device having a first connection portion in which a first electronic component is flip-chip connected to the surface of the outermost insulating layer using a predetermined resist layer. Forming a wiring conductor for connecting components, further forming a conductive protrusion on the surface of the first connecting portion of the wiring conductor, and then removing the resist layer and then a solder resist layer on the surfaces of the insulating layer and the wiring conductor By adhering, the conductive protrusion can be reliably formed on the surface of the first connection part with a sufficient width and shape, and as a result, the electrical insulation reliability between the adjacent first connection parts is excellent. In addition, it is excellent in connection reliability between the conductive protrusion and the conductive bump connected to the conductive protrusion on the first connection portion, and the difference in height between the conductive protrusion and the solder resist layer is reduced. Fulfillment of New knowledge that a wiring board capable of flip-chip mounting semiconductor integrated circuit elements with excellent pitch characteristics, with reduced generation of voids, and electrode terminals with a narrow pitch through minute conductive bumps has been found. The invention has been completed.

すなわち、本発明における配線基板およびその製造方法は、以下の構成からなる。
（１）絶縁層と配線導体とが交互に積層され、最外層の絶縁層上の一部に電子部品接続用の配線導体が形成されており、該電子部品接続用の配線導体には、第一電子部品がフリップチップ接続される第一接続部を有する第一配線パターン部が帯状に複数並んで設けられているとともに、第二電子部品が半田ボール接続またはワイヤボンド接続される第二接続部を有する第二配線パターン部が複数並んで設けられ、かつ、前記第一接続部上には導電突起が第一接続部の幅と一致する幅で形成されており、さらに、前記電子部品接続用の配線導体上および該電子部品接続用の配線導体が形成された部分以外の最外層の絶縁層上には前記導電突起の上面および前記第二接続部の上面を露出させるソルダーレジスト層が被着されていることを特徴とする配線基板。
（２）前記導電突起の上面と前記ソルダーレジスト層の上面とが実質的に同じ高さである、前記（１）記載の配線基板。
（３）前記導電突起の上面と前記ソルダーレジスト層の上面との高低差が１０μｍ以下であるとともに、前記導電突起の上面と前記ソルダーレジスト層の上面との段差が傾斜面となっている、前記（１）記載の配線基板。
（４）前記導電突起の長さが該導電突起の幅よりも長い、前記（１）〜（３）のいずれかに記載の配線基板。
（５）絶縁層と配線導体とを交互に積層し、最外層の絶縁層上の一部には電子部品接続用の配線導体を形成し、該電子部品接続用の配線導体の形成に際しては、第一電子部品がフリップチップ接続される第一接続部を有する第一配線パターン部を帯状に複数並んで設けるとともに、第二電子部品が半田ボール接続またはワイヤボンド接続される第二接続部を有する第二配線パターン部を複数並んで設けるようにし、かつ、前記第一接続部上に導電突起を第一接続部の幅と一致する幅で形成し、さらに、前記電子部品接続用の配線導体上および該電子部品接続用の配線導体が形成された部分以外の最外層の絶縁層上に前記導電突起の上面および前記第二接続部の上面を露出させるソルダーレジスト層を被着する配線基板の製造方法であって、前記最外層の絶縁層上に、該絶縁層上の全面を覆う電解めっき用の下地金属層を形成する工程と、次に前記下地金属層上に前記電子部品接続用の配線導体に対応する形状の第一開口を有する第一レジスト層を形成する工程と、次に前記第一開口内の前記下地金属層上に電解めっきにより前記電子部品接続用の配線導体を形成する工程と、次に前記第一レジスト層および前記電子部品接続用の配線導体の上に、前記第一接続部に対応する位置で前記第一配線パターン部を横切る第二開口を有する第二レジスト層を形成する工程と、次に前記第一開口および第二開口で囲まれた前記第一配線パターン部上に電解めっきにより前記導電突起を前記第一開口で画定される幅および第二開口で画定される長さで形成する工程と、次に前記第一レジスト層および第二レジスト層を除去する工程と、次に前記電子部品接続用の配線導体が形成された部分以外の前記下地金属層を除去する工程と、次に前記電子部品接続用の配線導体上および該電子部品接続用の配線導体が形成された部分以外の最外層の絶縁層上に、前記導電突起の上面および前記第二接続部の上面を露出させるソルダーレジスト層を被着する工程とを含むことを特徴とする配線基板の製造方法。
（６）前記導電突起の上面と前記ソルダーレジスト層の上面とを実質的に同じ高さに形成する、前記（５）記載の配線基板の製造方法。
（７）前記導電突起の上面と前記ソルダーレジスト層の上面とを高低差が１０μｍ以下となるように形成するとともに、前記導電突起の上面と前記ソルダーレジスト層の上面との段差を傾斜面に形成する、前記（５）記載の配線基板の製造方法。
（８）前記導電突起の前記長さを該導電突起の幅よりも長く形成する、前記（５）〜（７）のいずれかに記載の配線基板の製造方法。
（９）前記ソルダーレジスト層を被着する工程は、ソルダーレジスト層用の感光性樹脂で前記導電突起を含む前記電子部品接続用の配線導体および該配線導体が形成された部分以外の最外層の絶縁層の全面を被覆する工程と、被覆した前記感光性樹脂を露光および現像処理して前記ソルダーレジスト層用の樹脂層に前記第二接続部の上面を露出させる第三開口を形成する工程と、前記ソルダーレジスト層用の樹脂を前記導電突起の上面が露出するまで研磨する工程とを含んでいる、前記（５）〜（８）のいずれかに記載の配線基板の製造方法。
（１０）前記ソルダーレジスト層用の樹脂層を前記導電突起の上面が露出するまで研磨する工程は、前記ソルダーレジスト層用の樹脂層の前記導電突起に対応する部位のみを選択的に研磨する工程を含む、前記（９）の配線基板の製造方法。
（１１）前記ソルダーレジスト層用の樹脂層の前記導電突起に対応する部位のみを選択的に研磨する工程は、前記ソルダーレジスト層用の樹脂層上に前記導電突起に対応する部位のみを露出させる第四開口を有するマスクを配置するとともに、該第四開口を介して前記ソルダーレジスト層用の樹脂層に砥粒を吹き付けることにより行われる、前記（１０）記載の配線基板の製造方法。 That is, the wiring board and the manufacturing method thereof according to the present invention have the following configurations.
(1) Insulating layers and wiring conductors are alternately stacked, and wiring conductors for connecting electronic components are formed on a part of the outermost insulating layer. The wiring conductors for connecting electronic components include: A second connection part in which a plurality of first wiring pattern parts having a first connection part to which one electronic component is flip-chip connected is provided in a strip shape, and a second electronic part is connected by solder ball connection or wire bond connection A plurality of second wiring pattern portions having a width, and conductive protrusions are formed on the first connection portion with a width matching the width of the first connection portion, and further for connecting the electronic component A solder resist layer that exposes the upper surface of the conductive protrusion and the upper surface of the second connection portion is deposited on the wiring conductor and the outermost insulating layer other than the portion where the wiring conductor for connecting the electronic component is formed. It is characterized by being Wiring board.
(2) The wiring board according to (1), wherein an upper surface of the conductive protrusion and an upper surface of the solder resist layer are substantially the same height.
(3) The difference in height between the upper surface of the conductive protrusion and the upper surface of the solder resist layer is 10 μm or less, and the step between the upper surface of the conductive protrusion and the upper surface of the solder resist layer is an inclined surface, (1) The wiring board according to the description.
(4) The wiring board according to any one of (1) to (3), wherein a length of the conductive protrusion is longer than a width of the conductive protrusion.
(5) Insulating layers and wiring conductors are alternately stacked, and a wiring conductor for connecting an electronic component is formed on a part of the outermost insulating layer, and when the wiring conductor for connecting the electronic component is formed, A plurality of first wiring pattern portions each having a first connection portion to which the first electronic component is flip-chip connected are provided in a strip shape, and the second electronic component has a second connection portion to which solder ball connection or wire bond connection is made. A plurality of second wiring pattern portions are provided side by side, and a conductive protrusion is formed on the first connection portion with a width that matches the width of the first connection portion, and further on the wiring conductor for connecting the electronic component And a wiring board for depositing a solder resist layer that exposes the upper surface of the conductive protrusion and the upper surface of the second connection portion on the outermost insulating layer other than the portion where the wiring conductor for connecting the electronic component is formed Before the method A step of forming a base metal layer for electrolytic plating covering the entire surface of the insulating layer on the outermost insulating layer, and then a shape corresponding to the wiring conductor for connecting the electronic component on the base metal layer Forming a first resist layer having a first opening; next, forming a wiring conductor for connecting the electronic component by electrolytic plating on the base metal layer in the first opening; and Forming a second resist layer having a second opening across the first wiring pattern portion at a position corresponding to the first connection portion on one resist layer and the wiring conductor for connecting the electronic component; and On the first wiring pattern portion surrounded by the first opening and the second opening, the conductive protrusion is formed by electrolytic plating with a width defined by the first opening and a length defined by the second opening. Process, and then the first resist layer And removing the second resist layer; next, removing the base metal layer other than the portion where the wiring conductor for connecting the electronic component is formed; and then on the wiring conductor for connecting the electronic component and Depositing a solder resist layer that exposes the upper surface of the conductive protrusion and the upper surface of the second connection portion on the outermost insulating layer other than the portion where the wiring conductor for connecting the electronic component is formed. A method for manufacturing a wiring board.
(6) The method for manufacturing a wiring board according to (5), wherein the upper surface of the conductive protrusion and the upper surface of the solder resist layer are formed at substantially the same height.
(7) The upper surface of the conductive protrusion and the upper surface of the solder resist layer are formed to have a height difference of 10 μm or less, and a step between the upper surface of the conductive protrusion and the upper surface of the solder resist layer is formed on an inclined surface. The method for manufacturing a wiring board according to (5).
(8) The method for manufacturing a wiring board according to any one of (5) to (7), wherein the length of the conductive protrusion is formed longer than the width of the conductive protrusion.
(9) The step of depositing the solder resist layer includes the step of forming the wiring conductor for connecting the electronic component including the conductive protrusions with a photosensitive resin for the solder resist layer and the outermost layer other than the portion where the wiring conductor is formed. A step of covering the entire surface of the insulating layer, and a step of exposing and developing the coated photosensitive resin to form a third opening that exposes the upper surface of the second connection portion in the resin layer for the solder resist layer; The method for manufacturing a wiring board according to any one of (5) to (8), further comprising a step of polishing the resin for the solder resist layer until an upper surface of the conductive protrusion is exposed.
(10) The step of polishing the resin layer for the solder resist layer until the upper surface of the conductive protrusion is exposed is a step of selectively polishing only a portion corresponding to the conductive protrusion of the resin layer for the solder resist layer The method for manufacturing a wiring board according to (9), including:
(11) The step of selectively polishing only the portion corresponding to the conductive protrusion of the resin layer for the solder resist layer exposes only the portion corresponding to the conductive protrusion on the resin layer for the solder resist layer. The method for manufacturing a wiring board according to (10), wherein a mask having a fourth opening is disposed and abrasive grains are sprayed onto the resin layer for the solder resist layer through the fourth opening.

本発明の配線基板によれば、最外層の絶縁層上の一部に電子部品接続用の配線導体が形成されており、該電子部品接続用の配線導体に、第一電子部品がフリップチップ接続される第一接続部を有する第一配線パターン部が帯状に複数並んで設けられているとともに、第二電子部品が半田ボール接続またはワイヤボンド接続される第二接続部を有する第二配線パターン部が複数並んで設けられ、かつ、前記第一接続部上には導電突起が第一接続部の幅と一致する幅で形成されており、さらに、前記電子部品接続用の配線導体上および該電子部品接続用の配線導体が形成された部分以外の最外層の絶縁層上には前記導電突起の上面および前記第二接続部の上面を露出させるソルダーレジスト層が被着されていることにより、前記第一接続部上に十分な幅の導電突起が第一接続部からはみ出すことなく良好な断面形状で形成され、隣接する第一接続部間の電気的絶縁信頼性に優れるとともに、導電突起と第一接続部上の導電突起に接続される導電バンプとの接続信頼性にも優れる、という効果が得られる。また、本発明の配線基板によれば、導電突起とソルダーレジスト層との高低差が小さくなることによって、充填樹脂の充填性に優れるとともに、ボイドの発生が抑制され、電極端子が狭ピッチな第一電子部品を微小な導電バンプを介してフリップチップ搭載することが可能になる。そして、さらにその上に、第二電子部品を通常の半田ボール接続またはワイヤボンド接続により搭載して、高密度実装することができる。
また、本発明の配線基板の製造方法によれば、所定のレジスト層を用いて最外層の絶縁層の表面に第一電子部品がフリップチップ接続される第一接続部を有する電子部品接続用の配線導体を形成し、さらに、この配線導体の前記第一接続部の表面に導電突起を形成し、次いで、前記レジスト層を除去した後に前記絶縁層および配線導体の表面にソルダーレジスト層を被着することにより、前記導電突起を第一接続部の表面に所定の幅および形状で確実に形成することができ、その結果、隣接する第一接続部間の電気的絶縁信頼性に優れるとともに、導電突起と第一接続部上の導電突起に接続される導電バンプとの接続信頼性にも優れた配線基板を得ることができる。また、この配線基板は、導電突起とソルダーレジスト層との高低差が小さいので、充填樹脂の充填性に優れ、かつボイドの発生が抑制され、電極端子が狭ピッチな第一電子部品を微小な導電バンプを介してフリップチップ搭載することができる。そして、さらにその上に、第二電子部品を通常の半田ボール接続またはワイヤボンド接続により搭載して、高密度実装することができる。 According to the wiring board of the present invention, the wiring conductor for connecting the electronic component is formed on a part of the outermost insulating layer, and the first electronic component is flip-chip connected to the wiring conductor for connecting the electronic component. The first wiring pattern portion having the first connection portion is arranged in a plurality of strips, and the second wiring pattern portion has the second connection portion to which the second electronic component is connected by solder ball connection or wire bond connection Are provided side by side, and conductive protrusions are formed on the first connection portion with a width that matches the width of the first connection portion, and on the wiring conductor for connecting the electronic component and the electron A solder resist layer that exposes the upper surface of the conductive protrusion and the upper surface of the second connection portion is deposited on the outermost insulating layer other than the portion where the wiring conductor for connecting components is formed, Ten on the first connection Conductive protrusions of a wide width are formed with a good cross-sectional shape without protruding from the first connection part, and are excellent in electrical insulation reliability between adjacent first connection parts, and the conductive protrusions and conductive protrusions on the first connection part The effect that the connection reliability with the conductive bump connected to is excellent is also obtained. Further, according to the wiring board of the present invention, the difference in height between the conductive protrusion and the solder resist layer is reduced, so that the filling resin is excellent in filling property, the generation of voids is suppressed, and the electrode terminals are narrow pitched. One electronic component can be flip-chip mounted via minute conductive bumps. Further, the second electronic component can be mounted thereon by ordinary solder ball connection or wire bond connection for high-density mounting.
In addition, according to the method for manufacturing a wiring board of the present invention, for connecting an electronic component, the first electronic component is flip-chip connected to the surface of the outermost insulating layer using a predetermined resist layer. Form a wiring conductor, and further form a conductive protrusion on the surface of the first connection portion of the wiring conductor, and then apply a solder resist layer on the insulating layer and the surface of the wiring conductor after removing the resist layer. As a result, the conductive protrusion can be reliably formed on the surface of the first connection portion with a predetermined width and shape. As a result, the electrical insulation reliability between the adjacent first connection portions is excellent, and the conductive A wiring board having excellent connection reliability between the protrusion and the conductive bump connected to the conductive protrusion on the first connection portion can be obtained. In addition, since the wiring board has a small difference in height between the conductive protrusion and the solder resist layer, the filling resin is excellent in filling property, generation of voids is suppressed, and the first electronic component having a narrow pitch of the electrode terminals is made minute. It can be flip-chip mounted via a conductive bump. Further, the second electronic component can be mounted thereon by ordinary solder ball connection or wire bond connection for high-density mounting.

以下、本発明にかかる配線基板およびその製造方法について図面を参照して詳細に説明する。
図１は、第一電子部品としてペリフェラル型の半導体集積回路素子をフリップチップ接続により搭載し、さらにその上に第二電子部品としての半導体素子搭載基板を半田ボール接続により搭載した本発明にかかる配線基板の一例を示す概略断面図であり、図２は、図１の配線基板を示す平面図である。 Hereinafter, a wiring board and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings.
FIG. 1 shows a wiring according to the present invention in which a peripheral type semiconductor integrated circuit element is mounted as a first electronic component by flip chip connection, and a semiconductor element mounting substrate as a second electronic component is mounted thereon by solder ball connection. FIG. 2 is a schematic cross-sectional view showing an example of a substrate, and FIG. 2 is a plan view showing the wiring substrate of FIG.

図１および図２に示すように、本発明にかかる配線基板１０は、上面から下面にかけてコア用の配線導体２が配設されたコア用の絶縁基板３の上下面に、ビルドアップ用の絶縁層４とビルドアップ用の配線導体５とが交互に積層され、さらに、その最表面に保護用のソルダーレジスト層６が被着されて成る。   As shown in FIG. 1 and FIG. 2, the wiring board 10 according to the present invention has a build-up insulation on the upper and lower surfaces of the core insulating substrate 3 in which the core wiring conductors 2 are arranged from the upper surface to the lower surface. Layers 4 and build-up wiring conductors 5 are alternately laminated, and a protective solder resist layer 6 is deposited on the outermost surface.

コア用の絶縁基板３は、厚みが０．０５〜１．５ｍｍ程度であり、例えばガラス繊維束を縦横に織ったガラスクロスにビスマレイミドトリアジン樹脂やエポキシ樹脂等の熱硬化性樹脂を含浸させた電気絶縁材料から成る。絶縁基板３は、配線基板１０のコア部材として機能する。   The core insulating substrate 3 has a thickness of about 0.05 to 1.5 mm. For example, a glass cloth in which a glass fiber bundle is woven vertically and horizontally is impregnated with a thermosetting resin such as a bismaleimide triazine resin or an epoxy resin. Made of electrically insulating material. The insulating substrate 3 functions as a core member of the wiring substrate 10.

コア用の絶縁基板３には、その上面から下面にかけて直径が０．０５〜０．３ｍｍ程度の複数のスルーホール７が形成されており、絶縁基板３の上下面およびスルーホール７の内面には、配線導体２が被着されている。コア用の配線導体２は、絶縁基板３の上下面では、主として銅箔から形成されており、スルーホール７の内面では、無電解銅めっきおよびその上の電解銅めっきから形成されている。   A plurality of through holes 7 having a diameter of about 0.05 to 0.3 mm are formed in the core insulating substrate 3 from the upper surface to the lower surface, and the upper and lower surfaces of the insulating substrate 3 and the inner surface of the through hole 7 are formed on the inner surface of the through hole 7. The wiring conductor 2 is attached. The core wiring conductor 2 is mainly formed of copper foil on the upper and lower surfaces of the insulating substrate 3, and is formed of electroless copper plating and electrolytic copper plating thereon on the inner surface of the through hole 7.

また、スルーホール７の内部には、エポキシ樹脂等の熱硬化性樹脂から成る埋め込み樹脂８が充填されており、絶縁基板３の上下面に形成された配線導体２同士がスルーホール７内の配線導体２を介して電気的に接続されている。   The through hole 7 is filled with an embedded resin 8 made of a thermosetting resin such as an epoxy resin, and the wiring conductors 2 formed on the upper and lower surfaces of the insulating substrate 3 are connected to each other in the through hole 7. It is electrically connected through the conductor 2.

このような絶縁基板３は、ガラス織物に未硬化の熱硬化性樹脂を含浸させたシートの上下面に配線導体２用の銅箔を貼着した後、そのシートを熱硬化させ、これに上面から下面にかけてスルーホール７用のドリル加工を施すことにより作製される。   Such an insulating substrate 3 is obtained by attaching a copper foil for the wiring conductor 2 on the upper and lower surfaces of a sheet in which a glass fabric is impregnated with an uncured thermosetting resin, and then thermally curing the sheet, It is produced by drilling for the through hole 7 from the bottom to the bottom.

配線導体２は、絶縁基板３用の前記シートの上下全面に、厚みが３〜５０μｍ程度の銅箔を上述のように貼着しておくとともに、これらの銅箔および絶縁基板３にスルーホール７を穿孔した後、このスルーホール7の内面および銅箔表面に無電解銅めっきおよび電解銅めっきを順次施し、次いで、スルーホール７内を埋め込み樹脂８で充填した後、この上下面の銅箔および銅めっきをフォトリソグラフィ技術を用いて所定のパターンにエッチング加工することにより、絶縁基板３の上下面およびスルーホール７の内面に形成される。   In the wiring conductor 2, copper foil having a thickness of about 3 to 50 μm is pasted on the entire upper and lower surfaces of the sheet for the insulating substrate 3 as described above, and through holes 7 are formed in these copper foil and the insulating substrate 3. Then, electroless copper plating and electrolytic copper plating are sequentially applied to the inner surface of the through hole 7 and the surface of the copper foil, and then the inside of the through hole 7 is filled with the embedded resin 8. The copper plating is etched into a predetermined pattern using a photolithography technique, so that the upper and lower surfaces of the insulating substrate 3 and the inner surface of the through hole 7 are formed.

埋め込み樹脂８は、スルーホール７を塞ぐことによりスルーホール７の直上および直下にビルドアップ用の絶縁層４を形成可能とするためのものであり、未硬化のペースト状の熱硬化性樹脂をスルーホール７内にスクリーン印刷法により充填し、これを熱硬化させた後、その上下面を略平坦に研磨することにより形成される。   The embedding resin 8 is used to form the insulating layer 4 for buildup directly above and below the through-hole 7 by closing the through-hole 7, and through the uncured pasty thermosetting resin. The hole 7 is formed by filling the hole 7 by a screen printing method, thermally curing it, and then polishing the upper and lower surfaces thereof substantially flatly.

絶縁基板３の上下面に積層されたビルドアップ用の絶縁層４は、それぞれの厚みが２０〜６０μｍ程度であり、絶縁基板３と同様にガラスクロスに熱硬化性樹脂を含浸させた電気絶縁材料や、あるいはエポキシ樹脂等の熱硬化性樹脂に酸化珪素等の無機フィラーを分散させた電気絶縁材料から成る。各絶縁層４には、直径が３０〜１００μｍ程度の複数のビアホール９が形成されている。   The insulating layers 4 for buildup laminated on the upper and lower surfaces of the insulating substrate 3 each have a thickness of about 20 to 60 μm. Similarly to the insulating substrate 3, an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin. Or, it is made of an electrically insulating material in which an inorganic filler such as silicon oxide is dispersed in a thermosetting resin such as an epoxy resin. In each insulating layer 4, a plurality of via holes 9 having a diameter of about 30 to 100 μm are formed.

各絶縁層４の表面およびビアホール９の内面には、無電解銅めっきおよびその上の電解銅めっきから成るビルドアップ用の配線導体５が被着形成されている。そして、絶縁層４を挟んで上層に位置する配線導体５と下層に位置する配線導体５とをビアホール９内の配線導体５を介して電気的に接続することにより、高密度配線が立体的に形成される。   A build-up wiring conductor 5 made of electroless copper plating and electrolytic copper plating thereon is deposited on the surface of each insulating layer 4 and the inner surface of the via hole 9. Then, the wiring conductor 5 located in the upper layer and the wiring conductor 5 located in the lower layer are electrically connected via the wiring conductor 5 in the via hole 9 with the insulating layer 4 interposed therebetween, so that the high-density wiring is three-dimensionally formed. It is formed.

ビルドアップ用の配線導体５のうち、配線基板１０の上面側における最外層の絶縁層４上に被着された一部は、半導体集積回路素子Ｅ１の電極に半田等の導電バンプＢ１および後述する導電突起１２を介して電気的に接続される第一接続部５ａを有する第一配線パターン部５Ａであり、複数並んだ帯状に形成されている。さらに、ビルドアップ用の配線導体５のうち、配線基板１０の上面側における最外層の絶縁層４上に被着された別の一部は、半導体素子搭載基板Ｅ２の電極端子に半田ボールＢ２を介して半田ボール接続により電気的に接続される第二接続部５ｂを有する第二配線パターン部５Ｂであり、複数並んで形成されている。また、配線基板１０の下面側における最外層の絶縁層４上に被着された一部は、外部電気回路基板の配線導体に半田ボールＢ３を介して電気的に接続される外部接続用の第三接続部５ｃを有する第三配線パターン部５Ｃであり、複数並んで形成されている。   A part of the buildup wiring conductor 5 deposited on the outermost insulating layer 4 on the upper surface side of the wiring substrate 10 is electrically conductive bumps B1 such as solder on the electrodes of the semiconductor integrated circuit element E1 and will be described later. A first wiring pattern portion 5A having a first connection portion 5a that is electrically connected via a conductive protrusion 12, and is formed in a plurality of lined strips. Further, another part of the build-up wiring conductor 5 deposited on the outermost insulating layer 4 on the upper surface side of the wiring substrate 10 has solder balls B2 applied to the electrode terminals of the semiconductor element mounting substrate E2. A second wiring pattern portion 5B having a second connection portion 5b electrically connected by solder ball connection, and a plurality of second wiring pattern portions 5B are formed side by side. Also, a part of the lower surface of the wiring board 10 deposited on the outermost insulating layer 4 is electrically connected to the wiring conductor of the external electric circuit board via the solder balls B3. A third wiring pattern portion 5C having three connection portions 5c is formed in a plurality.

このようなビルドアップ用の配線導体５は、セミアディティブ法といわれる方法により形成される。セミアディティブ法は、例えば、ビアホール９が形成されたビルドアップ用の絶縁層４の表面に、電解めっき用の下地金属層を無電解銅めっきにより形成し、その上に配線導体５に対応した開口を有するめっきレジスト層を形成し、次に、下地金属層を給電用の電極として開口から露出する下地金属層上に電解銅めっきを施すことで配線導体５を形成し、めっきレジストを剥離した後、露出する下地金属層をエッチング除去することによって、各配線導体５を電気的に独立させる方法である。
第一配線パターン部５Ａは、半導体集積回路素子Ｅ１の外周部に対応する位置に、半導体集積回路素子Ｅ１の外周辺に対して直角な方向に延びるようにして所定のピッチで帯状に複数並んで設けられている。そして、第一配線パターン部５Ａの半導体集積回路素子Ｅ１の電極端子に対応する位置には、第一接続部５ａが設けられており、該第一接続部５ａの上には導電バンプＢ１と接続される導電突起１２が第一接続部５ａの幅と一致する幅で形成されている。このように、導電突起１２は、第一接続部５ａの幅と一致する幅で形成されているので、第一接続部５ａからはみ出ることがないとともに、導電バンプＢ１と接続するための十分な幅を確保することができる。したがって、本発明の配線基板１０は、隣接する第一接続部５ａ間の電気的絶縁信頼性に優れるとともに、導電突起１２と導電バンプＢ１との接続信頼性に優れる。
なお、導電突起１２は、その長さが該導電突起１２の幅よりも長く（例えば５０μｍ以上長く）形成されている。このように、導電突起１２の長さがその幅よりも長く形成されることにより、例えば、導電突起１２の形成位置が第一配線パターン部５Ａの長さ方向に多少ずれた場合であっても、半導体集積回路素子Ｅ１の電極端子と導電突起１２との位置がずれることなく、両者を導電バンプＢ１を介して正確に接続することができる。
また、第二配線パターン部５Ｂは、半導体集積回路素子Ｅ１を取り囲むようにして一部が前記第一配線パターンに接続された状態で複数並んで設けられている。そして、第二配線パターン部５Ｂの半導体素子搭載基板Ｅ２の電極端子に対応する位置には、円形状の第二接続部５ｂが設けられている。 Such a build-up wiring conductor 5 is formed by a method called a semi-additive method. In the semi-additive method, for example, a base metal layer for electrolytic plating is formed on the surface of the build-up insulating layer 4 in which the via hole 9 is formed by electroless copper plating, and an opening corresponding to the wiring conductor 5 is formed thereon. After forming a wiring resist 5 by performing electrolytic copper plating on the base metal layer exposed from the opening using the base metal layer as an electrode for power feeding, and then peeling off the plating resist This is a method in which each wiring conductor 5 is electrically independent by etching away the exposed base metal layer.
A plurality of first wiring pattern portions 5A are arranged in a strip shape at a predetermined pitch so as to extend in a direction perpendicular to the outer periphery of the semiconductor integrated circuit element E1 at a position corresponding to the outer peripheral portion of the semiconductor integrated circuit element E1. Is provided. A first connection portion 5a is provided at a position corresponding to the electrode terminal of the semiconductor integrated circuit element E1 of the first wiring pattern portion 5A, and connected to the conductive bump B1 on the first connection portion 5a. The conductive protrusions 12 are formed with a width that matches the width of the first connecting portion 5a. Thus, since the conductive protrusion 12 is formed with a width that matches the width of the first connection portion 5a, the conductive protrusion 12 does not protrude from the first connection portion 5a and has a sufficient width for connection with the conductive bump B1. Can be secured. Therefore, the wiring board 10 of the present invention is excellent in the electrical insulation reliability between the adjacent first connection portions 5a, and is excellent in the connection reliability between the conductive protrusion 12 and the conductive bump B1.
The conductive protrusion 12 is formed so that its length is longer than the width of the conductive protrusion 12 (for example, 50 μm or longer). Thus, even if the formation position of the conductive protrusion 12 is slightly shifted in the length direction of the first wiring pattern portion 5A by forming the conductive protrusion 12 longer than its width, for example. The electrode terminals of the semiconductor integrated circuit element E1 and the conductive protrusions 12 can be accurately connected via the conductive bumps B1 without being displaced.
A plurality of second wiring pattern portions 5B are provided side by side so as to surround the semiconductor integrated circuit element E1 and partially connected to the first wiring pattern. A circular second connection portion 5b is provided at a position corresponding to the electrode terminal of the semiconductor element mounting substrate E2 of the second wiring pattern portion 5B.

さらに、配線導体５上および該配線導体５が形成された部分以外の最外層の絶縁層４上には、ソルダーレジスト層６が被着されている。ソルダーレジスト層６は、最外層の配線導体５を熱や外部環境から保護するための保護膜であり、上面側のソルダーレジスト層６は導電突起１２の上面および第二接続部５ｂの上面を露出させるようにして被着されている。また、下面側のソルダーレジスト層６は、外部接続用の第三の接続部５ｃを露出させるようにして被着されている。
そして、本発明の配線基板１０においては、導電突起１２の上面がソルダーレジスト層６の上面と実質的に同じ高さか、それよりも若干低い高さとなっている。このように、導電突起１２の上面がソルダーレジスト層６の上面と実質的に同じ高さか、それよりも若干低い高さとなっていることにより、導電突起１２の上に導電バンプＢ１を介して半導体集積回路素子Ｅ１の電極端子を接続する際に、ソルダーレジスト層６と半導体集積回路素子Ｅ１との間に導電バンプＢ１の高さに相当する隙間が確保され、その隙間に充填樹脂Ｕ１を充填性良く、かつボイドを発生させることなく充填することができる。
なお、導電突起１２の上面がソルダーレジスト層６の上面よりも若干低い高さである場合、その高低差は１０μｍ以下であることが好ましく、さらには、図３に要部拡大断面図で示すように、導電突起１２の上面とソルダーレジスト層６の上面との間の段差が緩やかな傾斜面となっていることが好ましい。このように、導電突起１２の上面とソルダーレジスト層６の上面との間の段差が高低差１０μｍ以下の緩やかな傾斜面となっていることによって、導電突起１２の上面がソルダーレジスト層６の上面よりも若干低い場合であっても、充填樹脂Ｕ１がこの緩やかな傾斜面を伝って半導体集積回路素子Ｅ１と配線基板１０との間の隙間に良好に流れ込み、充填樹脂Ｕ１を充填性良く、かつボイドを発生させることなく充填することができる。
また、第二接続部５ｂの上面は、ソルダーレジスト層６に設けた開口内に露出しており、この開口とで形成される凹部の底面を形成している。これにより、半導体素子搭載基板Ｅ２を配線基板１０上に実装する際に、半導体素子搭載基板Ｅ２の電極端子と第二接続部５ｂとを接続する半田ボールＢ２が第二接続部５ｂ上に良好に位置決めされ、半導体素子搭載基板Ｅ２を配線基板１０上に良好に搭載することが可能になる。
なお、ソルダーレジスト層６から露出する導電突起１２の上面および第二接続部５ｂの上面には、導電突起１２および第二接続部５ｂが酸化腐食するのを防止するとともに、導電バンプＢ１や半田ボールＢ２との接続を良好とするために、ニッケルめっきおよび金めっきを無電解めっき法や電解めっき法により順次被着させておくか、あるいは半田層を被着させておいてもよい。 Further, a solder resist layer 6 is deposited on the wiring conductor 5 and on the outermost insulating layer 4 other than the portion where the wiring conductor 5 is formed. The solder resist layer 6 is a protective film for protecting the outermost wiring conductor 5 from heat and the external environment. The solder resist layer 6 on the upper surface side exposes the upper surface of the conductive protrusion 12 and the upper surface of the second connection portion 5b. It is attached so that Further, the solder resist layer 6 on the lower surface side is applied so as to expose the third connection portion 5c for external connection.
In the wiring board 10 of the present invention, the upper surface of the conductive protrusion 12 is substantially the same height as the upper surface of the solder resist layer 6 or slightly lower than that. As described above, the upper surface of the conductive protrusion 12 is substantially the same height as the upper surface of the solder resist layer 6 or slightly lower than the upper surface of the solder resist layer 6, so that the semiconductor is formed on the conductive protrusion 12 via the conductive bump B1. When connecting the electrode terminals of the integrated circuit element E1, a gap corresponding to the height of the conductive bump B1 is secured between the solder resist layer 6 and the semiconductor integrated circuit element E1, and the filling resin U1 is filled in the gap. It is good and can be filled without generating voids.
In addition, when the upper surface of the conductive protrusion 12 is slightly lower than the upper surface of the solder resist layer 6, the height difference is preferably 10 μm or less, and further, as shown in FIG. Furthermore, it is preferable that the step between the upper surface of the conductive protrusion 12 and the upper surface of the solder resist layer 6 is a gently inclined surface. Thus, the step between the upper surface of the conductive protrusion 12 and the upper surface of the solder resist layer 6 is a gently inclined surface with a height difference of 10 μm or less, so that the upper surface of the conductive protrusion 12 becomes the upper surface of the solder resist layer 6. Even when the filling resin U1 is slightly lower, the filling resin U1 flows along the gentle inclined surface into the gap between the semiconductor integrated circuit element E1 and the wiring board 10, and the filling resin U1 has good filling properties, and It can be filled without generating voids.
Further, the upper surface of the second connection portion 5b is exposed in an opening provided in the solder resist layer 6, and forms a bottom surface of a recess formed by this opening. Thereby, when the semiconductor element mounting board E2 is mounted on the wiring board 10, the solder ball B2 for connecting the electrode terminal of the semiconductor element mounting board E2 and the second connection portion 5b is satisfactorily formed on the second connection portion 5b. Thus, the semiconductor element mounting substrate E2 can be satisfactorily mounted on the wiring substrate 10.
The conductive protrusion 12 and the second connection portion 5b are prevented from being oxidized and corroded on the upper surface of the conductive protrusion 12 exposed from the solder resist layer 6 and the upper surface of the second connection portion 5b. In order to improve the connection with B2, nickel plating and gold plating may be sequentially deposited by an electroless plating method or an electrolytic plating method, or a solder layer may be deposited.

次に、本発明の配線基板の製造方法を、上述の第一接続部５ａ、導電突起１２、第二接続部５ｂおよびソルダーレジスト層６の形成を例にして、図４〜図８を基に説明する。
図４は、本発明にかかる配線基板の製造方法を示す概略説明図であり、図５〜図８は、各工程を説明する概略断面図である。これらのうち、図５および図６は、半導体素子接続用の帯状の配線導体およびその上の導電突起の形成工程を示す概略断面図であり、図７は、ソルダーレジスト層の被着工程を示す概略断面図であり、図８は、ソルダーレジスト層の研磨工程を示す概略断面図である。 Next, the manufacturing method of the wiring board of the present invention is based on FIGS. 4 to 8 by taking the formation of the first connection portion 5a, the conductive protrusion 12, the second connection portion 5b and the solder resist layer 6 as an example. explain.
FIG. 4 is a schematic explanatory view showing a method for manufacturing a wiring board according to the present invention, and FIGS. 5 to 8 are schematic cross-sectional views for explaining each process. Among these, FIG. 5 and FIG. 6 are schematic sectional views showing a step of forming a strip-shaped wiring conductor for connecting a semiconductor element and a conductive protrusion thereon, and FIG. 7 shows a step of depositing a solder resist layer. FIG. 8 is a schematic cross-sectional view, and FIG. 8 is a schematic cross-sectional view showing a solder resist layer polishing step.

まず、図４（ａ）、（ｂ）および図５（ａ）、（ｂ）に示すように、上面側における最外層の絶縁層４の表面に、全面にわたって、電解めっき用の下地金属層５１を無電解めっきにより被着形成する。下地金属層５１を形成する無電解めっきとしては、無電解銅めっきが好ましい。
次いで、図４（ｃ）および図５（ｃ）に示すように、下地金属層５１の表面に、第一レジスト層Ｒ１を形成する。このとき、第一レジスト層Ｒ１は、第一配線パターン部５Ａおよび第二配線パターン部５Ｂに対応する形状の第一開口Ａ１を有するように形成する。具体的には、光感光性アルカリ現像型ドライフィルムレジストを下地金属層５１上に貼着し、それにフォトリソグラフィ技術を用いて露光および現像を行なうことにより、第一開口Ａ１を有するパターンに形成される。また、第一レジスト層Ｒ１の厚みは、後に形成する第一接続部５ａおよびその上に形成する導電突起１２の合計厚みよりも若干厚い厚みであるのがよい。 First, as shown in FIGS. 4A and 4B and FIGS. 5A and 5B, the entire surface of the outermost insulating layer 4 on the upper surface side is covered with an underlying metal layer 51 for electrolytic plating. Is formed by electroless plating. As the electroless plating for forming the base metal layer 51, electroless copper plating is preferable.
Next, as shown in FIGS. 4C and 5C, a first resist layer R <b> 1 is formed on the surface of the base metal layer 51. At this time, the first resist layer R1 is formed so as to have a first opening A1 having a shape corresponding to the first wiring pattern portion 5A and the second wiring pattern portion 5B. Specifically, a photosensitive alkali-developable dry film resist is stuck on the base metal layer 51, and is exposed and developed using a photolithography technique to form a pattern having the first opening A1. The The thickness of the first resist layer R1 is preferably slightly thicker than the total thickness of the first connection portion 5a to be formed later and the conductive protrusions 12 formed thereon.

次いで、図４（ｄ）および図５（ｄ）に示すように、第一レジスト層Ｒ１の第一開口Ａ１内に露出する下地金属層５１上に、電解めっきにより第一配線パターン部５Ａおよび第二配線パターン部５Ｂを被着形成する。第一配線パターン５Ａおよび第二配線パターン部５Ｂを形成するための電解めっきとしては、電解銅めっきが好ましい。ここで、第一配線パターン部５Ａおよび第二配線パターン部５Ｂの厚みは、第一レジスト層Ｒ１より薄くなっている。具体的には、第一配線パターン部５Ａおよび第二配線パターン部５Ｂの厚みは、８〜２０μｍ、好ましくは１０〜１５μｍであるのがよい。   Next, as shown in FIG. 4D and FIG. 5D, the first wiring pattern portion 5A and the first wiring pattern 5A are formed on the base metal layer 51 exposed in the first opening A1 of the first resist layer R1 by electrolytic plating. Two wiring pattern portions 5B are deposited. As the electrolytic plating for forming the first wiring pattern 5A and the second wiring pattern portion 5B, electrolytic copper plating is preferable. Here, the first wiring pattern portion 5A and the second wiring pattern portion 5B are thinner than the first resist layer R1. Specifically, the thickness of the first wiring pattern portion 5A and the second wiring pattern portion 5B is 8 to 20 μm, preferably 10 to 15 μm.

次いで、図４（ｅ）および図６（ｅ）に示すように、第一レジスト層Ｒ１、第一配線パターン部５Ａおよび第二配線パターン部５Ｂの表面に、第二レジスト層Ｒ２を形成する。このとき、第二レジスト層Ｒ２は、第二配線パターン部５Ｂを被覆するとともに、導電突起１２が形成される第一接続部５ａの位置に導電突起１２の長さに対応した幅で第一開口Ａ１を真横に横切る第二開口Ａ２を有するように形成する。具体的には、光感光性アルカリ現像型ドライフィルムレジストを第一レジスト層Ｒ１、第一配線パターン部５Ａおよび第二配線パターン部５Ｂ上に貼着し、それにフォトリソグラフィ技術を用いて露光および現像を行なうことにより、第二開口Ａ２を有するパターンに形成される。なお、第二レジスト層Ｒ２の厚みは、第一レジスト層Ｒ１の厚み以上であることが好ましい。   Next, as shown in FIGS. 4E and 6E, a second resist layer R2 is formed on the surfaces of the first resist layer R1, the first wiring pattern portion 5A, and the second wiring pattern portion 5B. At this time, the second resist layer R2 covers the second wiring pattern portion 5B, and the first opening with a width corresponding to the length of the conductive protrusion 12 at the position of the first connection portion 5a where the conductive protrusion 12 is formed. It forms so that it may have 2nd opening A2 which crosses A1 directly. Specifically, a photosensitive alkali development type dry film resist is stuck on the first resist layer R1, the first wiring pattern portion 5A, and the second wiring pattern portion 5B, and is exposed and developed using photolithography technology. To form a pattern having the second opening A2. In addition, it is preferable that the thickness of 2nd resist layer R2 is more than the thickness of 1st resist layer R1.

次いで、図４（ｆ）および図６（ｆ）に示すように、一開口Ａ１および第二開口Ａ２で囲まれた第一接続部５ａ上に、導電突起１２を電解めっきにより形成する。導電突起１２を形成するための電解めっきとしては、電解銅めっきが好ましい。なお、導電突起１２の高さは、第一レジスト層Ｒ１の上面よりも若干低い位置とする。このとき、導電突起１２は、第一開口Ａ１および第二開口Ａ２で囲まれた第一接続部５ａ上に形成されるので、その幅は第一開口Ａ１で画定される幅、すなわち第一接続部５ａの幅と一致する幅で形成されるとともに、その長さは第二開口Ａ２で画定される幅で形成される。その結果、導電突起１２は第一接続部５ａからはみ出すことがなく、導電バンプＢ１と接続するために十分な幅が確保され、かつその断面形状が歪むこともない。したがって、優れた接続信頼性で導電バンプＢ１と導電突起１２とを接合することができる。
なお、第二開口Ａ２の幅を、第一開口Ａ１の幅よりも広い幅で（例えば５０μｍ以上広い幅で）形成しておくと、その分、導電突起１２の長さが長く形成されることになるので、第二レジスト層Ｒ２を形成する際の位置合わせの誤差に起因して第二開口Ａ２の位置が第一配線パターン部５Ａの長さ方向に多少ずれたとしても（例えば２５μｍ程度ずれたとしても）、導電突起１２上に半導体集積回路素子Ｅ１の電極端子と正確に対向する領域を確保することができ、その結果、半導体集積回路素子Ｅ１の電極端子と導電突起１２とを導電バンプＢ１を介して正確に接続することができる。したがって、第二開口Ａ２の幅は、第一開口Ａ１の幅よりも例えば５０μｍ以上広くしておくことが好ましい。
また、第二開口Ａ２は、第一開口Ａ１を横切るように形成されているので、第二レジスト層Ｒ２を形成する際の位置合わせの誤差に起因して第二開口Ａ２の位置が第一配線パターン部５Ａの幅方向にずれたとしても、第一接続部５ａの露出幅が変わることはなく、したがって形成される導電突起１２の幅に影響を与えることはない。 Next, as shown in FIGS. 4 (f) and 6 (f), conductive protrusions 12 are formed by electrolytic plating on the first connection portion 5a surrounded by the one opening A1 and the second opening A2. As the electrolytic plating for forming the conductive protrusions 12, electrolytic copper plating is preferable. The height of the conductive protrusions 12 is set slightly lower than the upper surface of the first resist layer R1. At this time, since the conductive protrusion 12 is formed on the first connection portion 5a surrounded by the first opening A1 and the second opening A2, the width thereof is the width defined by the first opening A1, that is, the first connection. It is formed with a width that matches the width of the portion 5a, and the length is formed with a width defined by the second opening A2. As a result, the conductive protrusion 12 does not protrude from the first connection portion 5a, a sufficient width is secured for connection with the conductive bump B1, and the cross-sectional shape thereof is not distorted. Therefore, the conductive bump B1 and the conductive protrusion 12 can be joined with excellent connection reliability.
In addition, if the width of the second opening A2 is wider than the width of the first opening A1 (for example, a width wider than 50 μm), the length of the conductive protrusion 12 is increased accordingly. Therefore, even if the position of the second opening A2 is slightly shifted in the length direction of the first wiring pattern portion 5A due to an alignment error when forming the second resist layer R2, the shift is about 25 μm (for example, about 25 μm). Even if it is possible to ensure a region on the conductive protrusion 12 that is exactly opposite to the electrode terminal of the semiconductor integrated circuit element E1, the electrode terminal of the semiconductor integrated circuit element E1 and the conductive protrusion 12 are connected to the conductive bump. It is possible to connect accurately through B1. Therefore, it is preferable that the width of the second opening A2 is, for example, 50 μm or more wider than the width of the first opening A1.
Further, since the second opening A2 is formed so as to cross the first opening A1, the position of the second opening A2 is set to the first wiring due to an alignment error when forming the second resist layer R2. Even if the pattern portion 5A is displaced in the width direction, the exposed width of the first connection portion 5a does not change, and thus does not affect the width of the conductive protrusion 12 to be formed.

導電突起１２を形成後、図４（ｇ）および図６（ｇ）に示すように、第一レジスト層Ｒ１および第二レジスト層Ｒ２を除去する。第一レジスト層Ｒ１および第二レジスト層Ｒ２の除去は、例えば、水酸化ナトリウム水溶液への浸漬により行なうことができる。
次に、図４（ｈ）および図６（ｈ）に示すように、第一配線パターン部５Ａおよび第二配線パターン部５Ｂが形成された部分以外の下地金属層５１を除去する。これにより、隣接する第一接続部５ａ間および第二接続部５ｂ間が電気的に独立することになる。このとき、第一接続部５ａの上に形成された導電突起１２は、その幅が第一接続部５ａと一致する幅で形成されており、第一接続部５ａからはみ出すことはないので、隣接する第一接続部５ａ間の電気的な絶縁が良好に保たれる。なお、第一配線パターン部５Ａおよび第二配線パターン部５Ｂが形成された部分以外の下地金属層５１を除去するには、前記第一レジスト層Ｒ１および第二レジスト層Ｒ２を除去した後に露出する下地金属層５１を、例えば、塩化第二銅を含有するエッチング液によりエッチング除去する方法を採用すればよい。 After forming the conductive protrusions 12, the first resist layer R1 and the second resist layer R2 are removed as shown in FIGS. 4 (g) and 6 (g). The removal of the first resist layer R1 and the second resist layer R2 can be performed, for example, by immersion in an aqueous sodium hydroxide solution.
Next, as shown in FIGS. 4H and 6H, the base metal layer 51 other than the portion where the first wiring pattern portion 5A and the second wiring pattern portion 5B are formed is removed. Thereby, between the adjacent 1st connection parts 5a and between the 2nd connection parts 5b becomes electrically independent. At this time, the conductive protrusion 12 formed on the first connection portion 5a is formed with a width that matches the first connection portion 5a and does not protrude from the first connection portion 5a. Thus, the electrical insulation between the first connecting portions 5a is kept good. In order to remove the base metal layer 51 other than the portion where the first wiring pattern portion 5A and the second wiring pattern portion 5B are formed, the first resist layer R1 and the second resist layer R2 are removed and exposed. What is necessary is just to employ | adopt the method of etching-removing the base metal layer 51 with the etching liquid containing a cupric chloride, for example.

次いで、図４（ｉ）および図７（ｉ）に示すように、第二接続部５ｂを除き、ソルダーレジスト層用の樹脂６ａで、第一配線パターン部５Ａ（導電突起１２）、第二配線パターン部５Ｂおよびこれら配線導体５が形成された部分以外の最外層の絶縁層４を被覆する。ソルダーレジスト層用の樹脂６ａとしては、配線基板の表面を保護するソルダーレジスト層として機能する各種の公知の樹脂が採用可能であり、具体的には、例えば、エポキシ樹脂等に酸化珪素やタルク等の無機物粉末フィラーを３０〜７０質量％程度分散させた絶縁材料から成る熱硬化性樹脂が好ましい。このような樹脂６ａとなる感光性を有する熱硬化性樹脂ペーストまたはフィルムを、第一配線パターン部５Ａ（導電突起１２）および第二配線パターン部５Ｂが形成された最外層の絶縁層４上に積層したのち、第二接続部５ｂを露出させる第三開口Ａ３を有するように露光および現像し、硬化させればよい。   Next, as shown in FIGS. 4 (i) and 7 (i), the first wiring pattern portion 5A (conductive protrusion 12) and the second wiring are made of the resin 6a for the solder resist layer except for the second connection portion 5b. The outermost insulating layer 4 other than the pattern portions 5B and the portions where the wiring conductors 5 are formed is covered. As the resin 6a for the solder resist layer, various known resins that function as a solder resist layer for protecting the surface of the wiring board can be used. Specifically, for example, epoxy resin or the like such as silicon oxide or talc A thermosetting resin made of an insulating material in which about 30 to 70% by mass of the inorganic powder filler is dispersed is preferable. A photosensitive thermosetting resin paste or film to be the resin 6a is applied on the outermost insulating layer 4 on which the first wiring pattern portion 5A (conductive protrusion 12) and the second wiring pattern portion 5B are formed. After the lamination, exposure and development may be performed and cured so as to have a third opening A3 exposing the second connection portion 5b.

ソルダーレジスト層用の樹脂６ａで被覆した後、図４（ｊ）および図７（ｊ）に示すように、該ソルダーレジスト層用の樹脂６ａを前記導電突起１２の上面が露出するまで研磨することによってソルダーレジスト層６を形成して、導電突起１２の上面がソルダーレジスト層６の上面と実質的に同じ平面で露出する配線基板１０を得る。なお、前記研磨には、各種の公知の機械的研磨方法やレーザスクライブ法を採用すればよく、ソルダーレジスト層用の樹脂６ａの上面側を全面的に研磨してもよいし、導電突起１２に対応する部位のみを選択的に研磨してもよい。
導電突起１２に対応する部位のみを選択的に研磨する場合には、図８（ａ）に示すように、第二接続部５ｂを除いて、第一配線パターン部５Ａ（導電突起１２）、第二配線パターン部５Ｂおよびこれら配線導体５が形成された部分以外の最外層の絶縁層４をソルダーレジスト層用の樹脂６ａで被覆した後、図８（ｂ）に示すように、樹脂６ａの上の導電突起１２に対応する位置に、導電突起１２よりも若干大きな開口Ａ４を有するマスクＭを配設する。次いで、図８（ｃ）に示すように、マスクＭから露出したソルダーレジスト用の樹脂６ａをウェットブラスト法により研磨し、最後に、図８（ｄ）に示すように、マスクＭを除去する方法が好適である。このとき、開口Ａ４内の開口壁近傍領域では、砥粒の当たりが開口壁により阻害されて弱まるので、開口壁に近づくにしたがって研磨の程度が小さくなり、その結果、導電突起１２とソルダーレジスト層６との段差がなだらかな傾斜面となる。このように導電突起１２とソルダーレジスト層６との段差がなだらかな傾斜面である場合、導電突起１２の上面がソルダーレジスト層６の上面よりも若干低い場合であっても、充填樹脂Ｕ１がこの緩やかな傾斜面を伝って半導体集積回路素子Ｅ１と配線基板１０との間の隙間に良好に流れ込み、充填樹脂Ｕ１を充填性良く、かつボイドを発生させることなく充填することができる。なお、ソルダーレジスト層６の厚みは、ソルダーレジスト層６の上面と導電突起１２の上面との高低差が１０μｍ以下となる厚みにすることが好ましい。 After coating with the solder resist layer resin 6a, as shown in FIGS. 4J and 7J, the solder resist layer resin 6a is polished until the upper surface of the conductive protrusion 12 is exposed. By forming the solder resist layer 6, the wiring substrate 10 is obtained in which the upper surface of the conductive protrusion 12 is exposed in substantially the same plane as the upper surface of the solder resist layer 6. For the polishing, various known mechanical polishing methods and laser scribing methods may be employed. The upper surface side of the resin 6a for the solder resist layer may be entirely polished, or the conductive protrusions 12 may be polished. Only the corresponding part may be selectively polished.
When only the portion corresponding to the conductive protrusion 12 is selectively polished, as shown in FIG. 8A, the first wiring pattern portion 5A (conductive protrusion 12), the second connection portion 5b are excluded, as shown in FIG. After covering the outermost insulating layer 4 other than the two wiring pattern portions 5B and the portions where the wiring conductors 5 are formed with the resin 6a for the solder resist layer, as shown in FIG. A mask M having an opening A4 slightly larger than the conductive protrusion 12 is disposed at a position corresponding to the conductive protrusion 12. Next, as shown in FIG. 8C, the solder resist resin 6a exposed from the mask M is polished by the wet blast method, and finally, the mask M is removed as shown in FIG. 8D. Is preferred. At this time, in the vicinity of the opening wall in the opening A4, the contact of the abrasive grains is hindered and weakened by the opening wall, so that the degree of polishing becomes smaller as it approaches the opening wall. As a result, the conductive protrusion 12 and the solder resist layer The step with 6 becomes a gently inclined surface. Thus, when the step between the conductive protrusion 12 and the solder resist layer 6 is a gently inclined surface, even if the upper surface of the conductive protrusion 12 is slightly lower than the upper surface of the solder resist layer 6, the filling resin U1 It is possible to satisfactorily flow into the gap between the semiconductor integrated circuit element E1 and the wiring substrate 10 through the gentle inclined surface, and to fill the filling resin U1 with good filling property and without generating voids. In addition, it is preferable that the thickness of the solder resist layer 6 is a thickness at which the height difference between the upper surface of the solder resist layer 6 and the upper surface of the conductive protrusion 12 is 10 μm or less.

上記のようにしてソルダーレジスト層６が被着形成された配線基板１０においては、図１に示すように、ペリフェラル型の半導体集積回路素子Ｅ１の電極端子（ピッチが１００μｍ以下）と第一接続部５ａ上に形成された導電突起１２とを導電バンプＢ１を介して電気的に接続（フリップチップ接続）することによって、半導体集積回路素子Ｅ１の電極端子と配線導体５とが電気的に接続される。ここで、半導体素子接続用の第一接続部５ａ上に導電突起１２が第一接続部５ａの幅と一致する幅で確実に被着形成されているので、導電突起１２は、導電バンプＢ１との接続のために十分な幅が確保されるとともに、断面形状に歪みもなく、導電バンプＢ１と接合され、その結果、優れた接続信頼性が得られる。   In the wiring substrate 10 on which the solder resist layer 6 is deposited as described above, as shown in FIG. 1, the electrode terminals (pitch is 100 μm or less) of the peripheral type semiconductor integrated circuit element E1 and the first connection portion The electrode terminal of the semiconductor integrated circuit element E1 and the wiring conductor 5 are electrically connected by electrically connecting (flip chip connection) the conductive protrusion 12 formed on 5a via the conductive bump B1. . Here, since the conductive protrusion 12 is reliably deposited on the first connection portion 5a for connecting the semiconductor element with a width that matches the width of the first connection portion 5a, the conductive protrusion 12 is connected to the conductive bump B1. A sufficient width for securing the connection is secured, the cross-sectional shape is not distorted, and the conductive bump B1 is joined. As a result, excellent connection reliability is obtained.

半導体集積回路素子Ｅ１の電極端子と配線導体５とを電気的に接続したのち、半導体集積回路素子Ｅ１と配線基板１０との間の隙間に充填樹脂Ｕ１を充填することにより、半導体集積回路素子Ｅ１は配線基板１０上に実装される。ここで、導電突起１２の上面およびソルダーレジスト層６の上面は実質的に同じ高さとなるので、半導体集積回路素子Ｅ１と配線基板１０との間に導電バンプＢ１の高さに相当する隙間を確保できるようになり、充填樹脂Ｕ１の充填性に優れ、その結果、ボイドの発生が抑制される。   After the electrode terminal of the semiconductor integrated circuit element E1 and the wiring conductor 5 are electrically connected, the gap between the semiconductor integrated circuit element E1 and the wiring substrate 10 is filled with the filling resin U1, thereby the semiconductor integrated circuit element E1. Is mounted on the wiring board 10. Here, since the upper surface of the conductive protrusion 12 and the upper surface of the solder resist layer 6 have substantially the same height, a gap corresponding to the height of the conductive bump B1 is secured between the semiconductor integrated circuit element E1 and the wiring substrate 10. As a result, the filling property of the filling resin U1 is excellent, and as a result, generation of voids is suppressed.

そして、さらにその上に、第二電子部品としての半導体素子搭載基板Ｅ２の電極端子と第二接続部５ｂとを半田ボールＢ２を介して接続することにより、半導体素子搭載基板Ｅ２と配線基板１０の配線導体５とが電気的に接続され、半導体素子搭載基板Ｅ２が配線基板１０上に半田ボール接続により実装される。このようにして、本発明の配線基板上に複数の電子部品が高密度実装される。ここで、第二接続部５ｂの上面は、ソルダーレジスト層６の開口とで形成される凹部の底面を形成しているので、この凹部内に半田ボールＢ２が良好に位置決めされ、半導体素子搭載基板Ｅ２を配線基板１０上に良好に接続することが可能となる。   Further, the electrode terminal of the semiconductor element mounting board E2 as the second electronic component and the second connection portion 5b are further connected via the solder balls B2 to the semiconductor element mounting board E2 and the wiring board 10. The wiring conductor 5 is electrically connected, and the semiconductor element mounting board E2 is mounted on the wiring board 10 by solder ball connection. In this way, a plurality of electronic components are mounted with high density on the wiring board of the present invention. Here, since the upper surface of the second connection portion 5b forms the bottom surface of the recess formed by the opening of the solder resist layer 6, the solder ball B2 is well positioned in the recess, and the semiconductor element mounting substrate It becomes possible to connect E2 on the wiring board 10 satisfactorily.

なお、上述した例では、第二開口Ａ２を第一開口Ａ１と直交する向きに形成したが、本発明にかかる配線基板の製造方法はこれに限定されるものではなく、導電突起１２の形状に合わせて、任意の向きに第二開口Ａ２を形成すればよい。また、一つの第一接続部５ａの表面には、一つの導電突起１２が形成されているが、複数の第一開口Ａ１および第二開口Ａ２を組み合わせることにより、一つの第一接続部５ａの表面に複数の導電突起１２を被着形成することもできる。さらに、上述した例では、第一接続部５ａおよび導電突起１２は、第一電子部品としてペリフェラル型の半導体集積回路素子Ｅ１を搭載するために半導体集積回路素子Ｅ１の外周部に対応する位置にのみ形成しているが、例えば主面の中央部にも電極端子を有するような第一電子部品を搭載する場合、その電極端子の配列に応じて第一電子部品の中央部に対応する位置にも形成することができる。   In the above-described example, the second opening A2 is formed in a direction orthogonal to the first opening A1, but the method for manufacturing the wiring board according to the present invention is not limited to this, and the shape of the conductive protrusion 12 is In addition, the second opening A2 may be formed in an arbitrary direction. In addition, one conductive protrusion 12 is formed on the surface of one first connection portion 5a. By combining a plurality of first openings A1 and second openings A2, one first connection portion 5a A plurality of conductive protrusions 12 can be deposited on the surface. Furthermore, in the above-described example, the first connection portion 5a and the conductive protrusion 12 are only at positions corresponding to the outer peripheral portion of the semiconductor integrated circuit element E1 in order to mount the peripheral type semiconductor integrated circuit element E1 as the first electronic component. Although it is formed, for example, when mounting a first electronic component having an electrode terminal in the central portion of the main surface, the position corresponding to the central portion of the first electronic component also depends on the arrangement of the electrode terminals. Can be formed.

また、上述した例では、第二電子部品として半導体素子搭載基板Ｅ２を半田ボール接続により搭載したが、図９に断面図で示すように、第二電子部品としてペリフェラル型の半導体集積回路素子Ｅ２をワイヤボンド接続により搭載してもよい。フリップチップ接続により搭載された第一の電子部品としての半導体集積回路素子Ｅ１上に第二の電子部品としての半導体集積回路素子Ｅ２を接合するとともに、該半導体集積回路素子Ｅ２の電極端子と第二接続部５ｂとをボンディングワイヤＢ４により接続することにより、半導体集積回路素子Ｅ２の電極端子と配線導体５とが電気的に接続され、半導体集積回路素子Ｅ２がワイヤボンド接続により配線基板１０上に搭載される。なお、この場合、第二接続部５ｂは図１０に平面図で示すように長方形状であることが好ましく、第二接続部５ｂの表面にはニッケルめっきおよび金めっきを無電解めっき法や電解めっき法により順次被着させておくことが好ましい。   In the above-described example, the semiconductor element mounting substrate E2 is mounted as the second electronic component by solder ball connection. However, as shown in the cross-sectional view of FIG. 9, the peripheral type semiconductor integrated circuit element E2 is used as the second electronic component. You may mount by wire bond connection. The semiconductor integrated circuit element E2 as the second electronic component is joined on the semiconductor integrated circuit element E1 as the first electronic component mounted by flip chip connection, and the electrode terminal of the semiconductor integrated circuit element E2 and the second By connecting the connecting portion 5b with the bonding wire B4, the electrode terminal of the semiconductor integrated circuit element E2 and the wiring conductor 5 are electrically connected, and the semiconductor integrated circuit element E2 is mounted on the wiring substrate 10 by wire bonding connection. Is done. In this case, the second connection portion 5b is preferably rectangular as shown in a plan view in FIG. 10, and the surface of the second connection portion 5b is subjected to electroless plating or electrolytic plating with nickel plating and gold plating. It is preferable to deposit sequentially by the method.

第一電子部品としてのペリフェラル型の半導体集積回路素子をフリップチップ接続により搭載し、その上に第二電子部品としての半導体素子搭載基板を半田ボール接続により搭載した本発明にかかる配線基板を示す概略断面図である。1 schematically shows a wiring board according to the present invention in which a peripheral type semiconductor integrated circuit element as a first electronic component is mounted by flip chip connection, and a semiconductor element mounting substrate as a second electronic component is mounted thereon by solder ball connection. It is sectional drawing. 図１の配線基板を示す平面図である。It is a top view which shows the wiring board of FIG. 図１に示す配線基板における好ましい例を示す要部拡大断面図である。It is a principal part expanded sectional view which shows the preferable example in the wiring board shown in FIG. （ａ）〜（ｊ）は、本発明にかかる配線基板の製造方法を示す概略説明図である。(A)-(j) is a schematic explanatory drawing which shows the manufacturing method of the wiring board concerning this invention. （ａ）〜（ｄ）は、本発明の製造方法にかかる配線導体の形成工程を示す断面図である。(A)-(d) is sectional drawing which shows the formation process of the wiring conductor concerning the manufacturing method of this invention. （ｅ）〜（ｈ）は、本発明の製造方法にかかる導電突起の形成工程を示す断面図である。(E)-(h) is sectional drawing which shows the formation process of the electrically conductive protrusion concerning the manufacturing method of this invention. （ｉ）〜（ｊ）は、本発明の製造方法にかかるソルダーレジスト層の被着工程を示す断面図である。(I)-(j) is sectional drawing which shows the adhesion process of the soldering resist layer concerning the manufacturing method of this invention. （ａ）〜（ｄ）は、本発明の製造方法を示すソルダーレジスト層の研磨工程を示す断面図である。(A)-(d) is sectional drawing which shows the grinding | polishing process of the soldering resist layer which shows the manufacturing method of this invention. 第一電子部品としてのペリフェラル型の半導体集積回路素子をフリップチップ接続により搭載し、その上に第二電子部品としての半導体集積回路素子をワイヤボンド接続により搭載した本発明にかかる配線基板を示す概略断面図である。1 schematically shows a wiring board according to the present invention in which a peripheral type semiconductor integrated circuit element as a first electronic component is mounted by flip chip connection, and a semiconductor integrated circuit element as a second electronic component is mounted thereon by wire bond connection. It is sectional drawing. 図９の配線基板を示す平面図である。It is a top view which shows the wiring board of FIG. 第一電子部品としてのペリフェラル型の半導体集積回路素子をフリップチップ接続により搭載し、その上に第二電子部品としての半導体素子搭載基板を半田ボール接続により搭載した従来の配線基板を示す概略断面図である。Schematic sectional view showing a conventional wiring board in which a peripheral type semiconductor integrated circuit element as a first electronic component is mounted by flip chip connection, and a semiconductor element mounting substrate as a second electronic component is mounted thereon by solder ball connection It is. 図１１の配線基板を示す平面図である。It is a top view which shows the wiring board of FIG.

符号の説明Explanation of symbols

２ 配線導体
３ 絶縁基板
４ 絶縁層
５ 配線導体
５Ａ 第一配線パターン部
５ａ 第一接続部
５Ｂ 第二配線パターン部
５ｂ 第二接続部
６ ソルダーレジスト層
６ａ ソルダーレジスト層用の樹脂
７ スルーホール
８ 埋め込み樹脂
９ ビアホール
１０ 配線基板
１２ 導電突起
５１ 下地金属層
Ｅ１ 第一電子部品
Ｅ２ 第二電子部品
Ｂ１ 導電バンプ
Ｂ２ 半田ボール
Ｂ４ ボンディングワイヤ
Ｕ１ 充填樹脂
Ａ１ 第一開口
Ａ２ 第二開口
Ａ３ 第三開口
Ｒ１ 第一レジスト層
Ｒ２ 第二レジスト層 2 Wiring conductor 3 Insulating substrate 4 Insulating layer 5 Wiring conductor 5A First wiring pattern portion 5a First connection portion 5B Second wiring pattern portion 5b Second connection portion 6 Solder resist layer 6a Resin for solder resist layer 7 Through hole 8 Embedding Resin 9 Via hole 10 Wiring board 12 Conductive protrusion 51 Base metal layer E1 First electronic component E2 Second electronic component B1 Conductive bump B2 Solder ball B4 Bonding wire U1 Filling resin A1 First opening A2 Second opening A3 Third opening R1 First Resist layer R2 Second resist layer

Claims (11)

絶縁層と配線導体とが交互に積層され、最外層の絶縁層上の一部に電子部品接続用の配線導体が形成されており、該電子部品接続用の配線導体には、第一電子部品がフリップチップ接続される第一接続部を有する第一配線パターン部が帯状に複数並んで設けられているとともに、第二電子部品が半田ボール接続またはワイヤボンド接続される第二接続部を有する第二配線パターン部が複数並んで設けられ、かつ、前記第一接続部上には導電突起が第一接続部の幅と一致する幅で形成されており、さらに、前記電子部品接続用の配線導体上および該電子部品接続用の配線導体が形成された部分以外の最外層の絶縁層上には前記導電突起の上面および前記第二接続部の上面を露出させるソルダーレジスト層が被着されていることを特徴とする配線基板。   Insulating layers and wiring conductors are alternately laminated, and a wiring conductor for connecting electronic components is formed on a part of the outermost insulating layer. The wiring conductor for connecting electronic components includes a first electronic component. A plurality of first wiring pattern portions having a first connection portion to be flip-chip connected, and a second connection portion having a second connection portion to which a second electronic component is connected by solder ball connection or wire bond connection. A plurality of two wiring pattern portions are provided side by side, and a conductive protrusion is formed on the first connection portion with a width that matches the width of the first connection portion. Further, the wiring conductor for connecting the electronic component A solder resist layer that exposes the upper surface of the conductive protrusion and the upper surface of the second connection part is deposited on the outermost insulating layer other than the upper part and the part where the wiring conductor for connecting the electronic component is formed. Wiring characterized by Plate. 前記導電突起の上面と前記ソルダーレジスト層の上面とが実質的に同じ高さである、請求項１記載の配線基板。   The wiring board according to claim 1, wherein an upper surface of the conductive protrusion and an upper surface of the solder resist layer are substantially the same height. 前記導電突起の上面と前記ソルダーレジスト層の上面との高低差が１０μｍ以下であるとともに、前記導電突起の上面と前記ソルダーレジスト層の上面との段差が傾斜面となっている、請求項１記載の配線基板。   2. The height difference between the upper surface of the conductive protrusion and the upper surface of the solder resist layer is 10 μm or less, and a step between the upper surface of the conductive protrusion and the upper surface of the solder resist layer is an inclined surface. Wiring board. 前記導電突起の長さが該導電突起の幅よりも長い、請求項１〜３のいずれかに記載の配線基板。   The wiring board according to claim 1, wherein a length of the conductive protrusion is longer than a width of the conductive protrusion. 絶縁層と配線導体とを交互に積層し、最外層の絶縁層上の一部には電子部品接続用の配線導体を形成し、該電子部品接続用の配線導体の形成に際しては、第一電子部品がフリップチップ接続される第一接続部を有する第一配線パターン部を帯状に複数並んで設けるとともに、第二電子部品が半田ボール接続またはワイヤボンド接続される第二接続部を有する第二配線パターン部を複数並んで設けるようにし、かつ、前記第一接続部上に導電突起を第一接続部の幅と一致する幅で形成し、さらに、前記電子部品接続用の配線導体上および該電子部品接続用の配線導体が形成された部分以外の最外層の絶縁層上に前記導電突起の上面および前記第二接続部の上面を露出させるソルダーレジスト層を被着する配線基板の製造方法であって、
前記最外層の絶縁層上に、該絶縁層上の全面を覆う電解めっき用の下地金属層を形成する工程と、
次に前記下地金属層上に前記電子部品接続用の配線導体に対応する形状の第一開口を有する第一レジスト層を形成する工程と、
次に前記第一開口内の前記下地金属層上に電解めっきにより前記電子部品接続用の配線導体を形成する工程と、
次に前記第一レジスト層および前記電子部品接続用の配線導体の上に、前記第一接続部に対応する位置で前記第一配線パターン部を横切る第二開口を有する第二レジスト層を形成する工程と、
次に前記第一開口および第二開口で囲まれた前記第一配線パターン部上に電解めっきにより前記導電突起を前記第一開口で画定される幅および第二開口で画定される長さで形成する工程と、
次に前記第一レジスト層および第二レジスト層を除去する工程と、
次に前記電子部品接続用の配線導体が形成された部分以外の前記下地金属層を除去する工程と、
次に前記電子部品接続用の配線導体上および該電子部品接続用の配線導体が形成された部分以外の最外層の絶縁層上に、前記導電突起の上面および前記第二接続部の上面を露出させるソルダーレジスト層を被着する工程とを含むことを特徴とする配線基板の製造方法。 Insulating layers and wiring conductors are alternately stacked, and a wiring conductor for connecting electronic components is formed on a part of the outermost insulating layer. When forming the wiring conductor for connecting electronic components, A second wiring having a second connection portion in which a plurality of first wiring pattern portions having a first connection portion to which a component is flip-chip connected are provided in a strip shape and a second electronic component is connected by solder ball connection or wire bond connection A plurality of pattern portions are provided side by side, and a conductive protrusion is formed on the first connection portion with a width that matches the width of the first connection portion, and further on the wiring conductor for connecting the electronic component and the electron A method of manufacturing a wiring board in which a solder resist layer that exposes the upper surface of the conductive protrusion and the upper surface of the second connection portion is coated on an outermost insulating layer other than a portion where a wiring conductor for connecting components is formed. And
Forming a base metal layer for electrolytic plating covering the entire surface of the insulating layer on the outermost insulating layer;
Next, forming a first resist layer having a first opening having a shape corresponding to the wiring conductor for connecting the electronic component on the base metal layer;
Next, the step of forming the wiring conductor for connecting the electronic component by electrolytic plating on the base metal layer in the first opening,
Next, a second resist layer having a second opening crossing the first wiring pattern portion at a position corresponding to the first connection portion is formed on the first resist layer and the wiring conductor for connecting the electronic component. Process,
Next, the conductive protrusion is formed by electrolytic plating on the first wiring pattern portion surrounded by the first opening and the second opening with a width defined by the first opening and a length defined by the second opening. And a process of
Next, removing the first resist layer and the second resist layer,
Next, removing the base metal layer other than the portion where the wiring conductor for connecting the electronic component is formed,
Next, the upper surface of the conductive protrusion and the upper surface of the second connection portion are exposed on the wiring conductor for connecting the electronic component and on the outermost insulating layer other than the portion where the wiring conductor for connecting the electronic component is formed. And a step of depositing a solder resist layer to be produced. 前記導電突起の上面と前記ソルダーレジスト層の上面とを実質的に同じ高さに形成する、請求項５記載の配線基板の製造方法。   6. The method of manufacturing a wiring board according to claim 5, wherein the upper surface of the conductive protrusion and the upper surface of the solder resist layer are formed at substantially the same height. 前記導電突起の上面と前記ソルダーレジスト層の上面とを高低差が１０μｍ以下となるように形成するとともに、前記導電突起の上面と前記ソルダーレジスト層の上面との段差を傾斜面に形成する、請求項５記載の配線基板の製造方法。   The upper surface of the conductive protrusion and the upper surface of the solder resist layer are formed so that the height difference is 10 μm or less, and a step between the upper surface of the conductive protrusion and the upper surface of the solder resist layer is formed on an inclined surface. Item 6. A method for manufacturing a wiring board according to Item 5. 前記導電突起の前記長さを該導電突起の幅よりも長く形成する、請求項５〜７のいずれかに記載の配線基板の製造方法。   The method for manufacturing a wiring board according to claim 5, wherein the length of the conductive protrusion is formed longer than the width of the conductive protrusion. 前記ソルダーレジスト層を被着する工程は、ソルダーレジスト層用の感光性樹脂で前記導電突起を含む前記電子部品接続用の配線導体および該配線導体が形成された部分以外の最外層の絶縁層の全面を被覆する工程と、被覆した前記感光性樹脂を露光および現像処理して前記ソルダーレジスト層用の樹脂層に前記第二接続部の上面を露出させる第三開口を形成する工程と、前記ソルダーレジスト層用の樹脂を前記導電突起の上面が露出するまで研磨する工程とを含んでいる、請求項５〜８のいずれかに記載の配線基板の製造方法。   The step of depositing the solder resist layer includes a wiring conductor for connecting the electronic component including the conductive protrusions with a photosensitive resin for the solder resist layer, and an insulating layer on the outermost layer other than the portion where the wiring conductor is formed. A step of covering the entire surface, a step of exposing and developing the coated photosensitive resin to form a third opening that exposes the upper surface of the second connection portion in the resin layer for the solder resist layer, and the solder The method for manufacturing a wiring board according to claim 5, further comprising a step of polishing a resist layer resin until an upper surface of the conductive protrusion is exposed. 前記ソルダーレジスト層用の樹脂層を前記導電突起の上面が露出するまで研磨する工程は、前記ソルダーレジスト層用の樹脂層の前記導電突起に対応する部位のみを選択的に研磨する工程を含む、請求項９記載の配線基板の製造方法。   The step of polishing the resin layer for the solder resist layer until the upper surface of the conductive protrusion is exposed includes a step of selectively polishing only a portion corresponding to the conductive protrusion of the resin layer for the solder resist layer. The manufacturing method of the wiring board of Claim 9. 前記ソルダーレジスト層用の樹脂層の前記導電突起に対応する部位のみを選択的に研磨する工程は、前記ソルダーレジスト層用の樹脂層上に前記導電突起に対応する部位のみを露出させる第四開口を有するマスクを配置するとともに、該第四開口を介して前記ソルダーレジスト層用の樹脂層に砥粒を吹き付けることにより行われる、請求項１０記載の配線基板の製造方法。   The step of selectively polishing only the portion corresponding to the conductive protrusion of the resin layer for the solder resist layer is a fourth opening that exposes only the portion corresponding to the conductive protrusion on the resin layer for the solder resist layer. The method for manufacturing a wiring board according to claim 10, wherein the method is performed by disposing a mask having, and spraying abrasive grains on the resin layer for the solder resist layer through the fourth opening.
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