JP4751121B2 - Wiring board - Google Patents
Wiring board Download PDFInfo
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- JP4751121B2 JP4751121B2 JP2005213479A JP2005213479A JP4751121B2 JP 4751121 B2 JP4751121 B2 JP 4751121B2 JP 2005213479 A JP2005213479 A JP 2005213479A JP 2005213479 A JP2005213479 A JP 2005213479A JP 4751121 B2 JP4751121 B2 JP 4751121B2
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- connection pad
- element connection
- solder
- wiring board
- wiring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
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Description
本発明は配線基板に関し、より詳細には、例えばペリフェラル型の半導体集積回路素子をフリップチップ接続により搭載するのに好適な配線基板に関する。 The present invention relates to a wiring board, and more particularly to a wiring board suitable for mounting, for example, a peripheral type semiconductor integrated circuit element by flip chip connection.
従来から、半導体集積回路素子として、多数の電極端子を、その一方の主面の外周に沿って配設した、いわゆるペリフェラル型の半導体集積回路素子がある。このような半導体集積回路素子を配線基板に搭載する方法として、フリップチップ接続により接続する方法がある。フリップチップ接続とは、配線基板上に設けた半導体素子接続用の配線導体の一部を半導体集積回路素子の電極端子の配置に対応した並びに露出させ、この半導体素子接続用の配線導体の露出部と前記半導体集積回路素子の電極端子とを対向させ、これらを例えば半田バンプを介して電気的に接続する方法である。 2. Description of the Related Art Conventionally, as a semiconductor integrated circuit element, there is a so-called peripheral type semiconductor integrated circuit element in which a large number of electrode terminals are arranged along the outer periphery of one main surface thereof. As a method of mounting such a semiconductor integrated circuit element on a wiring board, there is a method of connecting by flip chip connection. Flip-chip connection means that a part of a wiring conductor for connecting a semiconductor element provided on a wiring board is exposed corresponding to the arrangement of electrode terminals of a semiconductor integrated circuit element, and an exposed portion of the wiring conductor for connecting a semiconductor element is exposed. And electrode terminals of the semiconductor integrated circuit element are opposed to each other, and are electrically connected through, for example, solder bumps.
図７は、ペリフェラル型の半導体集積回路素子をフリップチップ接続により搭載する従来の配線基板を示す概略断面図であり、図８は、図７の配線基板を示す平面図である。図７および図８に示すように、従来の配線基板１２０は、上面から下面にかけて第一の配線導体１０２が配設された絶縁基板１０３の上下面に絶縁層１０４と第二の配線導体１０５とが交互に積層され、さらに、その最表面には保護用のソルダーレジスト層１０６が被着されている。 FIG. 7 is a schematic cross-sectional view showing a conventional wiring board on which peripheral type semiconductor integrated circuit elements are mounted by flip-chip connection, and FIG. 8 is a plan view showing the wiring board of FIG. As shown in FIGS. 7 and 8, the conventional wiring board 120 includes an insulating layer 104 and a second wiring conductor 105 on the upper and lower surfaces of the insulating board 103 on which the first wiring conductor 102 is disposed from the upper surface to the lower surface. Are stacked alternately, and a protective solder resist layer 106 is deposited on the outermost surface.
絶縁基板１０３の上面から下面にかけては複数のスルーホール１０７が形成されており、絶縁基板１０３の上下面およびスルーホール１０７の内面には第一の配線導体１０２が被着され、スルーホール１０７の内部には埋め込み樹脂１０８が充填されている。絶縁層１０４には、それぞれに複数のビアホール１０９が形成されており、各絶縁層１０４の表面およびビアホール１０９の内面には、第二の配線導体１０５がそれぞれ被着形成されている。 A plurality of through holes 107 are formed from the upper surface to the lower surface of the insulating substrate 103, and the first wiring conductor 102 is attached to the upper and lower surfaces of the insulating substrate 103 and the inner surface of the through hole 107. Is filled with embedded resin 108. A plurality of via holes 109 are respectively formed in the insulating layer 104, and second wiring conductors 105 are formed on the surface of each insulating layer 104 and the inner surface of the via hole 109, respectively.
そして、複数の第二の配線導体１０５のうち、配線基板１２０の上面側における最外層の絶縁層１０４上に被着された一部が、半導体集積回路素子１０１の電極端子１０１ａに半田バンプ１１０を介して電気的に接続される半導体素子接続用の帯状配線導体１０５ａを構成し、この帯状配線導体１０５ａのうち、ソルダーレジスト層１０６から露出した素子接続パッド１０５ａｐに、半導体集積回路素子１０１の電極端子１０１ａが半田バンプ１１０を介して電気的に接続される。また、配線基板１２０の下面側における最外層の絶縁層１０４上に被着された一部が、外部電気回路基板の配線導体に電気的に接続される外部接続用の配線導体１０５ｂを構成し、この外部接続用の配線導体１０５ｂのうち、ソルダーレジスト層１０６から露出した外部接続パッド１０５ｂｐに、外部電気回路基板の配線導体が半田ボール１１１を介して電気的に接続される。 A part of the plurality of second wiring conductors 105 deposited on the outermost insulating layer 104 on the upper surface side of the wiring substrate 120 has solder bumps 110 applied to the electrode terminals 101 a of the semiconductor integrated circuit element 101. A strip-shaped wiring conductor 105a for connecting a semiconductor element electrically connected to each other is formed, and an electrode terminal of the semiconductor integrated circuit element 101 is connected to an element connection pad 105ap exposed from the solder resist layer 106 of the strip-shaped wiring conductor 105a. 101 a is electrically connected via the solder bump 110. In addition, a part of the lower surface side of the wiring board 120 that is deposited on the outermost insulating layer 104 constitutes a wiring conductor 105b for external connection that is electrically connected to the wiring conductor of the external electric circuit board, Of the wiring conductor 105b for external connection, the wiring conductor of the external electric circuit board is electrically connected via the solder ball 111 to the external connection pad 105bp exposed from the solder resist layer 106.
ソルダーレジスト層１０６は、最外層の第二の配線導体１０５を保護するとともに素子接続パッド１０５ａｐや外部接続パッド１０５ｂｐを画定する。このようなソルダーレジスト層１０６は、感光性を有する熱硬化性樹脂ペーストまたはフィルムを第二の配線導体１０５が形成された最外層の絶縁層１０４上に積層したのち、素子接続パッド１０５ａｐや外部接続パッド１０５ｂｐを露出させる開口部を有するように露光および現像し、硬化させることにより形成される。 The solder resist layer 106 protects the outermost second wiring conductor 105 and defines the element connection pad 105ap and the external connection pad 105bp. Such a solder resist layer 106 is formed by laminating a thermosetting resin paste or film having photosensitivity on the outermost insulating layer 104 on which the second wiring conductor 105 is formed, and then the element connection pad 105ap or external connection. It is formed by exposing, developing and curing so as to have an opening for exposing the pad 105 bp.
なお、図８に示すように、上面側のソルダーレジスト層１０６は、素子接続パッド１０５ａｐを露出させるスリット状の開口部１０６ａを有しており、開口部１０６ａの幅に対応した長さで帯状配線導体１０５ａの一部を露出させることにより長方形状の素子接続パッド１０５ａｐを画定している。 As shown in FIG. 8, the solder resist layer 106 on the upper surface side has a slit-like opening 106a that exposes the element connection pad 105ap, and has a strip-like wiring having a length corresponding to the width of the opening 106a. A rectangular element connection pad 105ap is defined by exposing a part of the conductor 105a.
そして、この配線基板１２０においては、素子接続パッド１０５ａｐに予め半田バンプ１１０を形成しておき、半導体集積回路素子１０１の電極端子１０１ａと半田バンプ１１０を当接させた状態で加熱し、半田バンプ１１０を溶融させ、半導体集積回路素子１０１の電極端子１０１ａと素子接続パッド１０５ａｐとを半田バンプ１１０を介して電気的に接続する。ついで、半導体集積回路素子１０１と配線基板１２０との間の隙間にエポキシ樹脂等の熱硬化性樹脂から成るアンダーフィルと呼ばれる充填樹脂（不図示）を充填し、半導体集積回路素子１０１が配線基板１２０上に実装される。 In this wiring board 120, solder bumps 110 are formed in advance on the element connection pads 105 ap and heated in a state where the electrode terminals 101 a of the semiconductor integrated circuit element 101 and the solder bumps 110 are in contact with each other. The electrode terminal 101a of the semiconductor integrated circuit element 101 and the element connection pad 105ap are electrically connected via the solder bump 110. Next, a gap between the semiconductor integrated circuit element 101 and the wiring board 120 is filled with a filling resin (not shown) made of a thermosetting resin such as an epoxy resin so that the semiconductor integrated circuit element 101 is connected to the wiring board 120. Implemented above.
ここで、素子接続パッド１０５ａｐに半田バンプ１１０を形成するには、ソルダーレジスト層１０６から露出する素子接続パッド１０５ａｐの表面にペースト状あるいは粒状の半田を付着させた後、これを加熱して半田を溶融させ、溶融した半田を素子接続パッド１０５ａｐの露出表面に濡れ広がらせるとともに、溶融した半田の表面張力により素子接続パッド１０５ａｐ上に半田の溜まりを形成する方法が採用されている。このような方法で形成される半田バンプ１１０のうち、前記半田の溜まりを介して電極端子１０１ａと素子接続パッド１０５ａｐとが電気的に接続される。 Here, in order to form the solder bump 110 on the element connection pad 105ap, paste or granular solder is attached to the surface of the element connection pad 105ap exposed from the solder resist layer 106, and then the solder is heated to heat the solder. A method is adopted in which the molten solder is wetted and spread on the exposed surface of the element connection pad 105ap, and a pool of solder is formed on the element connection pad 105ap by the surface tension of the molten solder. Of the solder bumps 110 formed by such a method, the electrode terminal 101a and the element connection pad 105ap are electrically connected via the solder pool.
しかしながら、従来の配線基板１２０では、ソルダーレジスト層１０６から露出する素子接続パッド１０５ａｐは長方形状であるので、この素子接続パッド１０５ａｐに半田バンプ１１０を形成する際には、溶融した半田の表面張力が一点に集中し難く、形成される半田の溜まりの位置にばらつきが発生してしまう。その結果、半導体集積回路素子１０１の電極端子１０１ａと配線基板１２０の素子接続パッド１０５ａｐとを半田バンプ１１０を介して電気的に接続する際には、半導体集積回路素子１０１の電極端子１０１ａと半田バンプ１１０との全てを良好に当接させることができず、半導体集積回路素子１０１の電極端子１０１ａと配線基板１２０の素子接続パッド１０５ａｐとを半田バンプ１１０を介して信頼性高く接続することができないという問題点を有していた。 However, in the conventional wiring substrate 120, the element connection pad 105ap exposed from the solder resist layer 106 is rectangular, and therefore when the solder bump 110 is formed on the element connection pad 105ap, the surface tension of the molten solder is reduced. It is difficult to concentrate on one point, and variations occur in the position of the solder pool to be formed. As a result, when the electrode terminal 101a of the semiconductor integrated circuit element 101 and the element connection pad 105ap of the wiring substrate 120 are electrically connected via the solder bump 110, the electrode terminal 101a of the semiconductor integrated circuit element 101 and the solder bump 110 cannot be brought into good contact with each other, and the electrode terminals 101a of the semiconductor integrated circuit element 101 and the element connection pads 105ap of the wiring board 120 cannot be reliably connected via the solder bumps 110. Had problems.
そこで、例えば特許文献１では、接続パッドよりも幅寸法の狭い配線パターンを接続パッドと連続的に形成し、接続パッドおよび配線パターンをソルダーレジストから露出させるとともに、露出した接続パッドおよび配線パターンに半田を付着させ、これを加熱して半田を溶融させることにより、幅が広い接続パッド上に半田の瘤を形成する基板が提案されている。 Therefore, for example, in Patent Document 1, a wiring pattern having a width smaller than that of the connection pad is continuously formed with the connection pad, the connection pad and the wiring pattern are exposed from the solder resist, and the exposed connection pad and wiring pattern are soldered. A substrate is proposed in which a solder bump is formed on a wide connection pad by adhering and heating this to melt the solder.
しかしながら、特許文献１に記載されているような基板は、接続パッドの幅寸法よりも狭い幅寸法の配線パターンがソルダーレジストで覆われずに露出した状態となる。このような幅寸法の狭い配線パターンがソルダーレジストで覆われずに露出している構成である場合には、該配線パターンに剥がれが発生し易いとともに、外部環境の水分や異物等の影響を受け易くなるので、隣接する配線パターン間の電気的な絶縁信頼性が低下してしまうという問題がある。
本発明の課題は、素子接続パッドの中央部に半田の溜まりを有する半田バンプが良好に形成され、それにより半導体集積回路素子の電極端子と素子接続パッドとを半田バンプを介して接続信頼性高く接続することができるとともに、素子接続パッドが形成された帯状配線導体に剥がれが発生し難く、かつ隣接する帯状配線導体間の電気的な絶縁信頼性に優れる配線基板を提供することである。 An object of the present invention is that a solder bump having a solder pool is satisfactorily formed in the center portion of an element connection pad, thereby connecting the electrode terminal of the semiconductor integrated circuit element and the element connection pad through the solder bump with high reliability. It is an object of the present invention to provide a wiring board that can be connected, is less likely to be peeled off from a strip-shaped wiring conductor on which element connection pads are formed, and is excellent in electrical insulation reliability between adjacent strip-shaped wiring conductors.
本発明者らは、上記課題を解決すべく鋭意検討を重ねた結果、半導体素子接続用の帯状配線導体の一部として形成された素子接続パッドの幅寸法をその両端から中央部へ向けて徐々に広くするとともに、前記帯状配線導体を前記素子接続パッドの少なくとも両端までソルダーレジスト層で覆うことにより、素子接続パッド上に半田を付着させた後、該半田を加熱溶融させると、素子接続パッドの中央部に半田の溜まりを有する半田バンプを良好に形成することができるとともに、帯状配線導体に剥離が発生しにくく、かつ隣接する帯状配線導体間の絶縁信頼性に優れた配線基板が得られるという新たな知見を見出し、本発明を完成するに至った。 As a result of intensive studies to solve the above-mentioned problems, the present inventors have gradually increased the width dimension of the element connection pad formed as a part of the strip-shaped wiring conductor for connecting the semiconductor element from the both ends toward the center. And by covering the strip-shaped wiring conductor with at least both ends of the element connection pad with a solder resist layer so that solder is deposited on the element connection pad, and then the solder is heated and melted, It is possible to form a solder bump having a solder pool in the center part, to obtain a wiring board that is less likely to be peeled off from the strip-shaped wiring conductor and excellent in insulation reliability between adjacent strip-shaped wiring conductors. The inventors have found new knowledge and have completed the present invention.
すなわち、本発明における配線基板は、以下の構成からなる。
（1）絶縁層と配線導体とが交互に積層されており、最外層の絶縁層上に半導体素子接続用の帯状配線導体が複数並んで形成されているとともに、該帯状配線導体の一部に半導体素子の電極端子がフリップチップ接続される素子接続パッドが前記帯状配線導体の延びる方向に縦長の形状で前記帯状配線導体の幅方向に並んで複数形成されており、かつ前記最外層の絶縁層上および前記帯状配線導体上に、該帯状配線導体を横切って前記素子接続パッドを露出させるスリット状の開口部を有するソルダーレジスト層が被着されている配線基板であって、前記素子接続パッドはその幅寸法がその両端から中央部に向けて徐々に広くなっているとともに、前記ソルダーレジスト層は前記帯状配線導体を前記素子接続パッドの少なくとも両端まで覆っていることを特徴とする配線基板。
（2）前記素子接続パッドは、前記中央部の幅寸法が前記ソルダーレジスト層の開口部から露出した位置での素子接続パッドの幅寸法よりも１〜１０μｍ広いことを特徴とする前記（１）記載の配線基板。
（3）前記素子接続パッドに、該素子接続パッドの中央部に半田の溜まりを有する半田バンプが形成されていることを特徴とする前記（１）または（２）に記載の配線基板。
（4）前記素子接続パッドは、その両端間の辺を複数の直線の組み合わせとすることでその幅寸法がその両端から中央部に向けて徐々に広くなっていることを特徴とする前記（１）乃至（３）の何れかに記載の配線基板。
（5）前記素子接続パッドの幅寸法の最も広い部位が千鳥状の並びになっていることを特徴とする前記（１）乃至（４）の何れかに記載の配線基板。
That is, the wiring board in the present invention has the following configuration.
(1) Insulating layers and wiring conductors are alternately stacked, and a plurality of strip-like wiring conductors for connecting semiconductor elements are formed side by side on the outermost insulating layer, and part of the strip-like wiring conductors A plurality of element connection pads to which the electrode terminals of the semiconductor element are flip-chip connected are formed in a longitudinally long shape in the extending direction of the strip-shaped wiring conductor and aligned in the width direction of the strip-shaped wiring conductor , and the outermost insulating layer A wiring board on which a solder resist layer having a slit-like opening that exposes the element connection pad across the band-shaped wiring conductor is deposited on and on the band-shaped wiring conductor , wherein the element connection pad is The width dimension gradually increases from both ends toward the center, and the solder resist layer covers the strip-shaped wiring conductor to at least both ends of the element connection pad. A wiring board characterized by comprising:
(2) The element connection pad is characterized in that the width dimension of the central portion is 1 to 10 μm wider than the width dimension of the element connection pad at the position exposed from the opening of the solder resist layer. The wiring board described.
(3) The wiring board according to (1) or (2), wherein a solder bump having a pool of solder is formed at a central portion of the element connection pad.
(4) The element connection pad is characterized in that the width dimension is gradually widened from the both ends toward the central portion by combining the sides between the ends with a plurality of straight lines. The wiring board according to any one of (3) to (3).
(5) The wiring board according to any one of (1) to (4), wherein the widest part of the element connection pad has a staggered arrangement.
本発明の配線基板によれば、素子接続パッドは前記両端から中央部に向けてその幅寸法が徐々に広くなっているので、この素子接続パッド上に半田を付着させた後、該半田を加熱溶融させると、溶融した半田はその表面張力により素子接続パッドの幅寸法が広くなった中央部に集まってくるので、素子接続パッドの中央部に半田の溜まりを有する半田バンプが良好に形成される。したがって、本発明の配線基板によれば、半導体集積回路素子の電極端子と素子接続パッドとを半田バンプを介して接続する際、半導体集積回路素子の電極端子と半田バンプとが良好に当接し、その結果、半導体集積回路素子の電極端子と素子接続パッドとを半田バンプを介して信頼性高く接続することができる。また、ソルダーレジスト層は帯状配線導体を素子接続パッドの少なくとも両端まで覆っていることから、帯状配線導体に剥離が発生し難く、かつ隣接する帯状配線導体間の絶縁信頼性に優れた配線基板となる。 According to the wiring board of the present invention, since the element connection pad gradually increases in width from the both ends toward the center, the solder is attached to the element connection pad, and then the solder is heated. When melted, the melted solder gathers in the center part where the width dimension of the element connection pad is widened by the surface tension, so that a solder bump having a solder pool is formed well in the center part of the element connection pad. . Therefore, according to the wiring board of the present invention, when the electrode terminal of the semiconductor integrated circuit element and the element connection pad are connected via the solder bump, the electrode terminal of the semiconductor integrated circuit element and the solder bump are in good contact, As a result, the electrode terminal of the semiconductor integrated circuit element and the element connection pad can be connected with high reliability via the solder bump. In addition, since the solder resist layer covers the strip-shaped wiring conductor to at least both ends of the element connection pad, it is difficult for the strip-shaped wiring conductor to peel off, and the wiring board has excellent insulation reliability between adjacent strip-shaped wiring conductors. Become.
以下、本発明にかかる配線基板の一実施形態について図面を参照して詳細に説明する。図１は、ペリフェラル型の半導体集積回路素子をフリップチップ接続により搭載する本実施形態にかかる配線基板を示す概略断面図であり、図２は、図１の配線基板を示す平面図である。また図３は、図２のソルダーレジスト層の開口部付近を示す拡大平面図である。 Hereinafter, an embodiment of a wiring board according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic cross-sectional view showing a wiring board according to the present embodiment on which peripheral type semiconductor integrated circuit elements are mounted by flip-chip connection, and FIG. 2 is a plan view showing the wiring board of FIG. FIG. 3 is an enlarged plan view showing the vicinity of the opening of the solder resist layer of FIG.
図１，図２に示すように、本実施形態にかかる配線基板１０は、上面から下面にかけて第一の配線導体２が配設された絶縁基板３の上下面に絶縁層４と第二の配線導体５とが交互に積層され、さらに、その最表面には保護用のソルダーレジスト層６が被着されて成る。 As shown in FIGS. 1 and 2, the wiring substrate 10 according to the present embodiment includes an insulating layer 4 and a second wiring on the upper and lower surfaces of the insulating substrate 3 on which the first wiring conductor 2 is disposed from the upper surface to the lower surface. Conductors 5 are alternately stacked, and a protective solder resist layer 6 is deposited on the outermost surface.
絶縁基板３は、厚みが０．３〜１．５ｍｍ程度であり、例えばガラス繊維束を縦横に織ったガラスクロスにビスマレイミドトリアジン樹脂やエポキシ樹脂等の熱硬化性樹脂を含浸させた電気絶縁材料から成り、配線基板１０のコア部材として機能する。 The insulating substrate 3 has a thickness of about 0.3 to 1.5 mm. For example, an electrically insulating material obtained by impregnating a glass cloth in which glass fiber bundles are woven vertically and horizontally with a thermosetting resin such as bismaleimide triazine resin or epoxy resin. And functions as a core member of the wiring board 10.
絶縁基板３には、その上面から下面にかけて直径が０．０５〜０．３ｍｍ程度の複数のスルーホール７が形成されており、絶縁基板３の上下面およびスルーホール７の内面には、第一の配線導体２が被着されている。第一の配線導体２は、絶縁基板３の上下面では、主として銅箔から形成されており、スルーホール７内面では、無電解銅めっきおよびその上の電解銅めっきから形成されている。 A plurality of through holes 7 having a diameter of about 0.05 to 0.3 mm are formed in the insulating substrate 3 from the upper surface to the lower surface. The wiring conductor 2 is attached. The first wiring conductor 2 is mainly formed of copper foil on the upper and lower surfaces of the insulating substrate 3, and is formed of electroless copper plating and electrolytic copper plating thereon on the inner surface of the through hole 7.
また、スルーホール７内部には、エポキシ樹脂等の熱硬化性樹脂から成る埋め込み樹脂８が充填されており、絶縁基板３の上下面に形成された第一の配線導体２同士がスルーホール７内の第一の配線導体２を介して電気的に接続されている。 The through hole 7 is filled with an embedded resin 8 made of a thermosetting resin such as an epoxy resin, and the first wiring conductors 2 formed on the upper and lower surfaces of the insulating substrate 3 are in the through hole 7. The first wiring conductor 2 is electrically connected.
このような絶縁基板３は、ガラス織物に未硬化の熱硬化性樹脂を含浸させたシートの上下面に第一の配線導体２用の銅箔を貼着した後、そのシートを熱硬化させ、これに上面から下面にかけてスルーホール７用のドリル加工を施すことにより製作される。 Such an insulating substrate 3 is formed by sticking a copper foil for the first wiring conductor 2 on the upper and lower surfaces of a sheet of glass fabric impregnated with an uncured thermosetting resin, and then thermally curing the sheet. This is manufactured by drilling through holes 7 from the upper surface to the lower surface.
第一の配線導体２は、絶縁基板３用のシートの上下全面に、厚みが３〜５０μｍ程度の銅箔を上述のように貼着しておくとともに、これらの銅箔および絶縁基板３にスルーホール７を穿孔した後、このスルーホール7の内面および銅箔表面に無電解銅めっきおよび電解銅めっきを順次施し、次にスルーホール７内を埋め込み樹脂８で充填した後、この上下面の銅箔および銅めっきをフォトリソグラフィ技術を用いて所定のパターンにエッチング加工することにより絶縁基板３の上下面およびスルーホール７の内面に形成される。 The first wiring conductor 2 has a copper foil having a thickness of about 3 to 50 μm adhered to the entire upper and lower surfaces of the sheet for the insulating substrate 3 as described above, and through the copper foil and the insulating substrate 3. After the hole 7 is drilled, the inner surface of the through hole 7 and the surface of the copper foil are sequentially subjected to electroless copper plating and electrolytic copper plating, and the inside of the through hole 7 is filled with the embedded resin 8. The foil and the copper plating are etched into a predetermined pattern using a photolithography technique to form the upper and lower surfaces of the insulating substrate 3 and the inner surface of the through hole 7.
埋め込み樹脂８は、スルーホール７を塞ぐことによりスルーホール７の直上および直下に絶縁層４を形成可能とするためのものであり、未硬化のペースト状の熱硬化性樹脂をスルーホール７内にスクリーン印刷法により充填し、これを熱硬化させた後、その上下面を略平坦に研磨することにより形成される。 The embedded resin 8 is used to form the insulating layer 4 immediately above and below the through hole 7 by closing the through hole 7, and an uncured paste-like thermosetting resin is placed in the through hole 7. After filling with a screen printing method and thermosetting it, the upper and lower surfaces thereof are polished to be substantially flat.
絶縁基板３の上下面に積層された絶縁層４は、それぞれの厚みが２０〜６０μｍ程度であり、絶縁基板３と同様にガラスクロスに熱硬化性樹脂を含浸させた電気絶縁材料や、あるいはエポキシ樹脂等の熱硬化性樹脂に酸化ケイ素等の無機フィラーを分散させた電気絶縁材料から成る。また、各絶縁層４には、直径が３０〜１００μｍ程度の複数のビアホール９が形成されている。 The insulating layers 4 laminated on the upper and lower surfaces of the insulating substrate 3 each have a thickness of about 20 to 60 μm. Similarly to the insulating substrate 3, an electric insulating material in which a glass cloth is impregnated with a thermosetting resin, or an epoxy It consists of an electrically insulating material in which an inorganic filler such as silicon oxide is dispersed in a thermosetting resin such as a resin. Each insulating layer 4 is formed with a plurality of via holes 9 having a diameter of about 30 to 100 μm.
各絶縁層４の表面およびビアホール９内面には、無電解銅めっきおよびその上の電解銅めっきから成る第二の配線導体５が被着形成されている。そして、絶縁層４を挟んで上層に位置する配線導体５と下層に位置する配線導体５とをビアホール９内の配線導体５を介して電気的に接続することにより高密度配線が立体的に形成される。 A second wiring conductor 5 made of electroless copper plating and electrolytic copper plating thereon is deposited on the surface of each insulating layer 4 and the inner surface of the via hole 9. Then, the wiring conductor 5 located in the upper layer and the wiring conductor 5 located in the lower layer are electrically connected via the wiring conductor 5 in the via hole 9 with the insulating layer 4 interposed therebetween, thereby forming a high-density wiring in three dimensions. Is done.
複数の第二の配線導体５のうち、配線基板１０の上面側における最外層の絶縁層４上に被着された一部が半導体集積回路素子１０１の電極１０１ａと半田等の半田バンプ１１０を介して電気的に接続される素子接続パッド５ａｐを有する半導体素子接続用の帯状配線導体５ａを形成し、配線基板１０の下面側における最外層の絶縁層４上に被着された一部が、外部電気回路基板の配線導体と電気的に接続される外部接続パッド５ｂｐを有する外部接続用の配線導体５ｂを形成する。 Among the plurality of second wiring conductors 5, a part of the second wiring conductor 5 deposited on the outermost insulating layer 4 on the upper surface side of the wiring substrate 10 is interposed via the electrodes 101 a of the semiconductor integrated circuit element 101 and solder bumps 110 such as solder. Forming a strip-like wiring conductor 5a for connecting a semiconductor element having an element connection pad 5ap that is electrically connected to each other, and a portion deposited on the outermost insulating layer 4 on the lower surface side of the wiring substrate 10 is externally connected. An external connection wiring conductor 5b having an external connection pad 5bp electrically connected to the wiring conductor of the electric circuit board is formed.
そして、半導体素子接続用の帯状配線導体５ａは、図２に示すように、半導体集積回路素子１０１の外周部に対応する位置を半導体集積回路素子１０１の外周辺に対して直角な方向に延びるようにして所定のピッチで複数並んで設けられており、その上には半導体集積回路素子１０１の電極端子１０１ａに対応する位置に、半田バンプ１１０が形成される素子接続パッド５ａｐが形成されている。 Then, as shown in FIG. 2, the strip-shaped wiring conductor 5a for connecting the semiconductor element extends at a position corresponding to the outer peripheral portion of the semiconductor integrated circuit element 101 in a direction perpendicular to the outer periphery of the semiconductor integrated circuit element 101. A plurality of element connection pads 5ap on which solder bumps 110 are formed are formed at positions corresponding to the electrode terminals 101a of the semiconductor integrated circuit element 101.
このような第二の配線導体５は、セミアディティブ法といわれる方法により形成される。セミアディティブ法は、例えば、ビアホール９が形成された絶縁層４の表面に電解めっき用の下地金属層を無電解銅めっきにより形成し、その上に第二の配線導体５に対応した開口を有するめっきレジスト層を形成し、次に、下地金属層を給電用の電極として開口から露出する下地金属層上に電解銅めっきを施し第二の配線導体５を形成し、めっきレジストを剥離した後、露出する下地金属層をエッチング除去することによって各第二の配線導体５を電気的に独立させる方法である。 Such a second wiring conductor 5 is formed by a method called a semi-additive method. In the semi-additive method, for example, a base metal layer for electrolytic plating is formed on the surface of the insulating layer 4 in which the via hole 9 is formed by electroless copper plating, and an opening corresponding to the second wiring conductor 5 is formed thereon. After forming the plating resist layer, and then applying the electrolytic copper plating on the base metal layer exposed from the opening as the power supply electrode as the base metal layer to form the second wiring conductor 5 and peeling the plating resist, This is a method in which each second wiring conductor 5 is electrically independent by etching away the exposed base metal layer.
そして、最外層の絶縁層４およびその上の第二の配線導体５上には、ソルダーレジスト層６が被着されている。該ソルダーレジスト層６は、最外層の第二の配線導体５を熱や外部環境から保護するための保護膜であり、上面側のソルダーレジスト層６は、素子接続パッド５ａｐを露出させるようにして、また下面側のソルダーレジスト層６は、外部接続パッド５ｂを露出させるようにして、それぞれ被着されている。 A solder resist layer 6 is deposited on the outermost insulating layer 4 and the second wiring conductor 5 thereon. The solder resist layer 6 is a protective film for protecting the outermost second wiring conductor 5 from heat and the external environment, and the solder resist layer 6 on the upper surface side exposes the element connection pads 5ap. Further, the solder resist layer 6 on the lower surface side is respectively deposited so as to expose the external connection pads 5b.
また、上面側のソルダーレジスト層６は、図２に示すように、素子接続パッド５ａｐを露出させるスリット状の開口部６ａを有しており、該開口部６ａの幅に対応した長さで帯状配線導体５ａの一部を露出させることにより所定形状の素子接続パッド５ａｐを画定している。 Further, as shown in FIG. 2, the solder resist layer 6 on the upper surface side has a slit-like opening 6a that exposes the element connection pad 5ap, and has a strip shape with a length corresponding to the width of the opening 6a. By exposing a part of the wiring conductor 5a, an element connection pad 5ap having a predetermined shape is defined.
ここで、本実施形態にかかる素子接続パッド５ａｐは、図３に示すように、その幅寸法がその両端から中央部に向けて徐々に広くなっている。これにより、該素子接続パッド５ａｐの上に半田を付着させた後、該半田を加熱溶融させると、溶融した半田はその表面張力により素子接続パッド５ａｐの中央部に集まってくるので、素子接続パッド５ａｐの中央部に半田の溜まりを有する半田バンプ１１０が良好に形成される。すなわち、この素子接続パッド５ａｐ上に形成される半田の溜まりは、素子接続パッド５ａｐの中央部に確実に形成されるので、半田の溜まりが形成される位置にばらつきが発生することがない。このため、該半田バンプ１１０を介して半導体集積回路素子１０１の電極端子１０１ａと素子接続パッド５ａｐとを電気的に接続する際には、半導体集積回路素子１０１の電極端子１０１ａと半田バンプ１１０とが良好に当接することができ、その結果、半導体集積回路素子１０１の電極端子１０１ａと素子接続パッド５ａｐとを半田バンプ１１０を介して信頼性高く接続することができる。 Here, as shown in FIG. 3, the element connection pad 5ap according to the present embodiment has a width that gradually increases from both ends toward the center. As a result, after the solder is deposited on the element connection pad 5ap and then heated and melted, the melted solder gathers at the center of the element connection pad 5ap due to its surface tension. A solder bump 110 having a solder pool at the center of 5 ap is formed satisfactorily. That is, the solder pool formed on the element connection pad 5ap is surely formed at the center of the element connection pad 5ap, so that no variation occurs in the position where the solder pool is formed. Therefore, when the electrode terminal 101a of the semiconductor integrated circuit element 101 and the element connection pad 5ap are electrically connected via the solder bump 110, the electrode terminal 101a of the semiconductor integrated circuit element 101 and the solder bump 110 are connected to each other. As a result, the electrode terminals 101a of the semiconductor integrated circuit element 101 and the element connection pads 5ap can be connected with high reliability via the solder bumps 110.
さらに、本実施形態にかかるソルダーレジスト層６は、半導体素子接続用の帯状配線導体５ａを素子接続パッド５ａｐの少なくとも両端まで覆っている。これにより、帯状配線導体５ａは素子接続パッド５ａｐと連続する部分の幅寸法が狭いものであったとしても、その剥離がソルダーレジスト層６により有効に防止されるとともに、隣接する帯状配線導体５ａ間における電気的な絶縁信頼性が高いものとなる。 Furthermore, the solder resist layer 6 according to the present embodiment covers the strip-shaped wiring conductor 5a for connecting the semiconductor element to at least both ends of the element connection pad 5ap. As a result, even if the strip-like wiring conductor 5a has a narrow width dimension in the portion continuous with the element connection pad 5ap, the peeling is effectively prevented by the solder resist layer 6, and the strip-like wiring conductor 5a is adjacent to each other. In this case, the electrical insulation reliability is high.
具体的には、素子接続パッド５ａｐは、その中央部にける幅寸法Ｗ１がソルダーレジスト層６の開口部６ａから露出した位置での素子接続パッド５ａｐの幅寸法Ｗ２よりも１〜１０μｍ広いことが好ましい。前記幅寸法Ｗ１と幅寸法Ｗ２との関係が、このような構成となるようにソルダーレジスト層６を被覆すると、溶融した半田がその表面張力で素子接続パッド５ａｐの中央部に確実に集まってくるので、所定の半田バンプ１１０を形成することができる。これに対し、前記幅寸法Ｗ１と幅寸法Ｗ２との差が１μｍ未満であれば、素子接続パッド５ａｐ上に半田を付着させた後、該半田を加熱溶融させた場合に、溶融した半田がその表面張力により素子接続パッド５ａｐの中央部に集まる力が弱くなり、素子接続パッド５ａｐの中央部に半田の溜まりを有する半田バンプ１１０を良好に形成することが困難となる傾向にあり、他方、１０μｍを超えると、帯状配線導体５ａを高密度で形成することが困難となる。 Specifically, the element connection pad 5ap is wider by 1 to 10 μm than the width dimension W2 of the element connection pad 5ap at the position where the width dimension W1 at the center is exposed from the opening 6a of the solder resist layer 6. preferable. When the solder resist layer 6 is coated so that the relationship between the width dimension W1 and the width dimension W2 has such a configuration, the molten solder is surely collected at the center of the element connection pad 5ap by its surface tension. Therefore, the predetermined solder bump 110 can be formed. On the other hand, if the difference between the width dimension W1 and the width dimension W2 is less than 1 μm, when the solder is adhered to the element connection pad 5ap and then the solder is heated and melted, The force gathered at the central portion of the element connection pad 5ap is weakened by the surface tension, and it tends to be difficult to satisfactorily form the solder bump 110 having a pool of solder at the central portion of the element connection pad 5ap. If it exceeds the upper limit, it becomes difficult to form the strip-shaped wiring conductor 5a at a high density.
上記のような素子接続パッド５ａｐ上に半田バンプ１１０を形成し、該半田バンプ１１０に半導体集積回路素子１０１の電極端子１０１ａを当接させた状態で加熱し、半田バンプ１１０を溶融させると、半導体集積回路素子１０１の電極端子１０１ａと素子接続パッド５ａｐとが半田バンプ１１０を介して電気的に接続される。ここで、素子接続パッド５ａｐは所定形状に構成されているので、その中央部に半田の溜まりを有する半田バンプ１１０が良好に形成され、半導体集積回路素子１０１の電極端子１０１ａと素子接続パッド５ａｐとが該半田バンプ１１０を介して接続信頼性高く接続される。さらに、ソルダーレジスト層６が所定位置で被覆しているので、素子接続パッド５ａｐが形成された帯状配線導体５ａに剥がれが発生し難く、かつ隣接する帯状配線導体５ａ間の電気的な絶縁信頼性が優れたものとなる。 When the solder bumps 110 are formed on the element connection pads 5ap as described above, the solder bumps 110 are heated while the electrode terminals 101a of the semiconductor integrated circuit element 101 are in contact with the solder bumps 110, and the solder bumps 110 are melted. The electrode terminal 101 a of the integrated circuit element 101 and the element connection pad 5 ap are electrically connected via the solder bump 110. Here, since the element connection pad 5ap is configured in a predetermined shape, a solder bump 110 having a pool of solder is satisfactorily formed at the center thereof, and the electrode terminals 101a and the element connection pads 5ap of the semiconductor integrated circuit element 101 are formed. Are connected with high connection reliability through the solder bumps 110. Further, since the solder resist layer 6 is coated at a predetermined position, the strip-shaped wiring conductor 5a on which the element connection pad 5ap is formed is not easily peeled off, and the electrical insulation reliability between the adjacent strip-shaped wiring conductors 5a. Will be excellent.
そして、半導体集積回路素子１０１と配線基板１０との間の隙間にエポキシ樹脂等の熱硬化性樹脂から成るアンダーフィルと呼ばれる充填樹脂（不図示）を充填し、半導体集積回路素子１０１が配線基板１０上に実装される。 A gap between the semiconductor integrated circuit element 101 and the wiring substrate 10 is filled with a filling resin (not shown) called an underfill made of a thermosetting resin such as an epoxy resin. Implemented above.
なお、本発明は、上述の実施の形態例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能であり、例えば上述の実施形態例では、素子接続パッド５ａｐの両端間の辺を円弧状の曲線とすることで素子接続パッド５ａｐの幅寸法を両端から中央部に向けて徐々に広くなるようにしたが、例えば図４や図５に示すように、素子接続パッド５ａｐの両端間の辺を複数の直線の組み合わせとすることで素子接続パッド５ａｐの幅寸法が両端から中央部に向けて徐々に広くなるようにしてもよい。 The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. For example, in the above-described embodiment, the element connection pad The width of the element connection pad 5ap is gradually widened from both ends toward the center by making the sides between both ends of the 5ap into an arcuate curve. For example, as shown in FIGS. The width between the both ends of the element connection pad 5ap may be a combination of a plurality of straight lines so that the width dimension of the element connection pad 5ap gradually increases from both ends toward the center.
また、上述の実施の形態例では、素子接続パッド５ａｐの幅寸法が最も広い部位が直線状の並びとなるように各素子接続パッド５ａｐを形成したが、例えば図６に示すように、素子接続パッド５ａｐの幅寸法が最も広い部位が千鳥状の並びとなるように各素子接続パッド５ａｐを形成してもよい。この場合には、隣接する素子接続パッド５ａｐ間の間隔を広くすることができるので、素子接続パッド５ａｐをより高密度に配設することができる。 In the above-described embodiment, each element connection pad 5ap is formed so that the parts having the widest width dimension of the element connection pad 5ap are arranged in a straight line. For example, as shown in FIG. The element connection pads 5ap may be formed so that the portions having the widest width of the pads 5ap are arranged in a staggered pattern. In this case, since the interval between the adjacent element connection pads 5ap can be widened, the element connection pads 5ap can be arranged with higher density.
２ 第一の配線導体
３ 絶縁基板
４ 絶縁層
５ 第二の配線導体
５ａ 半導体素子接続用の帯状配線導体
５ａｐ 素子接続パッド
５ｂ 外部接続用の配線導体
５ｂｐ 外部接続パッド
６ ソルダーレジスト層
７ スルーホール
８ 埋め込み樹脂
９ ビアホール
１０ 配線基板
１０１ 半導体集積回路素子
１１０ 半田バンプ
１１１ 半田ボール
DESCRIPTION OF SYMBOLS 2 1st wiring conductor 3 Insulation board | substrate 4 Insulating layer 5 2nd wiring conductor 5a Strip | belt-shaped wiring conductor for semiconductor element connection 5ap Element connection pad 5b Wiring conductor for external connection 5bp External connection pad 6 Solder resist layer 7 Through hole 8 Embedded resin 9 Via hole 10 Wiring board 101 Semiconductor integrated circuit element 110 Solder bump 111 Solder ball
Claims (5)
前記素子接続パッドはその幅寸法がその両端から中央部に向けて徐々に広くなっているとともに、前記ソルダーレジスト層は前記帯状配線導体を前記素子接続パッドの少なくとも両端まで覆っていることを特徴とする配線基板。 Insulating layers and wiring conductors are alternately laminated, and a plurality of strip-shaped wiring conductors for connecting semiconductor elements are formed side by side on the outermost insulating layer, and a part of the strip-shaped wiring conductors is provided A plurality of element connection pads to which the electrode terminals are flip-chip connected are formed in a vertically long shape in the extending direction of the strip-shaped wiring conductor and arranged in the width direction of the strip-shaped wiring conductor , and on the outermost insulating layer and the A wiring board on which a solder resist layer having a slit-like opening that exposes the element connection pad across the band- shaped wiring conductor is deposited on the band-shaped wiring conductor ,
The element connection pad has a width that gradually increases from both ends toward the center, and the solder resist layer covers the strip-shaped wiring conductor to at least both ends of the element connection pad. Wiring board to be used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005213479A JP4751121B2 (en) | 2005-07-22 | 2005-07-22 | Wiring board |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005213479A JP4751121B2 (en) | 2005-07-22 | 2005-07-22 | Wiring board |
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| Publication Number | Publication Date |
|---|---|
| JP2007035731A JP2007035731A (en) | 2007-02-08 |
| JP4751121B2 true JP4751121B2 (en) | 2011-08-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP6467797B2 (en) * | 2014-07-14 | 2019-02-13 | 凸版印刷株式会社 | WIRING BOARD, SEMICONDUCTOR DEVICE USING WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME |
| JP6356625B2 (en) * | 2015-03-25 | 2018-07-11 | 京セラ株式会社 | Surface acoustic wave device |
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| JPH1022413A (en) * | 1996-07-08 | 1998-01-23 | Hitachi Ltd | Wiring board, manufacture of semiconductor device using it and mounting method thereof |
| JP3442648B2 (en) * | 1998-03-12 | 2003-09-02 | 株式会社日立製作所 | Ball grid array type semiconductor device |
| JP3420076B2 (en) * | 1998-08-31 | 2003-06-23 | 新光電気工業株式会社 | Method for manufacturing flip-chip mounting board, flip-chip mounting board, and flip-chip mounting structure |
| JP3581111B2 (en) * | 2001-05-01 | 2004-10-27 | 新光電気工業株式会社 | Semiconductor device mounting substrate and mounting structure |
| JP3915765B2 (en) * | 2003-10-03 | 2007-05-16 | 松下電器産業株式会社 | Joining method |
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